--- /dev/null
+The development team wants to acknowledge the following people:
+- STMicroelectronics discovery kit team for their low cost boards and for their help in development process.
\ No newline at end of file
m@capitanio.org
spen@spen-soft.co.uk
+texane@gmail.com
whitequark@whitequark.org
grestm@galexander.org
karlp@tweak.net.au
+++ /dev/null
-INSTALL
-=======
-
-1) Load the sg kernel module:
-
- $ modprobe sg
-
-2) On Ubuntu you need to install the package libsgutils2-dev:
-
- $ sudo apt-get install libsgutils2-dev
-
-3) Make:
-
- $ make -C build
-
-4) Install or reinstall
-
- $ sudo make install -C build
-
-5) Run:
-
- $ st-util port [/dev/sgX]
-or
- $ st-util [port]
-or
- $ st-util --help
-
-6) Have fun!
-
HOWTO
=====
-First, load the sg kernel module.
+First, you have to know there are several boards supported by the software.
+Those boards use a chip to translate from USB to JTAG commands. The chip is
+called stlink and there are 2 versions:
+. STLINKv1, present on STM32VL discovery kits,
+. STLINKv2, present on STM32L discovery and later kits.
+
+2 different transport layers are used:
+. STLINKv1 uses SCSI passthru commands over USB,
+. STLINKv2 uses raw USB commands.
+
+It means that if you are using a STM32VL board, you have to install and load
+SCSI related software. First, load the sg kernel module:
# modprobe sg
-On Ubuntu you need to install the package libsgutils2-dev:
+Then, you need to install the package libsgutils2-dev. On Ubuntu:
# sudo apt-get install libsgutils2-dev
+LIBUSB is required for both cases.
+
To run the gdb server, do (you do not need sudo if you have set up
permissions correctly):
-$ make -C build && sudo ./build/st-util 1234 /dev/sg1
+$ make -C build && sudo ./build/st-util [/dev/sgX]
+
+Currently, the GDB server listening port is hardcoded to 4242:
Then, in gdb:
-(gdb) target remote :1234
+(gdb) target remote :4242
Have fun!
You may reset the chip using GDB if you want. You'll need to use `target
extended-remote' command like in this session:
-(gdb) target extended-remote localhost:1111
-Remote debugging using localhost:1111
+(gdb) target extended-remote localhost:4242
+Remote debugging using localhost:4242
0x080007a8 in _startup ()
(gdb) kill
Kill the program being debugged? (y or n) y
(gdb) run
Starting program: /home/whitequark/ST/apps/bally/firmware.elf
-Remember that you can shorten the commands. `tar ext :1111' is good enough
+Remember that you can shorten the commands. `tar ext :4242' is good enough
for GDB.
Setting up udev rules
--- /dev/null
+. flash writing is not working from GDB
+add a standalone application, flash/
+
+. add a startup.S based example
+
+. remove libsg dependency using:
+https://github.com/afaerber/stlink/tree/master/libstlink
+
+. compile and test a realtime kernel, for instance:
+http://www.chibios.org/dokuwiki/doku.php?id=start
--- /dev/null
+\documentclass[a4paper, 11pt]{article}
+
+\usepackage{graphicx}
+\usepackage{graphics}
+\usepackage{verbatim}
+\usepackage{listings}
+\usepackage{color}
+
+\begin{document}
+
+\title{Using STM32 discovery kits with open source tools}
+\author{STLINK development team}
+\date{}
+
+\maketitle
+
+\newpage
+\tableofcontents
+\addtocontents{toc}{\protect\setcounter{tocdepth}{1}}
+
+
+\newpage
+
+\section{Overview}
+\paragraph{}
+This guide details the use of STMicroelectronics STM32 discovery kits in
+an opensource environment.
+
+
+\newpage
+
+\section{Installing a GNU toolchain}
+\paragraph{}
+Any toolchain supporting the cortex m3 should do. You can find the necessary
+to install such a toolchain here:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+https://github.com/esden/summon-arm-toolchain
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+Details for the installation are provided in the topmost README file.
+This documentation assumes the toolchains is installed in a \$TOOLCHAIN\_PATH.
+
+
+\newpage
+
+\section{Installing STLINK}
+\paragraph{}
+STLINK is an opensource software to program and debug the discovery kits. Those
+kits have an onboard chip that translates USB commands sent by the host PC into
+JTAG commands. This chip is called STLINK, which is confusing since the software
+has the same name. It comes into 2 versions (STLINK v1 and v2). From a software
+point of view, those versions differ only in the transport layer used to communicate
+(v1 uses SCSI passthru commands, while v2 uses raw USB).
+
+\paragraph{}
+Before continuing, the following dependencies are required:
+\begin{itemize}
+\item libusb-1.0
+\item libsg2
+\end{itemize}
+
+\paragraph{}
+The STLINK software source code is retrieved using:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+git clone https://github.com/texane/stlink stlink.git
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+The GDB server is called st-util and is built using:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> cd stlink.git;
+$> make ;
+$> cd gdbserver ;
+$> make ;
+\end{lstlisting}
+\end{small}
+
+
+\newpage
+
+\section{Building and running a program}
+A simple LED blinking example is provided in the example directory. It is built using:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+cd stlink.git/example/blink ;
+PATH=$TOOLCHAIN_PATH/bin:$PATH make ;
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+A GDB server must be start to interact with the STM32. Depending on the discovery kit you
+are using, you must run one of the 2 commands:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+# STM32VL discovery kit
+$> sudo ./st-util /dev/sg2
+
+# STM32L discovery kit
+$> sudo ./st-util
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+Then, GDB can be used to interact with the kit:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> $TOOLCHAIN_PATH/bin/arm-none-eabi-gdb
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+From GDB, connect to the server using:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> target extended localhost:4242
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+By default, the program was linked such that the base address is 0x20000000. From the architecture
+memory map, GDB knows this address belongs to SRAM. To load the program in SRAM, simply use:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> load blink.elf
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+GDB automatically set the PC register to the correct value, 0x20000000 in this case. Then, you
+can run the program using:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> continue
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+The board BLUE and GREEN leds should be blinking (those leds are near the user and reset buttons).
+
+
+\newpage
+\section{Notes}
+
+\subsection{Disassembling THUMB code in GDB}
+\paragraph{}
+By default, the disassemble command in GDB operates in ARM mode. The programs running on CORTEX-M3
+are compiled in THUMB mode. To correctly disassemble them under GDB, uses an odd address. For instance,
+if you want to disassemble the code at 0x20000000, use:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> disassemble 0x20000001
+\end{lstlisting}
+\end{small}
+
+
+\subsection{libstm32l\_discovery}
+\paragraph{}
+The repository includes the STM32L discovery library source code from ST original firmware packages,
+available here:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+http://www.st.com/internet/evalboard/product/250990.jsp#FIRMWARE
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+It is built using:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> cd stlink.git/example/libstm32l_discovery/build
+$> make
+\end{lstlisting}
+\end{small}
+
+\paragraph{}
+An example using the library can be built using:\\
+\begin{small}
+\begin{lstlisting}[frame=tb]
+$> cd stlink.git/example/lcd
+$> make
+\end{lstlisting}
+\end{small}
+
+\newpage
+\section{References}
+\begin{itemize}
+\item http://www.st.com/internet/mcu/product/248823.jsp\\
+ documentation related to the STM32L mcu
+\item http://www.st.com/internet/evalboard/product/250990.jsp\\
+ documentation related to the STM32L discovery kit
+\end{itemize}
+
+\end{document}
+++ /dev/null
-EXECUTABLE=blink.elf
-BIN_IMAGE=blink.bin
-
-CC=arm-none-eabi-gcc
-OBJCOPY=arm-none-eabi-objcopy
-
-CFLAGS=-O2 -mlittle-endian -mthumb
-CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
-
-all: $(BIN_IMAGE)
-
-$(BIN_IMAGE): $(EXECUTABLE)
- $(OBJCOPY) -O binary $^ $@
-
-$(EXECUTABLE): main.c
- $(CC) $(CFLAGS) $^ -o $@
-
-clean:
- rm -rf $(EXECUTABLE)
- rm -rf $(BIN_IMAGE)
-
-.PHONY: all clean
--- /dev/null
+EXECUTABLE=blink.elf
+BIN_IMAGE=blink.bin
+
+CC=arm-none-eabi-gcc
+OBJCOPY=arm-none-eabi-objcopy
+
+CFLAGS=-O2 -mlittle-endian -mthumb
+CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
+
+# to run from SRAM
+CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000
+
+# to write to flash then run
+# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000
+
+all: $(BIN_IMAGE)
+
+$(BIN_IMAGE): $(EXECUTABLE)
+ $(OBJCOPY) -O binary $^ $@
+
+$(EXECUTABLE): main.c
+ $(CC) $(CFLAGS) $^ -o $@
+
+clean:
+ rm -rf $(EXECUTABLE)
+ rm -rf $(BIN_IMAGE)
+
+.PHONY: all clean
--- /dev/null
+#!/usr/bin/env sh
+#/home/texane/sat/bin/arm-none-eabi-objdump -marm -Mforce-thumb -EL -b binary -D /tmp/barfoo
+/home/texane/sat/bin/arm-none-eabi-objdump -marm -EL -b binary -D /tmp/barfoo
--- /dev/null
+/* missing type */
+
+typedef unsigned int uint32_t;
+
+
+/* hardware configuration */
+
+#define CONFIG_STM32L_DISCOVERY 1
+#define CONFIG_STM32VL_DISCOVERY 0
+
+
+#if CONFIG_STM32VL_DISCOVERY
+
+# define GPIOC 0x40011000 /* port C */
+# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */
+# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */
+
+# define LED_BLUE (1 << 8) /* port C, pin 8 */
+# define LED_GREEN (1 << 9) /* port C, pin 9 */
+
+static inline void setup_leds(void)
+{
+ *(volatile uint32_t*)GPIOC_CRH = 0x44444411;
+}
+
+static inline void switch_leds_on(void)
+{
+ *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN;
+}
+
+static inline void switch_leds_off(void)
+{
+ *(volatile uint32_t*)GPIOC_ODR = 0;
+}
+
+#elif CONFIG_STM32L_DISCOVERY
+
+# define GPIOB 0x40020400 /* port B */
+# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */
+# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */
+
+# define LED_BLUE (1 << 6) /* port B, pin 6 */
+# define LED_GREEN (1 << 7) /* port B, pin 7 */
+
+static inline void setup_leds(void)
+{
+ /* configure port 6 and 7 as output */
+ *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2));
+}
+
+static inline void switch_leds_on(void)
+{
+ *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN;
+}
+
+static inline void switch_leds_off(void)
+{
+ *(volatile uint32_t*)GPIOB_ODR = 0;
+}
+
+#endif /* otherwise, error */
+
+
+#define delay() \
+do { \
+ register unsigned int i; \
+ for (i = 0; i < 1000000; ++i) \
+ __asm__ __volatile__ ("nop\n\t":::"memory"); \
+} while (0)
+
+static void __attribute__((naked)) __attribute__((used)) main(void)
+{
+ setup_leds();
+
+ while (1)
+ {
+ switch_leds_on();
+ delay();
+ switch_leds_off();
+ delay();
+ }
+}
+++ /dev/null
-#!/usr/bin/env sh
-#/home/texane/sat/bin/arm-none-eabi-objdump -marm -Mforce-thumb -EL -b binary -D /tmp/barfoo
-/home/texane/sat/bin/arm-none-eabi-objdump -marm -EL -b binary -D /tmp/barfoo
--- /dev/null
+ELF=lcd.elf
+
+CC=arm-none-eabi-gcc
+
+CFLAGS=-O2 -mlittle-endian -mthumb
+CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
+
+CFLAGS+=-I.
+
+# stm32l_discovery lib
+CFLAGS+=-I../libstm32l_discovery/inc
+CFLAGS+=-I../libstm32l_discovery/inc/base
+CFLAGS+=-I../libstm32l_discovery/inc/core_support
+CFLAGS+=-I../libstm32l_discovery/inc/device_support
+
+# to run from SRAM
+CFLAGS+=-Wl,-T,linker_stm32l.lds
+
+SRCS=\
+main.c\
+stm32l_discovery_lcd.c
+
+OBJS=$(SRCS:.c=.o)
+
+all: $(ELF)
+
+$(ELF): $(OBJS)
+ $(CC) $(CFLAGS) -o $@ $(OBJS) -L../libstm32l_discovery/build -lstm32l_discovery
+
+%.o: %.c
+ $(CC) $(CFLAGS) -c -o $@ $^
+
+clean:
+ -rm -f $(OBJS)
+ -rm -f $(ELF)
+
+.PHONY: all clean
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file discover_board.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.2\r
+ * @date September-2011\r
+ * @brief Input/Output defines\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+\r
+#ifndef __DISCOVER_BOARD_H\r
+#define __DISCOVER_BOARD_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h" \r
+\r
+#define bool _Bool\r
+#define FALSE 0\r
+#define TRUE !FALSE\r
+\r
+/* MACROs for SET, RESET or TOGGLE Output port */\r
+\r
+#define GPIO_HIGH(a,b) a->BSRRL = b\r
+#define GPIO_LOW(a,b) a->BSRRH = b\r
+#define GPIO_TOGGLE(a,b) a->ODR ^= b \r
+\r
+#define USERBUTTON_GPIO_PORT GPIOA\r
+#define USERBUTTON_GPIO_PIN GPIO_Pin_0\r
+#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+\r
+#define LD_GPIO_PORT GPIOB\r
+#define LD_GREEN_GPIO_PIN GPIO_Pin_7\r
+#define LD_BLUE_GPIO_PIN GPIO_Pin_6\r
+#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB\r
+\r
+#define CTN_GPIO_PORT GPIOC\r
+#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13\r
+#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+\r
+#define WAKEUP_GPIO_PORT GPIOA\r
+\r
+#define IDD_MEASURE_PORT GPIOA\r
+#define IDD_MEASURE GPIO_Pin_4\r
+\r
+\r
+#endif\r
+\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+OUTPUT_FORMAT("elf32-littlearm")
+ENTRY(_main)
+
+MEMORY
+{
+ sram : ORIGIN = 0x20000000, LENGTH = 0x4000
+}
+
+SECTIONS
+{
+ .text(ORIGIN(sram)):
+ {
+ _main = .;
+ _ftext = .;
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ _etext = .;
+ } > sram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ _frodata = .;
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.rodata1)
+ _erodata = .;
+ } > sram
+
+ .data :
+ {
+ . = ALIGN(4);
+ _fdata = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.data1)
+ _gp = ALIGN(16);
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ _edata = .;
+ } > sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _fbss = .;
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ _ebss = .;
+ _end = .;
+ } > sram
+}
+
+PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);
--- /dev/null
+/* this example is only for stm32l discover.
+ adapted from ST firmwares projects.
+ */
+
+/* base headers */
+#include "stdint.h"
+
+/* libstm32l_discovery headers */
+#include "stm32l1xx_gpio.h"
+#include "stm32l1xx_adc.h"
+#include "stm32l1xx_lcd.h"
+#include "stm32l1xx_rcc.h"
+#include "stm32l1xx_rtc.h"
+#include "stm32l1xx_exti.h"
+#include "stm32l1xx_pwr.h"
+#include "stm32l1xx_syscfg.h"
+#include "stm32l1xx_dbgmcu.h"
+
+/* lcd wrapper routines header */
+#include "stm32l_discovery_lcd.h"
+
+/* boot mode */
+
+#define CONFIG_BOOT_SRAM 1
+#define CONFIG_BOOT_FLASH 0
+
+
+/* gpios
+ refer to CD00277537.pdf, APB memory space.
+ refer to CD00240193.pdf, GPIO.
+*/
+
+#define GPIOA_MODER (GPIOA_BASE + 0x00)
+#define GPIOA_ODR (GPIOA_BASE + 0x14)
+
+#define GPIOB_MODER (GPIOB_BASE + 0x00)
+#define GPIOB_ODR (GPIOB_BASE + 0x14)
+
+#define GPIOC_MODER (GPIOC_BASE + 0x00)
+#define GPIOC_ODR (GPIOC_BASE + 0x14)
+
+
+/* leds */
+
+#define LED_BLUE (1 << 6) /* port B, pin 6 */
+#define LED_GREEN (1 << 7) /* port B, pin 7 */
+
+static inline void setup_leds(void)
+{
+ /* configure port 6 and 7 as output */
+ *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2));
+}
+
+static inline void switch_leds_on(void)
+{
+ *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN;
+}
+
+static inline void switch_leds_off(void)
+{
+ *(volatile uint32_t*)GPIOB_ODR = 0;
+}
+
+
+#define delay() \
+do { \
+ register unsigned int i; \
+ for (i = 0; i < 1000000; ++i) \
+ __asm__ __volatile__ ("nop\n\t":::"memory"); \
+} while (0)
+
+
+#if CONFIG_BOOT_SRAM
+
+extern uint32_t _fstack;
+
+static inline void setup_stack(void)
+{
+ /* setup the stack to point to _fstack (refer to ld script) */
+
+ static const uint32_t fstack = (uint32_t)&_fstack;
+
+ __asm__ __volatile__
+ (
+ "ldr sp, %0\n\t"
+ :
+ : "m"(fstack)
+ : "sp"
+ );
+}
+
+#endif /* CONFIG_BOOT_SRAM */
+
+
+/* application related setup */
+
+static void RCC_Configuration(void)
+{
+ /* Enable HSI Clock */
+ RCC_HSICmd(ENABLE);
+
+ /*!< Wait till HSI is ready */
+ while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);
+
+ /* Set HSI as sys clock*/
+ RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
+
+ /* Set MSI clock range to ~4.194MHz*/
+ RCC_MSIRangeConfig(RCC_MSIRange_6);
+
+ /* Enable the GPIOs clocks */
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC| RCC_AHBPeriph_GPIOD| RCC_AHBPeriph_GPIOE| RCC_AHBPeriph_GPIOH, ENABLE);
+
+ /* Enable comparator, LCD and PWR mngt clocks */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP | RCC_APB1Periph_LCD | RCC_APB1Periph_PWR,ENABLE);
+
+ /* Enable ADC & SYSCFG clocks */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_SYSCFG , ENABLE);
+
+ /* Allow access to the RTC */
+ PWR_RTCAccessCmd(ENABLE);
+
+ /* Reset RTC Backup Domain */
+ RCC_RTCResetCmd(ENABLE);
+ RCC_RTCResetCmd(DISABLE);
+
+ /* LSE Enable */
+ RCC_LSEConfig(RCC_LSE_ON);
+
+ /* Wait until LSE is ready */
+ while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET);
+
+ /* RTC Clock Source Selection */
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+
+ /* Enable the RTC */
+ RCC_RTCCLKCmd(ENABLE);
+
+ /*Disable HSE*/
+ RCC_HSEConfig(RCC_HSE_OFF);
+ if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET )
+ {
+ /* Stay in infinite loop if HSE is not disabled*/
+ while(1);
+ }
+}
+
+static void Init_GPIOs(void)
+{
+#if 0 /* fixme: GPIO_Init raises a bug in some gcc toolchains */
+
+ /* GPIO, EXTI and NVIC Init structure declaration */
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+#if 0
+ EXTI_InitTypeDef EXTI_InitStructure;
+ NVIC_InitTypeDef NVIC_InitStructure;
+#endif
+
+#if 0
+ /* Configure User Button pin as input */
+ GPIO_InitStructure.GPIO_Pin = USERBUTTON_GPIO_PIN;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+ GPIO_Init(USERBUTTON_GPIO_PORT, &GPIO_InitStructure);
+#endif
+
+#if 0
+ /* Select User Button pin as input source for EXTI Line */
+ SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA,EXTI_PinSource0);
+
+ /* Configure EXT1 Line 0 in interrupt mode trigged on Rising edge */
+ EXTI_InitStructure.EXTI_Line = EXTI_Line0 ; // PA0 for User button AND IDD_WakeUP
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+ EXTI_Init(&EXTI_InitStructure);
+
+ /* Enable and set EXTI0 Interrupt to the lowest priority */
+ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn ;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+#endif
+
+#if 0
+ /* Configure the LED_pin as output push-pull for LD3 & LD4 usage*/
+ GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure);
+
+ /* Force a low level on LEDs*/
+ GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN);
+ GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);
+
+ /* Counter enable: GPIO set in output for enable the counter */
+ GPIO_InitStructure.GPIO_Pin = CTN_CNTEN_GPIO_PIN;
+ GPIO_Init( CTN_GPIO_PORT, &GPIO_InitStructure);
+
+ /* To prepare to start counter */
+ GPIO_HIGH(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN);
+
+ /* Configure Port A LCD Output pins as alternate function */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+ GPIO_Init( GPIOA, &GPIO_InitStructure);
+
+ /* Select LCD alternate function for Port A LCD Output pins */
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ;
+
+ /* Configure Port B LCD Output pins as alternate function */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \
+ | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+ GPIO_Init( GPIOB, &GPIO_InitStructure);
+
+ /* Select LCD alternate function for Port B LCD Output pins */
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ;
+#endif
+
+#if 0
+ /* Configure Port C LCD Output pins as alternate function */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \
+ | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+ GPIO_Init( GPIOC, &GPIO_InitStructure);
+
+ /* Select LCD alternate function for Port B LCD Output pins */
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ;
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ;
+#endif
+
+#if 0
+ /* Configure ADC (IDD_MEASURE) pin as Analogue */
+ GPIO_InitStructure.GPIO_Pin = IDD_MEASURE ;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
+ GPIO_Init( IDD_MEASURE_PORT, &GPIO_InitStructure);
+#endif
+
+#else /* fixme */
+
+ /* set every port in digital output mode */
+
+ /* PA[1:3,8:10,15] */
+ *(volatile uint32_t*)GPIOA_MODER |=
+ (GPIO_Mode_AF << (1 * 2)) |
+ (GPIO_Mode_AF << (2 * 2)) |
+ (GPIO_Mode_AF << (3 * 2)) |
+ (GPIO_Mode_AF << (8 * 2)) |
+ (GPIO_Mode_AF << (9 * 2)) |
+ (GPIO_Mode_AF << (10 * 2)) |
+ (GPIO_Mode_AF << (15 * 2));
+
+ /* PB[3:5,8:15] */
+ *(volatile uint32_t*)GPIOB_MODER |=
+ (GPIO_Mode_AF << (3 * 2)) |
+ (GPIO_Mode_AF << (4 * 2)) |
+ (GPIO_Mode_AF << (5 * 2)) |
+ (GPIO_Mode_AF << (8 * 2)) |
+ (GPIO_Mode_AF << (9 * 2)) |
+ (GPIO_Mode_AF << (10 * 2)) |
+ (GPIO_Mode_AF << (11 * 2)) |
+ (GPIO_Mode_AF << (12 * 2)) |
+ (GPIO_Mode_AF << (13 * 2)) |
+ (GPIO_Mode_AF << (14 * 2)) |
+ (GPIO_Mode_AF << (15 * 2));
+
+ /* PC[0:3,6:11] */
+ *(volatile uint32_t*)GPIOC_MODER |=
+ (GPIO_Mode_AF << (0 * 2)) |
+ (GPIO_Mode_AF << (1 * 2)) |
+ (GPIO_Mode_AF << (2 * 2)) |
+ (GPIO_Mode_AF << (3 * 2)) |
+ (GPIO_Mode_AF << (6 * 2)) |
+ (GPIO_Mode_AF << (7 * 2)) |
+ (GPIO_Mode_AF << (8 * 2)) |
+ (GPIO_Mode_AF << (9 * 2)) |
+ (GPIO_Mode_AF << (10 * 2)) |
+ (GPIO_Mode_AF << (11 * 2));
+
+#endif /* fixme */
+}
+
+
+/* main */
+
+static void __attribute__((naked)) __attribute__((used)) main(void)
+{
+#if CONFIG_BOOT_SRAM
+ /* do not use previsouly setup stack, if any */
+ setup_stack();
+#endif /* CONFIG_BOOT_SRAM */
+
+ RCC_Configuration();
+
+ Init_GPIOs();
+
+ LCD_GLASS_Init();
+
+ setup_leds();
+
+ while (1)
+ {
+ /* switch_leds_on(); */
+ GPIO_HIGH(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
+ GPIO_HIGH(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
+
+ LCD_GLASS_Clear();
+ LCD_GLASS_DisplayString("ON ");
+
+ delay();
+
+ /* switch_leds_off(); */
+ GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN);
+ GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN);
+
+ LCD_GLASS_Clear();
+ LCD_GLASS_DisplayString(" OFF");
+
+ delay();
+ }
+}
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l_discovery_lcd.c\r
+ * @author Microcontroller Division\r
+ * @version V1.0.0\r
+ * @date Apri-2011\r
+ * @brief This file includes driver for the glass LCD Module mounted on \r
+ * STM32l discovery board MB963\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l_discovery_lcd.h"\r
+#include "discover_board.h"\r
+#include "stm32l1xx_lcd.h"\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_rcc.h"\r
+/* #include "main.h" */\r
+\r
+/* this variable can be used for accelerate the scrolling exit when push user button */\r
+volatile bool KeyPressed = FALSE; \r
+ \r
+/* LCD BAR status: We don't write directly in LCD RAM for save the bar setting */\r
+uint8_t t_bar[2]={0x0,0X0};\r
+ \r
+/* =========================================================================\r
+ LCD MAPPING\r
+ =========================================================================\r
+ A\r
+ _ ----------\r
+COL |_| |\ |J /|\r
+ F| H | K |B\r
+ _ | \ | / |\r
+COL |_| --G-- --M--\r
+ | /| \ |\r
+ E| Q | N |C\r
+ _ | / |P \| \r
+DP |_| ----------- \r
+ D \r
+\r
+ An LCD character coding is based on the following matrix:\r
+ { E , D , P , N }\r
+ { M , C , COL , DP}\r
+ { B , A , K , J }\r
+ { G , F , Q , H }\r
+\r
+ The character 'A' for example is:\r
+ -------------------------------\r
+LSB { 1 , 0 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+MSB { 1 , 1 , 0 , 0 }\r
+ -------------------\r
+ 'A' = F E 0 0 hexa\r
+\r
+*/\r
+\r
+/* Constant table for cap characters 'A' --> 'Z' */\r
+const uint16_t CapLetterMap[26]=\r
+ {\r
+ /* A B C D E F G H I */\r
+ 0xFE00,0x6714,0x1d00,0x4714,0x9d00,0x9c00,0x3f00,0xfa00,0x0014,\r
+ /* J K L M N O P Q R */\r
+ 0x5300,0x9841,0x1900,0x5a48,0x5a09,0x5f00,0xFC00,0x5F01,0xFC01,\r
+ /* S T U V W X Y Z */\r
+ 0xAF00,0x0414,0x5b00,0x18c0,0x5a81,0x00c9,0x0058,0x05c0\r
+ };\r
+\r
+/* Constant table for number '0' --> '9' */\r
+const uint16_t NumberMap[10]=\r
+ {\r
+ /* 0 1 2 3 4 5 6 7 8 9 */\r
+ 0x5F00,0x4200,0xF500,0x6700,0xEa00,0xAF00,0xBF00,0x04600,0xFF00,0xEF00\r
+ };\r
+\r
+static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column,uint8_t* digit);\r
+\r
+/**\r
+ * @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_Init(void)\r
+{\r
+ LCD_InitTypeDef LCD_InitStruct;\r
+\r
+ \r
+ LCD_InitStruct.LCD_Prescaler = LCD_Prescaler_1;\r
+ LCD_InitStruct.LCD_Divider = LCD_Divider_31;\r
+ LCD_InitStruct.LCD_Duty = LCD_Duty_1_4;\r
+ LCD_InitStruct.LCD_Bias = LCD_Bias_1_3;\r
+ LCD_InitStruct.LCD_VoltageSource = LCD_VoltageSource_Internal;\r
+\r
+ \r
+ /* Initialize the LCD */\r
+ LCD_Init(&LCD_InitStruct);\r
+ \r
+ LCD_MuxSegmentCmd(ENABLE);\r
+ \r
+ /* To set contrast to mean value */\r
+ LCD_ContrastConfig(LCD_Contrast_Level_4);\r
+ \r
+ LCD_DeadTimeConfig(LCD_DeadTime_0);\r
+ LCD_PulseOnDurationConfig(LCD_PulseOnDuration_4);\r
+\r
+ /* Wait Until the LCD FCR register is synchronized */\r
+ LCD_WaitForSynchro();\r
+ \r
+ /* Enable LCD peripheral */\r
+ LCD_Cmd(ENABLE);\r
+ \r
+ /* Wait Until the LCD is enabled */\r
+ while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)\r
+ {\r
+ }\r
+ /*!< Wait Until the LCD Booster is ready */ \r
+ while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)\r
+ {\r
+ } \r
+\r
+ LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32); \r
+ LCD_GLASS_Clear();\r
+}\r
+\r
+/**\r
+ * @brief To initialize the LCD pins\r
+ * @caller main\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+void LCD_GLASS_Configure_GPIO(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ \r
+/* Enable GPIOs clock */ \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
+ RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, ENABLE);\r
+\r
+ \r
+/* Configure Output for LCD */\r
+/* Port A */\r
+ GPIO_StructInit(&GPIO_InitStructure);\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOA, &GPIO_InitStructure);\r
+\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+/* Configure Output for LCD */\r
+/* Port B */ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \\r
+ | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOB, &GPIO_InitStructure);\r
+ \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; \r
+ \r
+/* Configure Output for LCD */\r
+/* Port C*/ \r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \\r
+ | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; \r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_Init( GPIOC, &GPIO_InitStructure); \r
+ \r
+\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;\r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; \r
+ GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; \r
+\r
+/* Disable GPIOs clock */ \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |\r
+ RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, DISABLE);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief LCD contrast setting min-->max-->min by pressing user button\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+static void Delay(uint32_t nTime)\r
+{\r
+ while((nTime--) != 0); \r
+}\r
+\r
+void LCD_contrast()\r
+{\r
+ uint32_t contrast ;\r
+ \r
+ /* To get the actual contrast value in register */\r
+ contrast = LCD->FCR & LCD_Contrast_Level_7;\r
+ \r
+ while ((GPIOC->IDR & USERBUTTON_GPIO_PIN) == 0x0)\r
+ {\r
+ contrast += LCD_Contrast_Level_1; \r
+ \r
+ if (contrast > LCD_Contrast_Level_7)\r
+ contrast=LCD_Contrast_Level_0;\r
+ \r
+ LCD_ContrastConfig(contrast);\r
+ Delay(100);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Setting bar on LCD, writes bar value in LCD frame buffer \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_bar()\r
+{\r
+ \r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xffff5fff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xffff5fff;\r
+/* bar1 bar3 */\r
+ LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(t_bar[0]<<12);\r
+ \r
+/*bar0 bar2 */\r
+ LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(t_bar[1]<<12);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Converts an ascii char to the a LCD digit.\r
+ * @param c: a char to display.\r
+ * @param point: a point to add in front of char\r
+ * This parameter can be: POINT_OFF or POINT_ON\r
+ * @param column : flag indicating if a column has to be add in front\r
+ * of displayed character.\r
+ * This parameter can be: COLUMN_OFF or COLUMN_ON.\r
+ * @param digit array with segment \r
+ * @retval None\r
+ */\r
+static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit)\r
+{\r
+ uint16_t ch = 0 ;\r
+ uint8_t i,j;\r
+ \r
+ switch (*c)\r
+ {\r
+ case ' ' : \r
+ ch = 0x00;\r
+ break;\r
+ \r
+ case '*':\r
+ ch = star;\r
+ break;\r
+ \r
+ case 'µ' :\r
+ ch = C_UMAP;\r
+ break;\r
+ \r
+ case 'm' :\r
+ ch = C_mMap;\r
+ break;\r
+ \r
+ case 'n' :\r
+ ch = C_nMap;\r
+ break; \r
+ \r
+ case '-' :\r
+ ch = C_minus;\r
+ break;\r
+ \r
+ case '/' :\r
+ ch = C_slatch;\r
+ break; \r
+ \r
+ case '°' :\r
+ ch = C_percent_1;\r
+ break; \r
+ case '%' :\r
+ ch = C_percent_2; \r
+ break;\r
+ case 255 :\r
+ ch = C_full;\r
+ break ;\r
+ \r
+ case '0':\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9': \r
+ ch = NumberMap[*c-0x30]; \r
+ break;\r
+ \r
+ default:\r
+ /* The character c is one letter in upper case*/\r
+ if ( (*c < 0x5b) && (*c > 0x40) )\r
+ {\r
+ ch = CapLetterMap[*c-'A'];\r
+ }\r
+ /* The character c is one letter in lower case*/\r
+ if ( (*c <0x7b) && ( *c> 0x60) )\r
+ {\r
+ ch = CapLetterMap[*c-'a'];\r
+ }\r
+ break;\r
+ }\r
+ \r
+ /* Set the digital point can be displayed if the point is on */\r
+ if (point)\r
+ {\r
+ ch |= 0x0002;\r
+ }\r
+\r
+ /* Set the "COL" segment in the character that can be displayed if the column is on */\r
+ if (column)\r
+ {\r
+ ch |= 0x0020;\r
+ } \r
+\r
+ for (i = 12,j=0 ;j<4; i-=4,j++)\r
+ {\r
+ digit[j] = (ch >> i) & 0x0f; //To isolate the less signifiant dibit\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD frame buffer.\r
+ * @param ch: the character to display.\r
+ * @param point: a point to add in front of char\r
+ * This parameter can be: POINT_OFF or POINT_ON\r
+ * @param column: flag indicating if a column has to be add in front\r
+ * of displayed character.\r
+ * This parameter can be: COLUMN_OFF or COLUMN_ON. \r
+ * @param position: position in the LCD of the caracter to write [0:7]\r
+ * @retval None\r
+ * @par Required preconditions: The LCD should be cleared before to start the\r
+ * write operation. \r
+ */\r
+void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column, uint8_t position)\r
+{\r
+ uint8_t digit[4]; /* Digit frame buffer */\r
+ \r
+/* To convert displayed character in segment in array digit */\r
+ LCD_Conv_Char_Seg(ch,point,column,digit);\r
+\r
+/* TO wait LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ switch (position)\r
+ {\r
+ /* Position 1 on LCD (Digit1)*/\r
+ case 1:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xcffffffc;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xcffffffc;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 26 ) | (digit[0]& 0x03) ; // 1G 1B 1M 1E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 26 ) | (digit[1]& 0x03) ; // 1F 1A 1C 1D \r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 26 ) | (digit[2]& 0x03) ; // 1Q 1K 1Col 1P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 26 ) | (digit[3]& 0x03) ; // 1H 1J 1DP 1N\r
+\r
+ break;\r
+ \r
+ /* Position 2 on LCD (Digit2)*/\r
+ case 2:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xf3ffff03;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xf3ffff03; \r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xf3ffff03;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xf3ffff03;\r
+ \r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 24 )|((digit[0]& 0x02) << 6 )|((digit[0]& 0x01) << 2 ) ; // 2G 2B 2M 2E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 24 )|((digit[1]& 0x02) << 6 )|((digit[1]& 0x01) << 2 ) ; // 2F 2A 2C 2D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 24 )|((digit[2]& 0x02) << 6 )|((digit[2]& 0x01) << 2 ) ; // 2Q 2K 2Col 2P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 24 )|((digit[3]& 0x02) << 6 )|((digit[3]& 0x01) << 2 ) ; // 2H 2J 2DP 2N\r
+ \r
+ break;\r
+ \r
+ /* Position 3 on LCD (Digit3)*/\r
+ case 3:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfcfffcff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfcfffcff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 22 ) | ((digit[0]& 0x03) << 8 ) ; // 3G 3B 3M 3E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 22 ) | ((digit[1]& 0x03) << 8 ) ; // 3F 3A 3C 3D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 22 ) | ((digit[2]& 0x03) << 8 ) ; // 3Q 3K 3Col 3P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 22 ) | ((digit[3]& 0x03) << 8 ) ; // 3H 3J 3DP 3N\r
+ \r
+ break;\r
+ \r
+ /* Position 4 on LCD (Digit4)*/\r
+ case 4:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xffcff3ff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xffcff3ff;\r
+ \r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 18 ) | ((digit[0]& 0x03) << 10 ) ; // 4G 4B 4M 4E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 18 ) | ((digit[1]& 0x03) << 10 ) ; // 4F 4A 4C 4D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 18 ) | ((digit[2]& 0x03) << 10 ) ; // 4Q 4K 4Col 4P\r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 18 ) | ((digit[3]& 0x03) << 10 ) ; // 4H 4J 4DP 4N\r
+ \r
+ break;\r
+ \r
+ /* Position 5 on LCD (Digit5)*/\r
+ case 5:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfff3cfff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfff3cfff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfff3efff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfff3efff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 16 ) | ((digit[0]& 0x03) << 12 ) ; // 5G 5B 5M 5E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 16 ) | ((digit[1]& 0x03) << 12 ) ; // 5F 5A 5C 5D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 16 ) | ((digit[2]& 0x01) << 12 ) ; // 5Q 5K 5P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 16 ) | ((digit[3]& 0x01) << 12 ) ; // 5H 5J 5N\r
+ \r
+ break;\r
+ \r
+ /* Position 6 on LCD (Digit6)*/\r
+ case 6:\r
+ LCD->RAM[LCD_RAMRegister_0] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_2] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_4] &= 0xfffc3fff;\r
+ LCD->RAM[LCD_RAMRegister_6] &= 0xfffc3fff;\r
+\r
+ LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x04) << 15 ) | ((digit[0]& 0x08) << 13 ) | ((digit[0]& 0x03) << 14 ) ; // 6B 6G 6M 6E \r
+ LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x04) << 15 ) | ((digit[1]& 0x08) << 13 ) | ((digit[1]& 0x03) << 14 ) ; // 6A 6F 6C 6D\r
+ LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x04) << 15 ) | ((digit[2]& 0x08) << 13 ) | ((digit[2]& 0x01) << 14 ) ; // 6K 6Q 6P \r
+ LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x04) << 15 ) | ((digit[3]& 0x08) << 13 ) | ((digit[3]& 0x01) << 14 ) ; // 6J 6H 6N\r
+ \r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+/* Refresh LCD bar */\r
+ LCD_bar();\r
+\r
+/* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+ \r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD RAM.\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_DisplayString(uint8_t* ptr)\r
+{\r
+ uint8_t i = 0x01;\r
+\r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 8))\r
+ {\r
+ /* Display one character on LCD */\r
+ LCD_GLASS_WriteChar(ptr, FALSE, FALSE, i);\r
+\r
+ /* Point on the next character */\r
+ ptr++;\r
+\r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function writes a char in the LCD RAM.\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @retval None\r
+ * @par Required preconditions: Char is ASCCI value "Ored" with decimal point or Column flag\r
+ */\r
+void LCD_GLASS_DisplayStrDeci(uint16_t* ptr)\r
+{\r
+ uint8_t i = 0x01;\r
+ uint8_t char_tmp;\r
+ \r
+// LCD_GLASS_Clear();\r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 8))\r
+ { \r
+ char_tmp = (*ptr) & 0x00ff;\r
+ \r
+ switch ((*ptr) & 0xf000)\r
+ {\r
+ case DOT:\r
+ /* Display one character on LCD with decimal point */\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_ON, COLUMN_OFF, i);\r
+ break;\r
+ case DOUBLE_DOT:\r
+ /* Display one character on LCD with decimal point */\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_ON, i);\r
+ break;\r
+ default:\r
+ LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_OFF, i); \r
+ break;\r
+ }/* Point on the next character */\r
+ ptr++;\r
+ \r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function Clear the whole LCD RAM.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_GLASS_Clear(void)\r
+{\r
+ uint8_t counter = 0;\r
+\r
+ /* TO wait LCD Ready */ \r
+ while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;\r
+ \r
+ for (counter = LCD_RAMRegister_0; counter <= LCD_RAMRegister_15; counter++)\r
+ {\r
+ LCD->RAM[counter] = 0;\r
+ }\r
+\r
+ /* Update the LCD display */\r
+ LCD_UpdateDisplayRequest();\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Display a string in scrolling mode\r
+ * @param ptr: Pointer to string to display on the LCD Glass.\r
+ * @param nScroll: Specifies how many time the message will be scrolled\r
+ * @param ScrollSpeed : Speciifes the speed of the scroll, low value gives\r
+ * higher speed \r
+ * @retval None\r
+ * @par Required preconditions: The LCD should be cleared before to start the\r
+ * write operation.\r
+ */\r
+void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)\r
+{\r
+ uint8_t Repetition;\r
+ uint8_t Char_Nb;\r
+ uint8_t* ptr1;\r
+ uint8_t str[7]="";\r
+ uint8_t Str_size;\r
+ \r
+ if (ptr == 0) return;\r
+\r
+/* To calculate end of string */\r
+ for (ptr1=ptr,Str_size = 0 ; *ptr1 != 0; Str_size++,ptr1++) ;\r
+ \r
+ ptr1 = ptr;\r
+ \r
+ LCD_GLASS_DisplayString(ptr);\r
+ Delay(ScrollSpeed);\r
+ \r
+/* To shift the string for scrolling display*/\r
+ for (Repetition=0; Repetition<nScroll; Repetition++)\r
+ {\r
+ for (Char_Nb=0; Char_Nb<Str_size; Char_Nb++)\r
+ {\r
+ *(str) =* (ptr1+((Char_Nb+1)%Str_size));\r
+ *(str+1) =* (ptr1+((Char_Nb+2)%Str_size));\r
+ *(str+2) =* (ptr1+((Char_Nb+3)%Str_size));\r
+ *(str+3) =* (ptr1+((Char_Nb+4)%Str_size));\r
+ *(str+4) =* (ptr1+((Char_Nb+5)%Str_size));\r
+ *(str+5) =* (ptr1+((Char_Nb+6)%Str_size));\r
+ LCD_GLASS_Clear();\r
+ LCD_GLASS_DisplayString(str);\r
+ \r
+ /* user button pressed stop the scrolling sentence */\r
+ if (KeyPressed)\r
+ return; \r
+ Delay(ScrollSpeed);\r
+ } \r
+ }\r
+\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file stm32l_discovery_lcd.h\r
+ * @author Microcontroller Division\r
+ * @version V1.0.0\r
+ * @date Apri-2011\r
+ * @brief This file contains all the functions prototypes for the glass LCD\r
+ * firmware driver.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __stm32l_discovery_lcd\r
+#define __stm32l_discovery_lcd\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h" \r
+#include "discover_board.h"\r
+\r
+/* Define for scrolling sentences*/\r
+#define SCROLL_SPEED 300\r
+#define SCROLL_SPEED_L 600\r
+#define SCROLL_NUM 1\r
+\r
+/* Define for character '.' */\r
+#define POINT_OFF FALSE\r
+#define POINT_ON TRUE\r
+\r
+/* Define for caracter ":" */\r
+#define COLUMN_OFF FALSE\r
+#define COLUMN_ON TRUE\r
+\r
+#define DOT 0x8000 /* for add decimal point in string */\r
+#define DOUBLE_DOT 0x4000 /* for add decimal point in string */\r
+\r
+\r
+/* =========================================================================\r
+ LCD MAPPING\r
+ =========================================================================\r
+ A\r
+ _ ----------\r
+COL |_| |\ |J /|\r
+ F| H | K |B\r
+ _ | \ | / |\r
+COL |_| --G-- --M--\r
+ | /| \ |\r
+ E| Q | N |C\r
+ _ | / |P \| \r
+DP |_| ----------- \r
+ D \r
+\r
+ An LCD character coding is based on the following matrix:\r
+ { E , D , P , N }\r
+ { M , C , COL , DP}\r
+ { B , A , K , J }\r
+ { G , F , Q , H }\r
+\r
+ The character 'A' for example is:\r
+ -------------------------------\r
+LSB { 1 , 0 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+ { 1 , 1 , 0 , 0 }\r
+MSB { 1 , 1 , 0 , 0 }\r
+ -------------------\r
+ 'A' = F E 0 0 hexa\r
+\r
+*/\r
+/* Macros used for set/reset bar LCD bar */\r
+#define BAR0_ON t_bar[1] |= 8\r
+#define BAR0_OFF t_bar[1] &= ~8\r
+#define BAR1_ON t_bar[0] |= 8\r
+#define BAR1_OFF t_bar[0] &= ~8\r
+#define BAR2_ON t_bar[1] |= 2\r
+#define BAR2_OFF t_bar[1] &= ~2\r
+#define BAR3_ON t_bar[0] |= 2 \r
+#define BAR3_OFF t_bar[0] &= ~2 \r
+\r
+/* code for 'µ' character */\r
+#define C_UMAP 0x6084\r
+\r
+/* code for 'm' character */\r
+#define C_mMap 0xb210\r
+\r
+/* code for 'n' character */\r
+#define C_nMap 0x2210\r
+\r
+/* constant code for '*' character */\r
+#define star 0xA0DD\r
+\r
+/* constant code for '-' character */\r
+#define C_minus 0xA000\r
+\r
+/* constant code for '/' */\r
+#define C_slatch 0x00c0\r
+\r
+/* constant code for ° */\r
+#define C_percent_1 0xec00\r
+\r
+/* constant code for small o */\r
+#define C_percent_2 0xb300\r
+\r
+#define C_full 0xffdd\r
+\r
+void LCD_bar(void);\r
+void LCD_GLASS_Init(void);\r
+void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column,uint8_t position);\r
+void LCD_GLASS_DisplayString(uint8_t* ptr);\r
+void LCD_GLASS_DisplayStrDeci(uint16_t* ptr);\r
+void LCD_GLASS_ClearChar(uint8_t position);\r
+void LCD_GLASS_Clear(void);\r
+void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);\r
+void LCD_GLASS_WriteTime(char a, uint8_t posi, bool column);\r
+void LCD_GLASS_Configure_GPIO(void);\r
+\r
+#endif /* stm32l_discovery_lcd*/\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+LIB = libstm32l_discovery.a
+
+CC = arm-none-eabi-gcc
+AR = arm-none-eabi-ar
+RANLIB = arm-none-eabi-ranlib
+
+CFLAGS = -Wall -O2 -mlittle-endian -mthumb
+CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
+CFLAGS += -I../inc -I../inc/device_support -I../inc/core_support -I../inc/base
+
+SRCS = \
+../src/misc.c \
+../src/stm32l1xx_adc.c \
+../src/stm32l1xx_comp.c \
+../src/stm32l1xx_crc.c \
+../src/stm32l1xx_dac.c \
+../src/stm32l1xx_dbgmcu.c \
+../src/stm32l1xx_dma.c \
+../src/stm32l1xx_exti.c \
+../src/stm32l1xx_flash.c \
+../src/stm32l1xx_flash_ramfunc.c \
+../src/stm32l1xx_gpio.c \
+../src/stm32l1xx_i2c.c \
+../src/stm32l1xx_iwdg.c \
+../src/stm32l1xx_lcd.c \
+../src/stm32l1xx_pwr.c \
+../src/stm32l1xx_rcc.c \
+../src/stm32l1xx_rtc.c \
+../src/stm32l1xx_spi.c \
+../src/stm32l1xx_syscfg.c \
+../src/stm32l1xx_tim.c \
+../src/stm32l1xx_usart.c \
+../src/stm32l1xx_wwdg.c \
+../inc/core_support/core_cm3.c
+
+OBJS = $(SRCS:.c=.o)
+
+all: $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) -r $(LIB) $(OBJS)
+ $(RANLIB) $(LIB)
+
+%.o : %.c
+ $(CC) $(CFLAGS) -c -o $@ $^
+
+clean:
+ -rm -f $(OBJS)
+ -rm -f $(LIB)
+
+.PHONY: all clean
--- /dev/null
+#ifndef STDINT_H_INCLUDED
+# define STDINT_H_INCLUDED
+
+
+typedef char int8_t;
+typedef short int16_t;
+typedef int int32_t;
+typedef long long int64_t;
+
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+
+
+#endif /* ! STDINT_H_INCLUDED */
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.c\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+ mrs r0, psp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ msr psp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+ mrs r0, msp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+ msr msp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+ clrex\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t __get_BASEPRI(void)\r
+{\r
+ mrs r0, basepri\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ msr basepri, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+ mrs r0, primask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ msr primask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t __get_FAULTMASK(void)\r
+{\r
+ mrs r0, faultmask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ msr faultmask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+ mrs r0, control\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+ msr control, r0\r
+ bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+ __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, psp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, msp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ uint8_t result=0;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ uint16_t result=0;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ * - Error 10: \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';'\r
+ * .\r
+ * - Error 530: \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ * - Error 550: \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ * - Error 754: \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 750: \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 528: \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 751: \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note: To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core registers and bitfields\r
+ - Cortex-M core peripheral base address\r
+ @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+ memory mapped structure for System Control Block (SCB)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
+} SCB_Type; \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+ memory mapped structure for SysTick\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+ memory mapped structure for Interrupt Type\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+ memory mapped structure for Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+ memory mapped structure for Core Debug Register\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+ Core Function Interface containing:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn The positive number of the external interrupt to disable\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn The number of the device specifc interrupt\r
+ * @return 1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for read active bit\r
+ * @return 1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for set priority\r
+ * @param priority The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for get priority\r
+ * @return The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param PriorityGroup The used priority group\r
+ * @param PreemptPriority The preemptive priority value (starting from 0)\r
+ * @param SubPriority The sub priority value (starting from 0)\r
+ * @return The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param Priority The priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param pPreemptPriority The preemptive priority value (starting from 0)\r
+ * @param pSubPriority The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param ticks number of ticks between two interrupts\r
+ * @return 1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+ Core Debug Interface containing:\r
+ - Core Debug Receive / Transmit Functions\r
+ - Core Debug Defines\r
+ - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param ch character to output\r
+ * @return character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32L1xx devices. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32L1XX_H\r
+#define __STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define assert_param(__p)\r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM32L device used in your \r
+ application \r
+ */\r
+\r
+#if !defined (STM32L1XX_MD)\r
+ #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */\r
+#endif\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+\r
+ - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx \r
+ microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\r
+\r
+ */\r
+\r
+#if !defined (STM32L1XX_MD)\r
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"\r
+#endif\r
+\r
+#if !defined USE_STDPERIPH_DRIVER\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_STDPERIPH_DRIVER*/\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application \r
+ \r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */ \r
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+ Timeout value \r
+ */\r
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+\r
+/**\r
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup \r
+ Timeout value \r
+ */\r
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */\r
+\r
+#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */\r
+\r
+/**\r
+ * @brief STM32L1xx Standard Peripheral Library version number\r
+ */\r
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ \r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM32L1XX_STDPERIPH_VERSION_RC))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+#define __MPU_PRESENT 1 /*!< STM32L provides MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/*!< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** STM32L specific Interrupt Numbers ***********************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */\r
+ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */\r
+ DAC_IRQn = 21, /*!< DAC Interrupt */\r
+ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ LCD_IRQn = 24, /*!< LCD Interrupt */\r
+ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */\r
+ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */\r
+ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 44 /*!< TIM7 global Interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm3.h"\r
+#include "system_stm32l1xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/** \r
+ * @brief __RAM_FUNC definition \r
+ */ \r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options. \r
+ Functions that are executed in RAM should reside in a separate source \r
+ module. Using the 'Options for File' dialog you can simply change the \r
+ 'Code / Const' area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the \r
+ 'Options for Target' dialog. \r
+*/\r
+ #define __RAM_FUNC FLASH_Status \r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+*/\r
+ #define __RAM_FUNC __ramfunc FLASH_Status\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute \r
+ "__attribute__((section(".data")))". \r
+*/\r
+ #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))\r
+\r
+#elif defined ( __TASKING__ )\r
+/* TASKING Compiler\r
+ ----------------\r
+ RAM functions are defined using a specific toolchain pragma. This pragma is \r
+ defined in the stm32l1xx_flash_ramfunc.c \r
+*/\r
+ #define __RAM_FUNC FLASH_Status\r
+\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR;\r
+ __IO uint32_t CR1;\r
+ __IO uint32_t CR2;\r
+ __IO uint32_t SMPR1;\r
+ __IO uint32_t SMPR2;\r
+ __IO uint32_t SMPR3;\r
+ __IO uint32_t JOFR1;\r
+ __IO uint32_t JOFR2;\r
+ __IO uint32_t JOFR3;\r
+ __IO uint32_t JOFR4;\r
+ __IO uint32_t HTR;\r
+ __IO uint32_t LTR;\r
+ __IO uint32_t SQR1;\r
+ __IO uint32_t SQR2;\r
+ __IO uint32_t SQR3;\r
+ __IO uint32_t SQR4;\r
+ __IO uint32_t SQR5;\r
+ __IO uint32_t JSQR;\r
+ __IO uint32_t JDR1;\r
+ __IO uint32_t JDR2;\r
+ __IO uint32_t JDR3;\r
+ __IO uint32_t JDR4;\r
+ __IO uint32_t DR;\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR;\r
+ __IO uint32_t CCR;\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Comparator \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR;\r
+} COMP_TypeDef;\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR;\r
+ __IO uint8_t IDR;\r
+ uint8_t RESERVED0;\r
+ uint16_t RESERVED1;\r
+ __IO uint32_t CR;\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t SWTRIGR;\r
+ __IO uint32_t DHR12R1;\r
+ __IO uint32_t DHR12L1;\r
+ __IO uint32_t DHR8R1;\r
+ __IO uint32_t DHR12R2;\r
+ __IO uint32_t DHR12L2;\r
+ __IO uint32_t DHR8R2;\r
+ __IO uint32_t DHR12RD;\r
+ __IO uint32_t DHR12LD;\r
+ __IO uint32_t DHR8RD;\r
+ __IO uint32_t DOR1;\r
+ __IO uint32_t DOR2;\r
+ __IO uint32_t SR; \r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE;\r
+ __IO uint32_t CR;\r
+ __IO uint32_t APB1FZ;\r
+ __IO uint32_t APB2FZ; \r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR;\r
+ __IO uint32_t CNDTR;\r
+ __IO uint32_t CPAR;\r
+ __IO uint32_t CMAR;\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR;\r
+ __IO uint32_t IFCR;\r
+} DMA_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR;\r
+ __IO uint32_t EMR;\r
+ __IO uint32_t RTSR;\r
+ __IO uint32_t FTSR;\r
+ __IO uint32_t SWIER;\r
+ __IO uint32_t PR;\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR;\r
+ __IO uint32_t PECR;\r
+ __IO uint32_t PDKEYR;\r
+ __IO uint32_t PEKEYR;\r
+ __IO uint32_t PRGKEYR;\r
+ __IO uint32_t OPTKEYR;\r
+ __IO uint32_t SR;\r
+ __IO uint32_t OBR;\r
+ __IO uint32_t WRPR; \r
+} FLASH_TypeDef;\r
+\r
+/** \r
+ * @brief Option Bytes Registers\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RDP;\r
+ __IO uint32_t USER;\r
+ __IO uint32_t WRP01;\r
+ __IO uint32_t WRP23;\r
+} OB_TypeDef;\r
+\r
+/** \r
+ * @brief General Purpose IO\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER;\r
+ __IO uint16_t OTYPER;\r
+ uint16_t RESERVED0;\r
+ __IO uint32_t OSPEEDR;\r
+ __IO uint32_t PUPDR;\r
+ __IO uint16_t IDR;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t ODR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */\r
+ __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */\r
+ __IO uint32_t LCKR;\r
+ __IO uint32_t AFR[2];\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief SysTem Configuration\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP;\r
+ __IO uint32_t PMC;\r
+ __IO uint32_t EXTICR[4];\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t OAR1;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t OAR2;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t SR1;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t SR2;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t CCR;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t TRISE;\r
+ uint16_t RESERVED8;\r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR;\r
+ __IO uint32_t PR;\r
+ __IO uint32_t RLR;\r
+ __IO uint32_t SR;\r
+} IWDG_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief LCD\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t FCR;\r
+ __IO uint32_t SR;\r
+ __IO uint32_t CLR;\r
+ uint32_t RESERVED;\r
+ __IO uint32_t RAM[16];\r
+} LCD_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t CSR;\r
+} PWR_TypeDef;\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t ICSCR;\r
+ __IO uint32_t CFGR;\r
+ __IO uint32_t CIR;\r
+ __IO uint32_t AHBRSTR;\r
+ __IO uint32_t APB2RSTR;\r
+ __IO uint32_t APB1RSTR;\r
+ __IO uint32_t AHBENR;\r
+ __IO uint32_t APB2ENR;\r
+ __IO uint32_t APB1ENR;\r
+ __IO uint32_t AHBLPENR;\r
+ __IO uint32_t APB2LPENR;\r
+ __IO uint32_t APB1LPENR; \r
+ __IO uint32_t CSR; \r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Routing Interface \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ICR;\r
+ __IO uint32_t ASCR1;\r
+ __IO uint32_t ASCR2;\r
+ __IO uint32_t HYSCR1;\r
+ __IO uint32_t HYSCR2;\r
+ __IO uint32_t HYSCR3;\r
+} RI_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR;\r
+ __IO uint32_t DR;\r
+ __IO uint32_t CR;\r
+ __IO uint32_t ISR;\r
+ __IO uint32_t PRER;\r
+ __IO uint32_t WUTR;\r
+ __IO uint32_t CALIBR;\r
+ __IO uint32_t ALRMAR;\r
+ __IO uint32_t ALRMBR;\r
+ __IO uint32_t WPR;\r
+ uint32_t RESERVED1;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t TSTR;\r
+ __IO uint32_t TSDR;\r
+ uint32_t RESERVED3;\r
+ uint32_t RESERVED4;\r
+ __IO uint32_t TAFCR;\r
+ uint32_t RESERVED5;\r
+ uint32_t RESERVED6;\r
+ uint32_t RESERVED7;\r
+ __IO uint32_t BKP0R;\r
+ __IO uint32_t BKP1R;\r
+ __IO uint32_t BKP2R;\r
+ __IO uint32_t BKP3R;\r
+ __IO uint32_t BKP4R;\r
+ __IO uint32_t BKP5R;\r
+ __IO uint32_t BKP6R;\r
+ __IO uint32_t BKP7R;\r
+ __IO uint32_t BKP8R;\r
+ __IO uint32_t BKP9R;\r
+ __IO uint32_t BKP10R;\r
+ __IO uint32_t BKP11R;\r
+ __IO uint32_t BKP12R;\r
+ __IO uint32_t BKP13R;\r
+ __IO uint32_t BKP14R;\r
+ __IO uint32_t BKP15R;\r
+ __IO uint32_t BKP16R;\r
+ __IO uint32_t BKP17R;\r
+ __IO uint32_t BKP18R;\r
+ __IO uint32_t BKP19R;\r
+} RTC_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t CRCPR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t RXCRCR;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t TXCRCR;\r
+ uint16_t RESERVED6; \r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t SMCR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DIER;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t EGR;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t CCMR1;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t CCMR2;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t CCER;\r
+ uint16_t RESERVED8;\r
+ __IO uint16_t CNT;\r
+ uint16_t RESERVED9;\r
+ __IO uint16_t PSC;\r
+ uint16_t RESERVED10;\r
+ __IO uint16_t ARR;\r
+ uint16_t RESERVED11;\r
+ uint32_t RESERVED12;\r
+ __IO uint16_t CCR1;\r
+ uint16_t RESERVED13;\r
+ __IO uint16_t CCR2;\r
+ uint16_t RESERVED14;\r
+ __IO uint16_t CCR3;\r
+ uint16_t RESERVED15;\r
+ __IO uint16_t CCR4;\r
+ uint16_t RESERVED16;\r
+ uint32_t RESERVED17;\r
+ __IO uint16_t DCR;\r
+ uint16_t RESERVED18;\r
+ __IO uint16_t DMAR;\r
+ uint16_t RESERVED19;\r
+ __IO uint16_t OR;\r
+ uint16_t RESERVED20;\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t BRR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t CR3;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t GTPR;\r
+ uint16_t RESERVED6;\r
+} USART_TypeDef;\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t CFR;\r
+ __IO uint32_t SR;\r
+} WWDG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\r
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+\r
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
+\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define LCD_BASE (APB1PERIPH_BASE + 0x2400)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)\r
+#define RI_BASE (APB1PERIPH_BASE + 0x7C04)\r
+\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2700)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
+\r
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)\r
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x3800)\r
+\r
+\r
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */\r
+#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */\r
+\r
+#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)\r
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)\r
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)\r
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)\r
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)\r
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)\r
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)\r
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)\r
+\r
+\r
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define LCD ((LCD_TypeDef *) LCD_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define COMP ((COMP_TypeDef *) COMP_BASE)\r
+#define RI ((RI_TypeDef *) RI_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define OB ((OB_TypeDef *) OB_BASE) \r
+\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers Bits Definition */\r
+/******************************************************************************/\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter (ADC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */\r
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */\r
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */\r
+#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */\r
+#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */\r
+#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */\r
+\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */\r
+#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */\r
+\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */\r
+\r
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+\r
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */\r
+\r
+#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */\r
+#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */\r
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */\r
+\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+\r
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */\r
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */\r
+\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */\r
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */\r
+#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */\r
+#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */\r
+#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */\r
+#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */\r
+#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */\r
+#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */\r
+#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
+#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
+#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR3 register *******************/\r
+#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+ \r
+#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */\r
+#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */\r
+#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */\r
+\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR4 register *******************/\r
+#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR5 register *******************/\r
+#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */\r
+\r
+#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */\r
+#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */\r
+#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */\r
+#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */\r
+\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */\r
+\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */\r
+\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */\r
+#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */\r
+#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/\r
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ \r
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog Comparators (COMP) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for COMP_CSR register ********************/\r
+#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */\r
+#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */\r
+#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */\r
+#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */\r
+\r
+#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */\r
+#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */\r
+\r
+#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */\r
+#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */\r
+\r
+#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */\r
+#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */\r
+\r
+#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */\r
+#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+\r
+#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */\r
+#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit (CRC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter (DAC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU (DBGMCU) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */\r
+\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */\r
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/****************** Bit definition for DBGMCU_CR register *******************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/\r
+\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */\r
+\r
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/\r
+\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller (DMA) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for DMA_ISR register ********************/\r
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */\r
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */\r
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */\r
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */\r
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */\r
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */\r
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */\r
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */\r
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */\r
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */\r
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */\r
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */\r
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */\r
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */\r
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */\r
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */\r
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */\r
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */\r
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */\r
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */\r
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */\r
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */\r
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */\r
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */\r
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */\r
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */\r
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */\r
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */\r
+\r
+/******************* Bit definition for DMA_IFCR register *******************/\r
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */\r
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */\r
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */\r
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */\r
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */\r
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */\r
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */\r
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */\r
+\r
+/******************* Bit definition for DMA_CCR1 register *******************/\r
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/\r
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */\r
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR2 register *******************/\r
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */\r
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR3 register *******************/\r
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/*!<****************** Bit definition for DMA_CCR4 register *******************/\r
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/****************** Bit definition for DMA_CCR5 register *******************/\r
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
+\r
+/******************* Bit definition for DMA_CCR6 register *******************/\r
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR7 register *******************/\r
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */\r
+\r
+/****************** Bit definition for DMA_CNDTR1 register ******************/\r
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR2 register ******************/\r
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR3 register ******************/\r
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR4 register ******************/\r
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR5 register ******************/\r
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR6 register ******************/\r
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR7 register ******************/\r
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CPAR1 register *******************/\r
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR2 register *******************/\r
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR3 register *******************/\r
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR4 register *******************/\r
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR5 register *******************/\r
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR6 register *******************/\r
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR7 register *******************/\r
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CMAR1 register *******************/\r
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR2 register *******************/\r
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR3 register *******************/\r
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CMAR4 register *******************/\r
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR5 register *******************/\r
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR6 register *******************/\r
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR7 register *******************/\r
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller (EXTI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */\r
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */\r
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */\r
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH, DATA EEPROM and Option Bytes Registers */\r
+/* (FLASH, DATA_EEPROM, OB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for FLASH_ACR register ******************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */\r
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */\r
+#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */\r
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */\r
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */\r
+\r
+/******************* Bit definition for FLASH_PECR register ******************/\r
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */\r
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */\r
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */\r
+#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */\r
+#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */\r
+#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */\r
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */\r
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */\r
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */ \r
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */ \r
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */ \r
+\r
+/****************** Bit definition for FLASH_PDKEYR register ******************/\r
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PEKEYR register ******************/\r
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */\r
+\r
+/****************** Bit definition for FLASH_PRGKEYR register ******************/\r
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */\r
+\r
+/****************** Bit definition for FLASH_OPTKEYR register ******************/\r
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */\r
+\r
+/****************** Bit definition for FLASH_SR register *******************/\r
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */\r
+#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/\r
+#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */\r
+#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */\r
+\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */\r
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */\r
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */\r
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */\r
+\r
+/****************** Bit definition for FLASH_OBR register *******************/\r
+#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) /*!< Read Protection */\r
+#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/\r
+#define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */\r
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */\r
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */\r
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */\r
+\r
+/****************** Bit definition for FLASH_WRPR register ******************/\r
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose IOs (GPIO) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for GPIO_MODER register *****************/ \r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_OTYPER register ****************/ \r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/******************* Bit definition for GPIO_OSPEEDR register ***************/ \r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_PUPDR register *****************/ \r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_IDR register *******************/ \r
+#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)\r
+\r
+/******************* Bit definition for GPIO_ODR register *******************/ \r
+#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)\r
+\r
+/******************* Bit definition for GPIO_BSRR register ******************/ \r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_LCKR register ******************/\r
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)\r
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)\r
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)\r
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)\r
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)\r
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)\r
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)\r
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)\r
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)\r
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)\r
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)\r
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)\r
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)\r
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)\r
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)\r
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)\r
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)\r
+\r
+/******************* Bit definition for GPIO_AFRL register ******************/\r
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)\r
+\r
+/******************* Bit definition for GPIO_AFRH register ******************/\r
+#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for I2C_CR1 register ********************/\r
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */\r
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */\r
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */\r
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */\r
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */\r
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */\r
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */\r
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */\r
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */\r
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */\r
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */\r
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */\r
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */\r
+\r
+/******************* Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+\r
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */\r
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */\r
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */\r
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */\r
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */\r
+\r
+/******************* Bit definition for I2C_OAR1 register *******************/\r
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */\r
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */\r
+\r
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */\r
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */\r
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */\r
+\r
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */\r
+\r
+/******************* Bit definition for I2C_OAR2 register *******************/\r
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */\r
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */\r
+\r
+/******************** Bit definition for I2C_DR register ********************/\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */\r
+\r
+/******************* Bit definition for I2C_SR1 register ********************/\r
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */\r
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */\r
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */\r
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */\r
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */\r
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */\r
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */\r
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */\r
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */\r
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */\r
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */\r
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */\r
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */\r
+\r
+/******************* Bit definition for I2C_SR2 register ********************/\r
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */\r
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */\r
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */\r
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */\r
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */\r
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */\r
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */\r
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */\r
+\r
+/******************* Bit definition for I2C_CCR register ********************/\r
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */\r
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */\r
+\r
+/****************** Bit definition for I2C_TRISE register *******************/\r
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG (IWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD Controller (LCD) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for LCD_CR register *********************/\r
+#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */\r
+#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */\r
+\r
+#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */\r
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */\r
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */\r
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */\r
+\r
+#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */\r
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */\r
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */\r
+\r
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */\r
+\r
+/******************* Bit definition for LCD_FCR register ********************/\r
+#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */\r
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */\r
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */\r
+\r
+#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */\r
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */\r
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */\r
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */\r
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */\r
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */\r
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */\r
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */\r
+#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */\r
+\r
+/******************* Bit definition for LCD_SR register *********************/\r
+#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */\r
+#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */\r
+#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */\r
+#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */\r
+#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */\r
+#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */\r
+\r
+/******************* Bit definition for LCD_CLR register ********************/\r
+#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */\r
+#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */\r
+\r
+/******************* Bit definition for LCD_RAM register ********************/\r
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control (PWR) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */\r
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */\r
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */\r
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */\r
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */\r
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */\r
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */\r
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */\r
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
+#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */\r
+#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */\r
+\r
+#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */\r
+#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */\r
+#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */\r
+#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
+#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */\r
+#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */\r
+#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */\r
+\r
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */\r
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */\r
+#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control (RCC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */\r
+\r
+#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */\r
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */\r
+\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */\r
+\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */\r
+#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */\r
+\r
+#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */\r
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */\r
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */\r
+\r
+/******************** Bit definition for RCC_ICSCR register *****************/\r
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */\r
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */\r
+\r
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */\r
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */\r
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */\r
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */\r
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */\r
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */\r
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */\r
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */\r
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */\r
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */\r
+\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */\r
+\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */\r
+\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */\r
+\r
+/*!< PLL entry clock source*/\r
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */\r
+\r
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */\r
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */\r
+\r
+\r
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
+\r
+/*!< PLLMUL configuration */\r
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */\r
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */\r
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */\r
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */\r
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */\r
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */\r
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */\r
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */\r
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */\r
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */\r
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */\r
+\r
+\r
+/*!< PLLDIV configuration */\r
+#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */\r
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */\r
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */\r
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */\r
+\r
+\r
+#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+/*!< MCO configuration */\r
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */\r
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */\r
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */\r
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */\r
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */\r
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */\r
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */\r
+\r
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */\r
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */\r
+\r
+/*!< MCO Prescaler configuration */\r
+#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */\r
+#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */\r
+#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */\r
+#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */\r
+#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */\r
+\r
+/*!<****************** Bit definition for RCC_CIR register ********************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */\r
+#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */\r
+\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */\r
+#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */\r
+\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */\r
+#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */\r
+\r
+\r
+/***************** Bit definition for RCC_AHBRSTR register ******************/\r
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */\r
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */\r
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */\r
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */\r
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */\r
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */\r
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */\r
+#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */\r
+#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */\r
+ \r
+/***************** Bit definition for RCC_APB2RSTR register *****************/\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */\r
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */\r
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */\r
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */\r
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */\r
+\r
+/***************** Bit definition for RCC_APB1RSTR register *****************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */\r
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
+#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */\r
+\r
+/****************** Bit definition for RCC_AHBENR register ******************/\r
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */\r
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */\r
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */\r
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */\r
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */\r
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */\r
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */\r
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when\r
+ the Flash memory is in power down mode) */\r
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */\r
+\r
+\r
+/****************** Bit definition for RCC_APB2ENR register *****************/\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */\r
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */\r
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */\r
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
+\r
+\r
+/***************** Bit definition for RCC_APB1ENR register ******************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */\r
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
+#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */\r
+\r
+/****************** Bit definition for RCC_AHBLPENR register ****************/\r
+#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode\r
+ (has effect only when the Flash memory is\r
+ in power down mode) */\r
+#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */\r
+#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */\r
+\r
+/****************** Bit definition for RCC_APB2LPENR register ***************/\r
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */\r
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */\r
+\r
+/***************** Bit definition for RCC_APB1LPENR register ****************/\r
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */\r
+#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/\r
+\r
+/******************* Bit definition for RCC_CSR register ********************/\r
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */\r
+\r
+#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */\r
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */\r
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */\r
+\r
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+/*!< RTC congiguration */\r
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */\r
+\r
+#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */\r
+#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */\r
+ \r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */\r
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */\r
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */\r
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000)\r
+#define RTC_TR_HT ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TR_ST ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
+#define RTC_DR_YU ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_DR_MT ((uint32_t)0x00001000)\r
+#define RTC_DR_MU ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_DR_DT ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_DR_DU ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_COE ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
+#define RTC_CR_POL ((uint32_t)0x00100000)\r
+#define RTC_CR_BCK ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
+#define RTC_CR_DCE ((uint32_t)0x00000080)\r
+#define RTC_CR_FMT ((uint32_t)0x00000040)\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CALIBR register ***************/\r
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)\r
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TAFCR register ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)\r
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)\r
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)\r
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */\r
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */\r
+\r
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */\r
+\r
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */\r
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */\r
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */\r
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */\r
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */\r
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */\r
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* System Configuration (SYSCFG) */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for SYSCFG_MEMRMP register ****************/\r
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+/***************** Bit definition for SYSCFG_PMC register *******************/\r
+#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
+\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
+\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
+ \r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
+\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */\r
+ \r
+/******************************************************************************/\r
+/* */\r
+/* Routing Interface (RI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for RI_ICR register ********************/\r
+#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */\r
+#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */\r
+#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */\r
+#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */\r
+#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */\r
+\r
+#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */\r
+#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */\r
+#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */\r
+#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */\r
+#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */\r
+\r
+/******************** Bit definition for RI_ASCR1 register ********************/\r
+#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */\r
+#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */\r
+#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */\r
+#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */\r
+#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */\r
+#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */\r
+#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */\r
+#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */\r
+#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */\r
+\r
+#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */\r
+#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */\r
+\r
+/******************** Bit definition for RI_ASCR2 register ********************/\r
+#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */\r
+#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */\r
+#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */\r
+#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */\r
+#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */\r
+#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */\r
+#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */\r
+#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */\r
+#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */\r
+#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */\r
+#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */\r
+#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */\r
+\r
+\r
+/******************** Bit definition for RI_HYSCR1 register ********************/\r
+#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */\r
+#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */\r
+#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/******************** Bit definition for RI_HYSCR2 register ********************/\r
+#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */\r
+#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */\r
+#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/******************** Bit definition for RI_HYSCR3 register ********************/\r
+#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */\r
+#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Timers (TIM) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */\r
+\r
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */\r
+#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for USART_SR register *******************/\r
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */\r
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */\r
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */\r
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */\r
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */\r
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */\r
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */\r
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */\r
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */\r
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */\r
+\r
+/******************* Bit definition for USART_DR register *******************/\r
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */\r
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */\r
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */\r
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */\r
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */\r
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */\r
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */\r
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling by 8-bit mode */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */\r
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */\r
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */\r
+\r
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */\r
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */\r
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */\r
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */\r
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */\r
+\r
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Serial Bus (USB) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/*!<Endpoint-specific registers */\r
+/******************* Bit definition for USB_EP0R register *******************/\r
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP1R register *******************/\r
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP2R register *******************/\r
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP3R register *******************/\r
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP4R register *******************/\r
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP5R register *******************/\r
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP6R register *******************/\r
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP7R register *******************/\r
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/*!<Common registers */\r
+/******************* Bit definition for USB_CNTR register *******************/\r
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */\r
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */\r
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */\r
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */\r
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */\r
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */\r
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */\r
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */\r
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */\r
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */\r
+\r
+/******************* Bit definition for USB_ISTR register *******************/\r
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */\r
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */\r
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */\r
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */\r
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */\r
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */\r
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */\r
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */\r
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */\r
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */\r
+\r
+/******************* Bit definition for USB_FNR register ********************/\r
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */\r
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */\r
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */\r
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */\r
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */\r
+\r
+/****************** Bit definition for USB_DADDR register *******************/\r
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */\r
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */\r
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */\r
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */\r
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */\r
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */\r
+\r
+#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */\r
+\r
+/****************** Bit definition for USB_BTABLE register ******************/ \r
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */\r
+\r
+/*!< Buffer descriptor table */\r
+/***************** Bit definition for USB_ADDR0_TX register *****************/\r
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_TX register *****************/\r
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_TX register *****************/\r
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_TX register *****************/\r
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_TX register *****************/\r
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_TX register *****************/\r
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_TX register *****************/\r
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_TX register *****************/\r
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_TX register ****************/\r
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */\r
+\r
+/***************** Bit definition for USB_COUNT1_TX register ****************/\r
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */\r
+\r
+/***************** Bit definition for USB_COUNT2_TX register ****************/\r
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */\r
+\r
+/***************** Bit definition for USB_COUNT3_TX register ****************/\r
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */\r
+\r
+/***************** Bit definition for USB_COUNT4_TX register ****************/\r
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */\r
+\r
+/***************** Bit definition for USB_COUNT5_TX register ****************/\r
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */\r
+\r
+/***************** Bit definition for USB_COUNT6_TX register ****************/\r
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */\r
+\r
+/***************** Bit definition for USB_COUNT7_TX register ****************/\r
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_ADDR0_RX register *****************/\r
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_RX register *****************/\r
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_RX register *****************/\r
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_RX register *****************/\r
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_RX register *****************/\r
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_RX register *****************/\r
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_RX register *****************/\r
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_RX register *****************/\r
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_RX register ****************/\r
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT1_RX register ****************/\r
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT2_RX register ****************/\r
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT3_RX register ****************/\r
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT4_RX register ****************/\r
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT5_RX register ****************/\r
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT6_RX register ****************/\r
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT7_RX register ****************/\r
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */\r
+\r
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */\r
+\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */\r
+\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+\r
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG (WWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */\r
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */\r
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */\r
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SystemTick (SysTick) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/***************** Bit definition for SysTick_CTRL register *****************/\r
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */\r
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */\r
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */\r
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */\r
+\r
+/***************** Bit definition for SysTick_LOAD register *****************/\r
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
+\r
+/***************** Bit definition for SysTick_VAL register ******************/\r
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */\r
+\r
+/***************** Bit definition for SysTick_CALIB register ****************/\r
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */\r
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */\r
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Nested Vectored Interrupt Controller (NVIC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for NVIC_ISER register *******************/\r
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */\r
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICER register *******************/\r
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */\r
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ISPR register *******************/\r
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */\r
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICPR register *******************/\r
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */\r
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_IABR register *******************/\r
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */\r
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_PRI0 register *******************/\r
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */\r
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */\r
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */\r
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */\r
+\r
+/****************** Bit definition for NVIC_PRI1 register *******************/\r
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */\r
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */\r
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */\r
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */\r
+\r
+/****************** Bit definition for NVIC_PRI2 register *******************/\r
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */\r
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */\r
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */\r
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */\r
+\r
+/****************** Bit definition for NVIC_PRI3 register *******************/\r
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */\r
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */\r
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */\r
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */\r
+\r
+/****************** Bit definition for NVIC_PRI4 register *******************/\r
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */\r
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */\r
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */\r
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */\r
+\r
+/****************** Bit definition for NVIC_PRI5 register *******************/\r
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */\r
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */\r
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */\r
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */\r
+\r
+/****************** Bit definition for NVIC_PRI6 register *******************/\r
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */\r
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */\r
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */\r
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */\r
+\r
+/****************** Bit definition for NVIC_PRI7 register *******************/\r
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */\r
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */\r
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */\r
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */\r
+\r
+/****************** Bit definition for SCB_CPUID register *******************/\r
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */\r
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */\r
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */\r
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */\r
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */\r
+\r
+/******************* Bit definition for SCB_ICSR register *******************/\r
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */\r
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */\r
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */\r
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */\r
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */\r
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */\r
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */\r
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */\r
+\r
+/******************* Bit definition for SCB_VTOR register *******************/\r
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */\r
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */\r
+\r
+/*!<***************** Bit definition for SCB_AIRCR register *******************/\r
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */\r
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */\r
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */\r
+\r
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */\r
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+/* prority group configuration */\r
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
+\r
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */\r
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
+\r
+/******************* Bit definition for SCB_SCR register ********************/\r
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */\r
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */\r
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */\r
+\r
+/******************** Bit definition for SCB_CCR register *******************/\r
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */\r
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */\r
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */\r
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
+\r
+/******************* Bit definition for SCB_SHPR register ********************/\r
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
+\r
+/****************** Bit definition for SCB_SHCSR register *******************/\r
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */\r
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */\r
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */\r
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */\r
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */\r
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */\r
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */\r
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */\r
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */\r
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */\r
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */\r
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */\r
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */\r
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */\r
+\r
+/******************* Bit definition for SCB_CFSR register *******************/\r
+/*!< MFSR */\r
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */\r
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */\r
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */\r
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */\r
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */\r
+/*!< BFSR */\r
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */\r
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */\r
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */\r
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */\r
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */\r
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */\r
+/*!< UFSR */\r
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */\r
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */\r
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */\r
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */\r
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
+\r
+/******************* Bit definition for SCB_HFSR register *******************/\r
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */\r
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */\r
+\r
+/******************* Bit definition for SCB_DFSR register *******************/\r
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */\r
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */\r
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */\r
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */\r
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */\r
+\r
+/******************* Bit definition for SCB_MMFAR register ******************/\r
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */\r
+\r
+/******************* Bit definition for SCB_BFAR register *******************/\r
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */\r
+\r
+/******************* Bit definition for SCB_afsr register *******************/\r
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm32l1xx_conf.h"\r
+#endif\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l1xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32L1XX_H\r
+#define __SYSTEM_STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32L1xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_types\r
+ * @{\r
+ */\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32L1XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the miscellaneous\r
+ * firmware library functions (add-on to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
+ This parameter can be a value of @ref IRQn_Type \r
+ (For the complete STM32 Devices IRQ Channels list, please\r
+ refer to stm32l1xx.h file) */\r
+\r
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
+ specified in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
+ in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+ will be enabled or disabled. \r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+} NVIC_InitTypeDef;\r
+\r
+/** \r
+ *\r
+@verbatim \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ============================================================================================================================\r
+@endverbatim\r
+*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Vector_Table_Base \r
+ * @{\r
+ */\r
+\r
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0001FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_ADC_H\r
+#define __STM32L1xx_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.\r
+ This parameter can be a value of @ref ADC_Resolution */\r
+ \r
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
+ Scan (multichannel) or Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+ \r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
+ Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ \r
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the\r
+ trigger of a regular group. This parameter can be a value\r
+ of @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
+ to digital conversion of regular channels. This parameter\r
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
+ This parameter can be a value of @ref ADC_data_align */\r
+ \r
+ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done\r
+ using the sequencer for regular channel group.\r
+ This parameter must range from 1 to 27. */\r
+}ADC_InitTypeDef;\r
+\r
+typedef struct \r
+{ \r
+ uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.\r
+ This parameter can be a value \r
+ of @ref ADC_Prescaler */\r
+}ADC_CommonInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */ \r
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+\r
+/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase \r
+ * @{\r
+ */ \r
+#define ADC_PowerDown_Delay ((uint32_t)0x00010000)\r
+#define ADC_PowerDown_Idle ((uint32_t)0x00020000)\r
+#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)\r
+\r
+#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \\r
+ ((DWON) == ADC_PowerDown_Idle) || \\r
+ ((DWON) == ADC_PowerDown_Idle_Delay))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_Prescaler \r
+ * @{\r
+ */ \r
+#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)\r
+#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)\r
+#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)\r
+\r
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div2) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+\r
+/** @defgroup ADC_resolution \r
+ * @{\r
+ */ \r
+#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
+#define ADC_Resolution_10b ((uint32_t)0x01000000)\r
+#define ADC_Resolution_8b ((uint32_t)0x02000000)\r
+#define ADC_Resolution_6b ((uint32_t)0x03000000)\r
+\r
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
+ ((RESOLUTION) == ADC_Resolution_10b) || \\r
+ ((RESOLUTION) == ADC_Resolution_8b) || \\r
+ ((RESOLUTION) == ADC_Resolution_6b))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r
+#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r
+\r
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion\r
+ * @{\r
+ */ \r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)\r
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r
+#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)\r
+#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)\r
+\r
+/* TIM6 */\r
+#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r
+\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
+\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_Channel_0 ((uint8_t)0x00)\r
+#define ADC_Channel_1 ((uint8_t)0x01)\r
+#define ADC_Channel_2 ((uint8_t)0x02)\r
+#define ADC_Channel_3 ((uint8_t)0x03)\r
+#define ADC_Channel_4 ((uint8_t)0x04)\r
+#define ADC_Channel_5 ((uint8_t)0x05)\r
+#define ADC_Channel_6 ((uint8_t)0x06)\r
+#define ADC_Channel_7 ((uint8_t)0x07)\r
+#define ADC_Channel_8 ((uint8_t)0x08)\r
+#define ADC_Channel_9 ((uint8_t)0x09)\r
+#define ADC_Channel_10 ((uint8_t)0x0A)\r
+#define ADC_Channel_11 ((uint8_t)0x0B)\r
+#define ADC_Channel_12 ((uint8_t)0x0C)\r
+#define ADC_Channel_13 ((uint8_t)0x0D)\r
+#define ADC_Channel_14 ((uint8_t)0x0E)\r
+#define ADC_Channel_15 ((uint8_t)0x0F)\r
+#define ADC_Channel_16 ((uint8_t)0x10)\r
+#define ADC_Channel_17 ((uint8_t)0x11)\r
+#define ADC_Channel_18 ((uint8_t)0x12)\r
+#define ADC_Channel_19 ((uint8_t)0x13)\r
+#define ADC_Channel_20 ((uint8_t)0x14)\r
+#define ADC_Channel_21 ((uint8_t)0x15)\r
+#define ADC_Channel_22 ((uint8_t)0x16)\r
+#define ADC_Channel_23 ((uint8_t)0x17)\r
+#define ADC_Channel_24 ((uint8_t)0x18)\r
+#define ADC_Channel_25 ((uint8_t)0x19)\r
+\r
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
+\r
+\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \\r
+ ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \\r
+ ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \\r
+ ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \\r
+ ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) )\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_sampling_times \r
+ * @{\r
+ */ \r
+\r
+#define ADC_SampleTime_4Cycles ((uint8_t)0x00)\r
+#define ADC_SampleTime_9Cycles ((uint8_t)0x01)\r
+#define ADC_SampleTime_16Cycles ((uint8_t)0x02)\r
+#define ADC_SampleTime_24Cycles ((uint8_t)0x03)\r
+#define ADC_SampleTime_48Cycles ((uint8_t)0x04)\r
+#define ADC_SampleTime_96Cycles ((uint8_t)0x05)\r
+#define ADC_SampleTime_192Cycles ((uint8_t)0x06)\r
+#define ADC_SampleTime_384Cycles ((uint8_t)0x07)\r
+\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \\r
+ ((TIME) == ADC_SampleTime_9Cycles) || \\r
+ ((TIME) == ADC_SampleTime_16Cycles) || \\r
+ ((TIME) == ADC_SampleTime_24Cycles) || \\r
+ ((TIME) == ADC_SampleTime_48Cycles) || \\r
+ ((TIME) == ADC_SampleTime_96Cycles) || \\r
+ ((TIME) == ADC_SampleTime_192Cycles) || \\r
+ ((TIME) == ADC_SampleTime_384Cycles))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Delay_length \r
+ * @{\r
+ */ \r
+\r
+#define ADC_DelayLength_None ((uint8_t)0x00)\r
+#define ADC_DelayLength_Freeze ((uint8_t)0x10)\r
+#define ADC_DelayLength_7Cycles ((uint8_t)0x20)\r
+#define ADC_DelayLength_15Cycles ((uint8_t)0x30)\r
+#define ADC_DelayLength_31Cycles ((uint8_t)0x40)\r
+#define ADC_DelayLength_63Cycles ((uint8_t)0x50)\r
+#define ADC_DelayLength_127Cycles ((uint8_t)0x60)\r
+#define ADC_DelayLength_255Cycles ((uint8_t)0x70)\r
+\r
+#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \\r
+ ((LENGTH) == ADC_DelayLength_Freeze) || \\r
+ ((LENGTH) == ADC_DelayLength_7Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_15Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_31Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_63Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_127Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_255Cycles))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r
+#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+\r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r
+\r
+/* TIM7 */\r
+#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)\r
+\r
+/* TIM10 */\r
+#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_channel_selection \r
+ * @{\r
+ */ \r
+#define ADC_InjectedChannel_1 ((uint8_t)0x18)\r
+#define ADC_InjectedChannel_2 ((uint8_t)0x1C)\r
+#define ADC_InjectedChannel_3 ((uint8_t)0x20)\r
+#define ADC_InjectedChannel_4 ((uint8_t)0x24)\r
+\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) \r
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_IT_AWD ((uint16_t)0x0106) \r
+#define ADC_IT_EOC ((uint16_t)0x0205) \r
+#define ADC_IT_JEOC ((uint16_t)0x0407) \r
+#define ADC_IT_OVR ((uint16_t)0x201A) \r
+ \r
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \\r
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_FLAG_AWD ((uint16_t)0x0001)\r
+#define ADC_FLAG_EOC ((uint16_t)0x0002)\r
+#define ADC_FLAG_JEOC ((uint16_t)0x0004)\r
+#define ADC_FLAG_JSTRT ((uint16_t)0x0008)\r
+#define ADC_FLAG_STRT ((uint16_t)0x0010)\r
+#define ADC_FLAG_OVR ((uint16_t)0x0020)\r
+#define ADC_FLAG_ADONS ((uint16_t)0x0040)\r
+#define ADC_FLAG_RCNR ((uint16_t)0x0100)\r
+#define ADC_FLAG_JCNR ((uint16_t)0x0200) \r
+ \r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))\r
+ \r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \\r
+ ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \\r
+ ((FLAG) == ADC_FLAG_JCNR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_offset \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 27))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x1B))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_discontinuous_mode_number \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the ADC configuration to the default reset state *****/ \r
+void ADC_DeInit(ADC_TypeDef* ADCx); \r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Power saving functions *****************************************************/\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);\r
+\r
+/* Analog Watchdog configuration functions ************************************/\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
+\r
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+\r
+/* Regular Channels Configuration functions ***********************************/\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+\r
+/* Regular Channels DMA Configuration functions *******************************/\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Injected channels Configuration functions **********************************/\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_comp.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the COMP firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_COMP_H\r
+#define __STM32L1xx_COMP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup COMP\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief COMP Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.\r
+ This parameter can be a value of @ref COMP_Speed */\r
+ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.\r
+ This parameter can be a value of @ref COMP_InvertingInput */\r
+ uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.\r
+ This parameter can be a value of @ref COMP_OutputSelect */\r
+ \r
+}COMP_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup COMP_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+#define COMP_OutputLevel_High ((uint32_t)0x00000001)\r
+#define COMP_OutputLevel_Low ((uint32_t)0x00000000)\r
+\r
+/** @defgroup COMP_Selection\r
+ * @{\r
+ */\r
+\r
+#define COMP_Selection_COMP1 ((uint32_t)0x00000001)\r
+#define COMP_Selection_COMP2 ((uint32_t)0x00000002)\r
+\r
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \\r
+ ((PERIPH) == COMP_Selection_COMP2))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_InvertingInput\r
+ * @{\r
+ */\r
+\r
+#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */\r
+#define COMP_InvertingInput_IO ((uint32_t)0x00040000)\r
+#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)\r
+#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)\r
+#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)\r
+#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)\r
+#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)\r
+#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)\r
+\r
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \\r
+ ((INPUT) == COMP_InvertingInput_IO) || \\r
+ ((INPUT) == COMP_InvertingInput_VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_DAC1) || \\r
+ ((INPUT) == COMP_InvertingInput_DAC2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_OutputSelect\r
+ * @{\r
+ */\r
+\r
+#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)\r
+#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)\r
+#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)\r
+#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)\r
+#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)\r
+#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)\r
+#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)\r
+#define COMP_OutputSelect_None ((uint32_t)0x00E00000)\r
+\r
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \\r
+ ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \\r
+ ((OUTPUT) == COMP_OutputSelect_None))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup COMP_Speed\r
+ * @{\r
+ */\r
+\r
+#define COMP_Speed_Slow ((uint32_t)0x00000000)\r
+#define COMP_Speed_Fast ((uint32_t)0x00001000)\r
+\r
+#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \\r
+ ((SPEED) == COMP_Speed_Fast))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the COMP configuration to the default reset state ****/\r
+void COMP_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);\r
+void COMP_Cmd(FunctionalState NewState);\r
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);\r
+\r
+/* Window mode control function ***********************************************/\r
+void COMP_WindowCmd(FunctionalState NewState);\r
+\r
+/* Internal Reference Voltage (VREFINT) output function ***********************/\r
+void COMP_VrefintOutputCmd(FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_COMP_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_crc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_CRC_H\r
+#define __STM32L1xx_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+void CRC_ResetDR(void);\r
+uint32_t CRC_CalcCRC(uint32_t Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+void CRC_SetIDRegister(uint8_t IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_CRC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dac.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DAC_H\r
+#define __STM32L1xx_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+ \r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_trigger_selection */\r
+\r
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
+ are generated, or whether no wave is generated.\r
+ This parameter can be a value of @ref DAC_wave_generation */\r
+\r
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
+ the maximum amplitude triangle generation for the DAC channel. \r
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_output_buffer */\r
+}DAC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection \r
+ * @{\r
+ */\r
+ \r
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T9_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_lfsrunmask_triangleamplitude\r
+ * @{\r
+ */\r
+\r
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define DAC_Channel_2 ((uint32_t)0x00000010)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignment \r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DAC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
+ \r
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the DAC configuration to the default reset state *****/ \r
+void DAC_DeInit(void);\r
+\r
+/* DAC channels configuration: trigger, output buffer, data format functions */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+\r
+/* DMA management functions ***************************************************/\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_DAC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the DBGMCU \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DBGMCU_H\r
+#define __STM32L1xx_DBGMCU_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)\r
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_DBGMCU_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dma.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the DMA firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_DMA_H\r
+#define __STM32L1xx_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DMA Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
+ This parameter can be a value of @ref DMA_data_transfer_direction */\r
+\r
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
+ or DMA_MemoryDataSize members depending in the transfer direction. */\r
+\r
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
+\r
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_memory_incremented_mode */\r
+\r
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_peripheral_data_size */\r
+\r
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_memory_data_size */\r
+\r
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_circular_normal_mode.\r
+ @note: The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_priority_level */\r
+\r
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
+ This parameter can be a value of @ref DMA_memory_to_memory */\r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
+ ((PERIPH) == DMA1_Channel2) || \\r
+ ((PERIPH) == DMA1_Channel3) || \\r
+ ((PERIPH) == DMA1_Channel4) || \\r
+ ((PERIPH) == DMA1_Channel5) || \\r
+ ((PERIPH) == DMA1_Channel6) || \\r
+ ((PERIPH) == DMA1_Channel7))\r
+\r
+/** @defgroup DMA_data_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
+ ((DIR) == DMA_DIR_PeripheralSRC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
+ ((STATE) == DMA_PeripheralInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
+ ((STATE) == DMA_MemoryInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_circular_normal_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
+#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_priority_level \r
+ * @{\r
+ */\r
+\r
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
+#define DMA_Priority_High ((uint32_t)0x00002000)\r
+#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
+#define DMA_Priority_Low ((uint32_t)0x00000000)\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_to_memory \r
+ * @{\r
+ */\r
+\r
+#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
+#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define DMA_IT_TC ((uint32_t)0x00000002)\r
+#define DMA_IT_HT ((uint32_t)0x00000004)\r
+#define DMA_IT_TE ((uint32_t)0x00000008)\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
+\r
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flags_definition \r
+ * @{\r
+ */\r
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00))\r
+\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Buffer_Size \r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the DMA configuration to the default reset state *****/ \r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
+\r
+/* Data Counter functions *****************************************************/\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_DMA_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_exti.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the EXTI firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_EXTI_H\r
+#define __STM32L1xx_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief EXTI mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+ * @brief EXTI Trigger enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+ * @brief EXTI Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
+ This parameter can be any combination of @ref EXTI_Lines */\r
+ \r
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Lines \r
+ * @{\r
+ */\r
+\r
+#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */\r
+#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */\r
+#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */\r
+#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */\r
+#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */\r
+#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */\r
+#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */\r
+#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */\r
+#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */\r
+#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */\r
+#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */\r
+#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */\r
+#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */\r
+#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */\r
+#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */\r
+#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */\r
+#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 \r
+ Connected to the PVD Output */\r
+#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17 \r
+ Connected to the RTC Alarm \r
+ event */\r
+#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18 \r
+ Connected to the USB Device \r
+ FS Wakeup from suspend event */\r
+#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19 \r
+ Connected to the RTC Tamper \r
+ and Time Stamp events */ \r
+#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 \r
+ Connected to the RTC Wakeup \r
+ event */\r
+#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 \r
+ Connected to the Comparator 1 \r
+ event */\r
+\r
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 \r
+ Connected to the Comparator 2\r
+ event */\r
+ \r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\r
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \\r
+ ((LINE) == EXTI_Line22))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the EXTI configuration to the default reset state *****/\r
+void EXTI_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_EXTI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_FLASH_H\r
+#define __STM32L1xx_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief FLASH Status \r
+ */ \r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_ERROR_PROGRAM,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup FLASH_Latency \r
+ * @{\r
+ */ \r
+#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */\r
+ \r
+#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */\r
+#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Address \r
+ * @{\r
+ */\r
+ \r
+#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08080FFF))\r
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Option_Bytes_Write_Protection \r
+ * @{\r
+ */\r
+ \r
+\r
+#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */\r
+#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */\r
+#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */\r
+#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */\r
+#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */\r
+#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */\r
+#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */\r
+#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */\r
+#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */\r
+#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */\r
+#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */\r
+#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */\r
+#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */\r
+#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */\r
+#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */\r
+#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */\r
+#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */\r
+#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */\r
+#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */\r
+#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */\r
+#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */\r
+#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */\r
+#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */\r
+#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */\r
+#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */\r
+#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */\r
+#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */\r
+#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */\r
+#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */\r
+#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */\r
+#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */\r
+#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */\r
+\r
+#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */\r
+\r
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_Read_Protection \r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Read Protection Level \r
+ */ \r
+#define OB_RDP_Level_0 ((uint8_t)0xAA)\r
+#define OB_RDP_Level_1 ((uint8_t)0xBB)\r
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 \r
+ it's no more possible to go back to level 1 or 0 */\r
+\r
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\r
+ ((LEVEL) == OB_RDP_Level_1))/*||\\r
+ ((LEVEL) == OB_RDP_Level_2))*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Option_Bytes_IWatchdog \r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */\r
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STOP \r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_BOR_Level \r
+ * @{\r
+ */\r
+\r
+#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD \r
+ power supply reaches the PDR(Power Down Reset) threshold (1.5V) */\r
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */\r
+#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */\r
+#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */\r
+#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */\r
+#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */\r
+\r
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \\r
+ ((LEVEL) == OB_BOR_LEVEL1) || \\r
+ ((LEVEL) == OB_BOR_LEVEL2) || \\r
+ ((LEVEL) == OB_BOR_LEVEL3) || \\r
+ ((LEVEL) == OB_BOR_LEVEL4) || \\r
+ ((LEVEL) == OB_BOR_LEVEL5))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */\r
+#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */\r
+#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */\r
+#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFF0FD) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \\r
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \\r
+ ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */\r
+#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 \r
+ to unlock the RUN_PD bit in FLASH_ACR */\r
+\r
+#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */\r
+#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2\r
+ to unlock the write access to the FLASH_PECR register and\r
+ data EEPROM */\r
+\r
+#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */\r
+#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2\r
+ to unlock the program memory */\r
+\r
+#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */\r
+#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to\r
+ unlock the write access to the option byte block */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup Timeout_definition \r
+ * @{\r
+ */ \r
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+ \r
+/** \r
+ * @brief FLASH memory functions that can be executed from FLASH. \r
+ */ \r
+/* FLASH Interface configuration functions ************************************/ \r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
+\r
+/* FLASH Memory Programming functions *****************************************/ \r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
+\r
+/* DATA EEPROM Programming functions ******************************************/ \r
+void DATA_EEPROM_Unlock(void);\r
+void DATA_EEPROM_Lock(void);\r
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);\r
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
+\r
+/* Option Bytes Programming functions *****************************************/\r
+void FLASH_OB_Unlock(void);\r
+void FLASH_OB_Lock(void);\r
+void FLASH_OB_Launch(void);\r
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+uint8_t FLASH_OB_GetUser(void);\r
+uint32_t FLASH_OB_GetWRP(void);\r
+FlagStatus FLASH_OB_GetRDP(void);\r
+uint8_t FLASH_OB_GetBOR(void);\r
+\r
+/* Interrupts and flags management functions **********************************/ \r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+/** \r
+ * @brief FLASH memory functions that should be executed from internal SRAM.\r
+ * These functions are defined inside the "stm32l1xx_flash_ramfunc.c"\r
+ * file.\r
+ */ \r
+FLASH_Status FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
+FLASH_Status FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);\r
+FLASH_Status DATA_EEPROM_EraseDoubleWord(uint32_t Address);\r
+FLASH_Status DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_FLASH_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the GPIO \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_GPIO_H\r
+#define __STM32L1xx_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB) || \\r
+ ((PERIPH) == GPIOC) || \\r
+ ((PERIPH) == GPIOD) || \\r
+ ((PERIPH) == GPIOE) || \\r
+ ((PERIPH) == GPIOH))\r
+\r
+/** @defgroup Configuration_Mode_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */\r
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */\r
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */\r
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */\r
+}GPIOMode_TypeDef;\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \\r
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_type_enumeration\r
+ * @{\r
+ */ \r
+typedef enum\r
+{ GPIO_OType_PP = 0x00,\r
+ GPIO_OType_OD = 0x01\r
+}GPIOOType_TypeDef;\r
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_Maximum_frequency_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */\r
+ GPIO_Speed_2MHz = 0x01, /*!< Low Speed */\r
+ GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */\r
+ GPIO_Speed_40MHz = 0x03 /*!< High Speed */\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+ ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration \r
+ * @{\r
+ */ \r
+typedef enum\r
+{ GPIO_PuPd_NOPULL = 0x00,\r
+ GPIO_PuPd_UP = 0x01,\r
+ GPIO_PuPd_DOWN = 0x02\r
+}GPIOPuPd_TypeDef;\r
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
+ ((PUPD) == GPIO_PuPd_DOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration\r
+ * @{\r
+ */\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** \r
+ * @brief GPIO Init structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIOMode_TypeDef */\r
+\r
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.\r
+ This parameter can be a value of @ref GPIOOType_TypeDef */\r
+\r
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
+}GPIO_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup GPIO_pins_define \r
+ * @{\r
+ */\r
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+ * @{\r
+ */ \r
+#define GPIO_PinSource0 ((uint8_t)0x00)\r
+#define GPIO_PinSource1 ((uint8_t)0x01)\r
+#define GPIO_PinSource2 ((uint8_t)0x02)\r
+#define GPIO_PinSource3 ((uint8_t)0x03)\r
+#define GPIO_PinSource4 ((uint8_t)0x04)\r
+#define GPIO_PinSource5 ((uint8_t)0x05)\r
+#define GPIO_PinSource6 ((uint8_t)0x06)\r
+#define GPIO_PinSource7 ((uint8_t)0x07)\r
+#define GPIO_PinSource8 ((uint8_t)0x08)\r
+#define GPIO_PinSource9 ((uint8_t)0x09)\r
+#define GPIO_PinSource10 ((uint8_t)0x0A)\r
+#define GPIO_PinSource11 ((uint8_t)0x0B)\r
+#define GPIO_PinSource12 ((uint8_t)0x0C)\r
+#define GPIO_PinSource13 ((uint8_t)0x0D)\r
+#define GPIO_PinSource14 ((uint8_t)0x0E)\r
+#define GPIO_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Alternat_function_selection_define \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */\r
+#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */\r
+#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */\r
+#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */\r
+#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */\r
+#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */\r
+#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */\r
+#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */\r
+#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */\r
+#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */\r
+#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */\r
+#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */\r
+/** \r
+ * @brief AF 14 selection \r
+ */ \r
+#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \\r
+ ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \\r
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \\r
+ ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \\r
+ ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \\r
+ ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \\r
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \\r
+ ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \\r
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\r
+ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \\r
+ ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \\r
+ ((AF) == GPIO_AF_EVENTOUT))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Legacy \r
+ * @{\r
+ */\r
+ \r
+#define GPIO_Mode_AIN GPIO_Mode_AN\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the GPIO configuration to the default reset state ****/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+\r
+/* GPIO Read and Write functions **********************************************/\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+\r
+/* GPIO Alternate functions configuration functions ***************************/\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_GPIO_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the I2C firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_I2C_H\r
+#define __STM32L1xx_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief I2C Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
+ This parameter must be set to a value lower than 400kHz */\r
+\r
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
+ This parameter can be a value of @ref I2C_mode */\r
+\r
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
+\r
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
+ This parameter can be a value of @ref I2C_acknowledgement */\r
+\r
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+ This parameter can be a value of @ref I2C_acknowledged_address */\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+ ((PERIPH) == I2C2))\r
+/** @defgroup I2C_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_Mode_I2C ((uint16_t)0x0000)\r
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_duty_cycle_in_fast_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+ ((CYCLE) == I2C_DutyCycle_2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_acknowledgement\r
+ * @{\r
+ */\r
+\r
+#define I2C_Ack_Enable ((uint16_t)0x0400)\r
+#define I2C_Ack_Disable ((uint16_t)0x0000)\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+ ((STATE) == I2C_Ack_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
+#define I2C_Direction_Receiver ((uint8_t)0x01)\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledged_address \r
+ * @{\r
+ */\r
+\r
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_registers \r
+ * @{\r
+ */\r
+\r
+#define I2C_Register_CR1 ((uint8_t)0x00)\r
+#define I2C_Register_CR2 ((uint8_t)0x04)\r
+#define I2C_Register_OAR1 ((uint8_t)0x08)\r
+#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
+#define I2C_Register_DR ((uint8_t)0x10)\r
+#define I2C_Register_SR1 ((uint8_t)0x14)\r
+#define I2C_Register_SR2 ((uint8_t)0x18)\r
+#define I2C_Register_CCR ((uint8_t)0x1C)\r
+#define I2C_Register_TRISE ((uint8_t)0x20)\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_DR) || \\r
+ ((REGISTER) == I2C_Register_SR1) || \\r
+ ((REGISTER) == I2C_Register_SR2) || \\r
+ ((REGISTER) == I2C_Register_CCR) || \\r
+ ((REGISTER) == I2C_Register_TRISE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_SMBus_alert_pin_level \r
+ * @{\r
+ */\r
+\r
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+ ((ALERT) == I2C_SMBusAlert_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_PEC_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+ ((POSITION) == I2C_PECPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_BUF ((uint16_t)0x0400)\r
+#define I2C_IT_EVT ((uint16_t)0x0200)\r
+#define I2C_IT_ERR ((uint16_t)0x0100)\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
+#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
+#define I2C_IT_OVR ((uint32_t)0x01000800)\r
+#define I2C_IT_AF ((uint32_t)0x01000400)\r
+#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
+#define I2C_IT_BERR ((uint32_t)0x01000100)\r
+#define I2C_IT_TXE ((uint32_t)0x06000080)\r
+#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
+#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
+#define I2C_IT_BTF ((uint32_t)0x02000004)\r
+#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
+#define I2C_IT_SB ((uint32_t)0x02000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_flags_definition \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SR2 register flags \r
+ */\r
+\r
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
+\r
+/** \r
+ * @brief SR1 register flags \r
+ */\r
+\r
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
+#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
+#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Events \r
+ * @{\r
+ */\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Master Events (Events grouped in order of communication) \r
+ =============================================================================== \r
+ */\r
+\r
+/** \r
+ * @brief Communication start\r
+ * \r
+ * After sending the START condition (I2C_GenerateSTART() function) the master \r
+ * has to wait for this event. It means that the Start condition has been correctly \r
+ * released on the I2C bus (the bus is free, no other devices is communicating).\r
+ * \r
+ */\r
+/* --EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/** \r
+ * @brief Address Acknowledge\r
+ * \r
+ * After checking on EV5 (start condition correctly released on the bus), the \r
+ * master sends the address of the slave(s) with which it will communicate \r
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
+ * his address. If an acknowledge is sent on the bus, one of the following events will \r
+ * be set:\r
+ * \r
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
+ * event is set.\r
+ * \r
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
+ * is set\r
+ * \r
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
+ * function). Then master should wait on EV9. It means that the 10-bit addressing \r
+ * header has been correctly sent on the bus. Then master should send the second part of \r
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
+ * should wait for event EV6. \r
+ * \r
+ */\r
+\r
+/* --EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
+/* --EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * If a communication is established (START condition generated and slave address \r
+ * acknowledged) then the master has to check on one of the following events for \r
+ * communication procedures:\r
+ * \r
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
+ * the data received from the slave (I2C_ReceiveData() function).\r
+ * \r
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
+ * function) then to wait on event EV8 or EV8_2.\r
+ * These two events are similar: \r
+ * - EV8 means that the data has been written in the data register and is \r
+ * being shifted out.\r
+ * - EV8_2 means that the data has been physically shifted out and output \r
+ * on the bus.\r
+ * In most cases, using EV8 is sufficient for the application.\r
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
+ * (before Stop condition generation).\r
+ * \r
+ * @note In case the user software does not guarantee that this event EV7 is \r
+ * managed before the current byte end of transfer, then user may check on EV7 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ * \r
+ */\r
+\r
+/* Master RECEIVER mode -----------------------------*/ \r
+/* --EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* Master TRANSMITTER mode --------------------------*/\r
+/* --EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
+/* --EV8_2 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Slave Events (Events grouped in order of communication) \r
+ =============================================================================== \r
+ */\r
+\r
+\r
+/** \r
+ * @brief Communication start events\r
+ * \r
+ * Wait on one of these events at the start of the communication. It means that \r
+ * the I2C peripheral detected a Start condition on the bus (generated by master \r
+ * device) followed by the peripheral address. The peripheral generates an ACK \r
+ * condition on the bus (if the acknowledge feature is enabled through function \r
+ * I2C_AcknowledgeConfig()) and the events listed above are set :\r
+ * \r
+ * 1) In normal case (only one address managed by the slave), when the address \r
+ * sent by the master matches the own address of the peripheral (configured by \r
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
+ * (where XXX could be TRANSMITTER or RECEIVER).\r
+ * \r
+ * 2) In case the address sent by the master matches the second address of the \r
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
+ * \r
+ * 3) In case the address sent by the master is General Call (address 0x00) and \r
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
+ * \r
+ */\r
+\r
+/* --EV1 (all the events below are variants of EV1) */ \r
+/* 1) Case of One Single Address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+\r
+/* 2) Case of Dual address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+\r
+/* 3) Case of General Call enabled for the slave */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * Wait on one of these events when EV1 has already been checked and: \r
+ * \r
+ * - Slave RECEIVER mode:\r
+ * - EV2: When the application is expecting a data byte to be received. \r
+ * - EV4: When the application is expecting the end of the communication: master \r
+ * sends a stop condition and data transmission is stopped.\r
+ * \r
+ * - Slave Transmitter mode:\r
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
+ * used when the user software doesn't guarantee the EV3 is managed before the\r
+ * current byte end of transfer.\r
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
+ * shall end (before sending the STOP condition). In this case slave has to stop sending \r
+ * data bytes and expect a Stop condition on the bus.\r
+ * \r
+ * @note In case the user software does not guarantee that the event EV2 is \r
+ * managed before the current byte end of transfer, then user may check on EV2 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+\r
+/* Slave RECEIVER mode --------------------------*/ \r
+/* --EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
+/* --EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
+\r
+/* Slave TRANSMITTER mode -----------------------*/\r
+/* --EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
+/* --EV3_2 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
+\r
+/**\r
+ ===============================================================================\r
+ End of Events Description \r
+ =============================================================================== \r
+ */\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address1 \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_clock_speed \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the I2C configuration to the default reset state *****/\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+\r
+/* PEC management functions ***************************************************/ \r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+\r
+\r
+/* Interrupts, events and flags management functions **************************/\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief\r
+ * \r
+@verbatim \r
+ ===============================================================================\r
+ I2C State Monitoring Functions \r
+ =============================================================================== \r
+ This I2C driver provides three different ways for I2C state monitoring\r
+ depending on the application requirements and constraints:\r
+ \r
+ \r
+ 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
+ -----------------------------------------------------------\r
+ It compares the status registers (SR1 and SR2) content to a given event\r
+ (can be the combination of one or more flags).\r
+ It returns SUCCESS if the current status includes the given flags \r
+ and returns ERROR if one or more flags are missing in the current status.\r
+\r
+ - When to use\r
+ - This function is suitable for most applications as well as for startup \r
+ activity since the events are fully described in the product reference \r
+ manual (RM0038).\r
+ - It is also suitable for users who need to define their own events.\r
+\r
+ - Limitations\r
+ - If an error occurs (ie. error flags are set besides to the monitored \r
+ flags), the I2C_CheckEvent() function may return SUCCESS despite \r
+ the communication hold or corrupted real state. \r
+ In this case, it is advised to use error interrupts to monitor \r
+ the error events and handle them in the interrupt IRQ handler.\r
+ \r
+ @note \r
+ For error management, it is advised to use the following functions:\r
+ - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
+ Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
+ - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
+ and/or I2C_GenerateStop() in order to clear the error flag and source \r
+ and return to correct communciation status.\r
+ \r
+ \r
+ 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
+ -------------------------------------------------------------------- \r
+ Using the function I2C_GetLastEvent() which returns the image of both status \r
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ by 16 bits and concatenated to Status Register 1).\r
+\r
+ - When to use\r
+ - This function is suitable for the same applications above but it \r
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
+ function.\r
+ - The returned value could be compared to events already defined in \r
+ the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
+ This function is suitable when multiple flags are monitored at the \r
+ same time.\r
+ - At the opposite of I2C_CheckEvent() function, this function allows \r
+ user to choose when an event is accepted (when all events flags are \r
+ set and no other flags are set or just when the needed flags are set \r
+ like I2C_CheckEvent() function.\r
+\r
+ - Limitations\r
+ - User may need to define his own events.\r
+ - Same remark concerning the error management is applicable for this \r
+ function if user decides to check only regular communication flags \r
+ (and ignores error flags).\r
+ \r
+ \r
+ 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
+ -----------------------------------------------------------------------\r
+ \r
+ Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ one single flag (ie. I2C_FLAG_RXNE ...). \r
+\r
+ - When to use\r
+ - This function could be used for specific applications or in debug \r
+ phase.\r
+ - It is suitable when only one flag checking is needed (most I2C \r
+ events are monitored through multiple flags).\r
+ - Limitations: \r
+ - When calling this function, the Status register is accessed. \r
+ Some flags are cleared when the status register is accessed. \r
+ So checking the status of one Flag, may clear other ones.\r
+ - Function may need to be called twice or more in order to monitor \r
+ one single event.\r
+ \r
+ For detailed description of Events, please refer to section I2C_Events in \r
+ stm32l1xx_i2c.h file.\r
+ \r
+@endverbatim\r
+ * \r
+ */\r
+\r
+/**\r
+ ===============================================================================\r
+ 1. Basic state monitoring \r
+ =============================================================================== \r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
+/**\r
+ ===============================================================================\r
+ 2. Advanced state monitoring \r
+ =============================================================================== \r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+/**\r
+ ===============================================================================\r
+ 3. Flag-based state monitoring \r
+ =============================================================================== \r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+\r
+\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_I2C_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the IWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_IWDG_H\r
+#define __STM32L1xx_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_WriteAccess\r
+ * @{\r
+ */\r
+\r
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
+#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
+#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
+#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
+#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
+#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
+#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Flag \r
+ * @{\r
+ */\r
+\r
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Prescaler and Counter configuration functions ******************************/\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
+void IWDG_SetReload(uint16_t Reload);\r
+void IWDG_ReloadCounter(void);\r
+\r
+/* IWDG activation function ***************************************************/\r
+void IWDG_Enable(void);\r
+\r
+/* Flag management function ***************************************************/\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_IWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_lcd.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the LCD firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_LCD_H\r
+#define __STM32L1xx_LCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup LCD\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+ \r
+/** \r
+ * @brief LCD Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler. \r
+ This parameter can be one value of @ref LCD_Prescaler */\r
+ uint32_t LCD_Divider; /*!< Configures the LCD Divider.\r
+ This parameter can be one value of @ref LCD_Divider */\r
+ uint32_t LCD_Duty; /*!< Configures the LCD Duty.\r
+ This parameter can be one value of @ref LCD_Duty */\r
+ uint32_t LCD_Bias; /*!< Configures the LCD Bias.\r
+ This parameter can be one value of @ref LCD_Bias */ \r
+ uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source.\r
+ This parameter can be one value of @ref LCD_Voltage_Source */\r
+}LCD_InitTypeDef;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup LCD_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */\r
+#define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */\r
+#define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */\r
+#define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */\r
+#define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */\r
+#define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */\r
+#define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */\r
+#define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */\r
+#define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */\r
+#define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */\r
+#define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */\r
+#define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */\r
+#define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */\r
+#define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */\r
+#define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */\r
+#define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */\r
+\r
+#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \\r
+ ((PRESCALER) == LCD_Prescaler_2) || \\r
+ ((PRESCALER) == LCD_Prescaler_4) || \\r
+ ((PRESCALER) == LCD_Prescaler_8) || \\r
+ ((PRESCALER) == LCD_Prescaler_16) || \\r
+ ((PRESCALER) == LCD_Prescaler_32) || \\r
+ ((PRESCALER) == LCD_Prescaler_64) || \\r
+ ((PRESCALER) == LCD_Prescaler_128) || \\r
+ ((PRESCALER) == LCD_Prescaler_256) || \\r
+ ((PRESCALER) == LCD_Prescaler_512) || \\r
+ ((PRESCALER) == LCD_Prescaler_1024) || \\r
+ ((PRESCALER) == LCD_Prescaler_2048) || \\r
+ ((PRESCALER) == LCD_Prescaler_4096) || \\r
+ ((PRESCALER) == LCD_Prescaler_8192) || \\r
+ ((PRESCALER) == LCD_Prescaler_16384) || \\r
+ ((PRESCALER) == LCD_Prescaler_32768))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LCD_Divider \r
+ * @{\r
+ */\r
+\r
+#define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */\r
+#define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */\r
+#define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */\r
+#define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */\r
+#define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */\r
+#define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */\r
+#define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */\r
+#define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */\r
+#define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */\r
+#define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */\r
+#define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */\r
+#define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */\r
+#define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */\r
+#define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */\r
+#define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */\r
+#define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */\r
+\r
+#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \\r
+ ((DIVIDER) == LCD_Divider_17) || \\r
+ ((DIVIDER) == LCD_Divider_18) || \\r
+ ((DIVIDER) == LCD_Divider_19) || \\r
+ ((DIVIDER) == LCD_Divider_20) || \\r
+ ((DIVIDER) == LCD_Divider_21) || \\r
+ ((DIVIDER) == LCD_Divider_22) || \\r
+ ((DIVIDER) == LCD_Divider_23) || \\r
+ ((DIVIDER) == LCD_Divider_24) || \\r
+ ((DIVIDER) == LCD_Divider_25) || \\r
+ ((DIVIDER) == LCD_Divider_26) || \\r
+ ((DIVIDER) == LCD_Divider_27) || \\r
+ ((DIVIDER) == LCD_Divider_28) || \\r
+ ((DIVIDER) == LCD_Divider_29) || \\r
+ ((DIVIDER) == LCD_Divider_30) || \\r
+ ((DIVIDER) == LCD_Divider_31))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LCD_Duty \r
+ * @{\r
+ */\r
+ \r
+#define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */\r
+#define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */\r
+#define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */\r
+#define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */\r
+#define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */\r
+\r
+#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \\r
+ ((DUTY) == LCD_Duty_1_2) || \\r
+ ((DUTY) == LCD_Duty_1_3) || \\r
+ ((DUTY) == LCD_Duty_1_4) || \\r
+ ((DUTY) == LCD_Duty_1_8))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+\r
+/** @defgroup LCD_Bias \r
+ * @{\r
+ */\r
+ \r
+#define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */\r
+#define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */\r
+#define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */\r
+\r
+#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \\r
+ ((BIAS) == LCD_Bias_1_2) || \\r
+ ((BIAS) == LCD_Bias_1_3))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup LCD_Voltage_Source \r
+ * @{\r
+ */\r
+ \r
+#define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */\r
+#define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */\r
+\r
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \\r
+ ((SOURCE) == LCD_VoltageSource_External))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_Interrupts \r
+ * @{\r
+ */\r
+#define LCD_IT_SOF LCD_FCR_SOFIE\r
+#define LCD_IT_UDD LCD_FCR_UDDIE\r
+\r
+#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_PulseOnDuration \r
+ * @{\r
+ */\r
+\r
+#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */\r
+#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */\r
+#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */\r
+#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */\r
+#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */\r
+#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */\r
+#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */\r
+#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */\r
+\r
+#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \\r
+ ((DURATION) == LCD_PulseOnDuration_1) || \\r
+ ((DURATION) == LCD_PulseOnDuration_2) || \\r
+ ((DURATION) == LCD_PulseOnDuration_3) || \\r
+ ((DURATION) == LCD_PulseOnDuration_4) || \\r
+ ((DURATION) == LCD_PulseOnDuration_5) || \\r
+ ((DURATION) == LCD_PulseOnDuration_6) || \\r
+ ((DURATION) == LCD_PulseOnDuration_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LCD_DeadTime \r
+ * @{\r
+ */\r
+\r
+#define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */\r
+#define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */\r
+#define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */\r
+#define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */\r
+#define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */\r
+#define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */\r
+#define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */\r
+#define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */\r
+\r
+#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \\r
+ ((TIME) == LCD_DeadTime_1) || \\r
+ ((TIME) == LCD_DeadTime_2) || \\r
+ ((TIME) == LCD_DeadTime_3) || \\r
+ ((TIME) == LCD_DeadTime_4) || \\r
+ ((TIME) == LCD_DeadTime_5) || \\r
+ ((TIME) == LCD_DeadTime_6) || \\r
+ ((TIME) == LCD_DeadTime_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_BlinkMode \r
+ * @{\r
+ */\r
+\r
+#define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */\r
+#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */\r
+#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to \r
+ 8 pixels according to the programmed duty) */\r
+#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */\r
+\r
+#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \\r
+ ((MODE) == LCD_BlinkMode_SEG0_COM0) || \\r
+ ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \\r
+ ((MODE) == LCD_BlinkMode_AllSEG_AllCOM))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_BlinkFrequency \r
+ * @{\r
+ */\r
+\r
+#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */\r
+#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */\r
+#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */\r
+#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */\r
+#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */\r
+#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */\r
+#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */\r
+#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */\r
+\r
+#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \\r
+ ((FREQUENCY) == LCD_BlinkFrequency_Div1024))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Contrast \r
+ * @{\r
+ */\r
+\r
+#define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */\r
+#define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */\r
+#define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */\r
+#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */\r
+#define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */\r
+#define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */\r
+#define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */\r
+#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */\r
+\r
+#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_1) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_2) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_3) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_4) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_5) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_6) || \\r
+ ((CONTRAST) == LCD_Contrast_Level_7))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LCD_Flag \r
+ * @{\r
+ */\r
+\r
+#define LCD_FLAG_ENS LCD_SR_ENS\r
+#define LCD_FLAG_SOF LCD_SR_SOF\r
+#define LCD_FLAG_UDR LCD_SR_UDR\r
+#define LCD_FLAG_UDD LCD_SR_UDD\r
+#define LCD_FLAG_RDY LCD_SR_RDY\r
+#define LCD_FLAG_FCRSF LCD_SR_FCRSR\r
+\r
+#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \\r
+ ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \\r
+ ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))\r
+\r
+#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LCD_RAMRegister \r
+ * @{\r
+ */\r
+\r
+#define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */\r
+#define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */\r
+#define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */\r
+#define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */\r
+#define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */\r
+#define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */\r
+#define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */\r
+#define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */\r
+#define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */\r
+#define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */\r
+#define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */\r
+#define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */\r
+#define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */\r
+#define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */\r
+#define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */\r
+#define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */\r
+\r
+#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \\r
+ ((REGISTER) == LCD_RAMRegister_1) || \\r
+ ((REGISTER) == LCD_RAMRegister_2) || \\r
+ ((REGISTER) == LCD_RAMRegister_3) || \\r
+ ((REGISTER) == LCD_RAMRegister_4) || \\r
+ ((REGISTER) == LCD_RAMRegister_5) || \\r
+ ((REGISTER) == LCD_RAMRegister_6) || \\r
+ ((REGISTER) == LCD_RAMRegister_7) || \\r
+ ((REGISTER) == LCD_RAMRegister_8) || \\r
+ ((REGISTER) == LCD_RAMRegister_9) || \\r
+ ((REGISTER) == LCD_RAMRegister_10) || \\r
+ ((REGISTER) == LCD_RAMRegister_11) || \\r
+ ((REGISTER) == LCD_RAMRegister_12) || \\r
+ ((REGISTER) == LCD_RAMRegister_13) || \\r
+ ((REGISTER) == LCD_RAMRegister_14) || \\r
+ ((REGISTER) == LCD_RAMRegister_15))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the LCD configuration to the default reset state *****/\r
+void LCD_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct);\r
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct);\r
+void LCD_Cmd(FunctionalState NewState);\r
+void LCD_WaitForSynchro(void);\r
+void LCD_HighDriveCmd(FunctionalState NewState);\r
+void LCD_MuxSegmentCmd(FunctionalState NewState);\r
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration);\r
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime);\r
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency);\r
+void LCD_ContrastConfig(uint32_t LCD_Contrast);\r
+\r
+/* LCD RAM memory write functions *********************************************/\r
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data);\r
+void LCD_UpdateDisplayRequest(void);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState);\r
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG);\r
+void LCD_ClearFlag(uint32_t LCD_FLAG);\r
+ITStatus LCD_GetITStatus(uint32_t LCD_IT);\r
+void LCD_ClearITPendingBit(uint32_t LCD_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_LCD_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_PWR_H\r
+#define __STM32L1xx_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage \r
+ (Compare internally to VREFINT) */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WakeUp_Pins \r
+ * @{\r
+ */\r
+\r
+#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)\r
+#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)\r
+#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \\r
+ ((PIN) == PWR_WakeUpPin_2) || \\r
+ ((PIN) == PWR_WakeUpPin_3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup Voltage_Scaling_Ranges\r
+ * @{\r
+ */\r
+\r
+#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0\r
+#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1\r
+#define PWR_VoltageScaling_Range3 PWR_CR_VOS\r
+\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range2) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range3))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup Regulator_state_is_Sleep_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SLEEP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU PWR_CSR_WUF\r
+#define PWR_FLAG_SB PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF\r
+#define PWR_FLAG_VOS PWR_CSR_VOSF\r
+#define PWR_FLAG_REGLP PWR_CSR_REGLPF\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \\r
+ ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the PWR configuration to the default reset state ******/ \r
+void PWR_DeInit(void);\r
+\r
+/* RTC Domain Access function *************************************************/ \r
+void PWR_RTCAccessCmd(FunctionalState NewState);\r
+\r
+/* PVD configuration functions ************************************************/ \r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+\r
+/* WakeUp pins configuration functions ****************************************/ \r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);\r
+\r
+/* Ultra Low Power mode configuration functions *******************************/ \r
+void PWR_FastWakeUpCmd(FunctionalState NewState);\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState);\r
+\r
+/* Voltage Scaling configuration functions ************************************/ \r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);\r
+\r
+/* Low Power modes configuration functions ************************************/ \r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState);\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+\r
+/* Flags management functions *************************************************/ \r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_PWR_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the RCC \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RCC_H\r
+#define __STM32L1xx_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency;\r
+ uint32_t HCLK_Frequency;\r
+ uint32_t PCLK1_Frequency;\r
+ uint32_t PCLK2_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_HSE_OFF ((uint8_t)0x00)\r
+#define RCC_HSE_ON ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup MSI_Clock_Range \r
+ * @{\r
+ */\r
+\r
+#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */\r
+#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */\r
+#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */\r
+#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */\r
+#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */\r
+#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */\r
+#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */\r
+\r
+#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \\r
+ ((RANGE) == RCC_MSIRange_1) || \\r
+ ((RANGE) == RCC_MSIRange_2) || \\r
+ ((RANGE) == RCC_MSIRange_3) || \\r
+ ((RANGE) == RCC_MSIRange_4) || \\r
+ ((RANGE) == RCC_MSIRange_5) || \\r
+ ((RANGE) == RCC_MSIRange_6))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PLL_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSource_HSI ((uint8_t)0x00)\r
+#define RCC_PLLSource_HSE ((uint8_t)0x01)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PLL_Multiplication_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLMul_3 ((uint8_t)0x00)\r
+#define RCC_PLLMul_4 ((uint8_t)0x04)\r
+#define RCC_PLLMul_6 ((uint8_t)0x08)\r
+#define RCC_PLLMul_8 ((uint8_t)0x0C)\r
+#define RCC_PLLMul_12 ((uint8_t)0x10)\r
+#define RCC_PLLMul_16 ((uint8_t)0x14)\r
+#define RCC_PLLMul_24 ((uint8_t)0x18)\r
+#define RCC_PLLMul_32 ((uint8_t)0x1C)\r
+#define RCC_PLLMul_48 ((uint8_t)0x20)\r
+\r
+\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \\r
+ ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \\r
+ ((MUL) == RCC_PLLMul_48))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PLL_Divider_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLDiv_2 ((uint8_t)0x40)\r
+#define RCC_PLLDiv_3 ((uint8_t)0x80)\r
+#define RCC_PLLDiv_4 ((uint8_t)0xC0)\r
+\r
+\r
+#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \\r
+ ((DIV) == RCC_PLLDiv_4))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup System_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI\r
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_APB2_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup RCC_Interrupt_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_MSIRDY ((uint8_t)0x20)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \\r
+ ((IT) == RCC_IT_CSS))\r
+\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LSE_Configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSE_OFF ((uint8_t)0x00)\r
+#define RCC_LSE_ON ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE\r
+#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI\r
+#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE\r
+#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)\r
+#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)\r
+#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN\r
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN\r
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN\r
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN\r
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN\r
+#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN\r
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN\r
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN\r
+#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN\r
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup APB2_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN\r
+#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN\r
+#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN\r
+#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN\r
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN\r
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN\r
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN\r
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN\r
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN\r
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN\r
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN\r
+#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN\r
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN\r
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN\r
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN\r
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN\r
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN\r
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN\r
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN\r
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN\r
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN\r
+#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MCO_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)\r
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)\r
+#define RCC_MCOSource_HSI ((uint8_t)0x02)\r
+#define RCC_MCOSource_MSI ((uint8_t)0x03)\r
+#define RCC_MCOSource_HSE ((uint8_t)0x04)\r
+#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)\r
+#define RCC_MCOSource_LSI ((uint8_t)0x06)\r
+#define RCC_MCOSource_LSE ((uint8_t)0x07)\r
+\r
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \\r
+ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MCO_Output_Divider \r
+ * @{\r
+ */\r
+\r
+#define RCC_MCODiv_1 ((uint8_t)0x00)\r
+#define RCC_MCODiv_2 ((uint8_t)0x10)\r
+#define RCC_MCODiv_4 ((uint8_t)0x20)\r
+#define RCC_MCODiv_8 ((uint8_t)0x30)\r
+#define RCC_MCODiv_16 ((uint8_t)0x40)\r
+\r
+#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \\r
+ ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \\r
+ ((DIV) == RCC_MCODiv_16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_MSIRDY ((uint8_t)0x29)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x49)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)\r
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \\r
+ ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RCC clock configuration to the default reset state */\r
+void RCC_DeInit(void);\r
+\r
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);\r
+void RCC_MSICmd(FunctionalState NewState);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);\r
+\r
+/* System, AHB and APB busses clocks configuration functions ******************/\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+\r
+/* Peripheral clocks configuration functions **********************************/\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_RTCResetCmd(FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_RCC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the RTC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RTC_H\r
+#define __STM32L1xx_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief RTC Init structures definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.\r
+ This parameter can be a value of @ref RTC_Hour_Formats */\r
+ \r
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x7F */\r
+ \r
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x1FFF */ \r
+}RTC_InitTypeDef;\r
+\r
+/** \r
+ * @brief RTC Time structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.\r
+ This parameter must be set to a value in the 0-12 range\r
+ if the RTC_HourFormat_12 is selected or 0-23 range if\r
+ the RTC_HourFormat_24 is selected. */\r
+\r
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+ \r
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+\r
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.\r
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */\r
+}RTC_TimeTypeDef; \r
+\r
+/** \r
+ * @brief RTC Date structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+ \r
+ uint32_t RTC_Month; /*!< Specifies the RTC Date Month.\r
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */\r
+\r
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.\r
+ This parameter must be set to a value in the 1-31 range. */\r
+ \r
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.\r
+ This parameter must be set to a value in the 0-99 range. */\r
+}RTC_DateTypeDef;\r
+\r
+/** \r
+ * @brief RTC Alarm structure definition \r
+ */\r
+typedef struct\r
+{\r
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */\r
+\r
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.\r
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r
+\r
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r
+ \r
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r
+ This parameter must be set to a value in the 1-31 range \r
+ if the Alarm Date is selected.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions \r
+ if the Alarm WeekDay is selected. */\r
+}RTC_AlarmTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Hour_Formats \r
+ * @{\r
+ */ \r
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)\r
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)\r
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \\r
+ ((FORMAT) == RTC_HourFormat_24))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Asynchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Synchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))\r
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)\r
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)\r
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_AM_PM_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_H12_AM ((uint8_t)0x00)\r
+#define RTC_H12_PM ((uint8_t)0x40)\r
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Year_Date_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Month_Date_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Month_January ((uint32_t)0x00000001)\r
+#define RTC_Month_February ((uint32_t)0x00000002)\r
+#define RTC_Month_March ((uint32_t)0x00000003)\r
+#define RTC_Month_April ((uint32_t)0x00000004)\r
+#define RTC_Month_May ((uint32_t)0x00000005)\r
+#define RTC_Month_June ((uint32_t)0x00000006)\r
+#define RTC_Month_July ((uint32_t)0x00000007)\r
+#define RTC_Month_August ((uint32_t)0x00000008)\r
+#define RTC_Month_September ((uint32_t)0x00000009)\r
+#define RTC_Month_October ((uint32_t)0x00000010)\r
+#define RTC_Month_November ((uint32_t)0x00000011)\r
+#define RTC_Month_December ((uint32_t)0x00000012)\r
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))\r
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_WeekDay_Definitions \r
+ * @{\r
+ */ \r
+ \r
+#define RTC_Weekday_Monday ((uint32_t)0x00000001)\r
+#define RTC_Weekday_Tuesday ((uint32_t)0x00000002)\r
+#define RTC_Weekday_Wednesday ((uint32_t)0x00000003)\r
+#define RTC_Weekday_Thursday ((uint32_t)0x00000004)\r
+#define RTC_Weekday_Friday ((uint32_t)0x00000005)\r
+#define RTC_Weekday_Saturday ((uint32_t)0x00000006)\r
+#define RTC_Weekday_Sunday ((uint32_t)0x00000007)\r
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Alarm_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmDateWeekDay_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) \r
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) \r
+\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \\r
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmMask_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)\r
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) \r
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)\r
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)\r
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)\r
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)\r
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarms_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Alarm_A ((uint32_t)0x00000100)\r
+#define RTC_Alarm_B ((uint32_t)0x00000200)\r
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))\r
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Wakeup_Timer_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)\r
+#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)\r
+#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)\r
+#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)\r
+#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)\r
+#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)\r
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))\r
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Stamp_Edges_definitions \r
+ * @{\r
+ */ \r
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)\r
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)\r
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \\r
+ ((EDGE) == RTC_TimeStampEdge_Falling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Output_Disable ((uint32_t)0x00000000)\r
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)\r
+#define RTC_Output_AlarmB ((uint32_t)0x00400000)\r
+#define RTC_Output_WakeUp ((uint32_t)0x00600000)\r
+ \r
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \\r
+ ((OUTPUT) == RTC_Output_AlarmA) || \\r
+ ((OUTPUT) == RTC_Output_AlarmB) || \\r
+ ((OUTPUT) == RTC_Output_WakeUp))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_Polarity_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)\r
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)\r
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \\r
+ ((POL) == RTC_OutputPolarity_Low))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Digital_Calibration_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_CalibSign_Positive ((uint32_t)0x00000000) \r
+#define RTC_CalibSign_Negative ((uint32_t)0x00000080)\r
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \\r
+ ((SIGN) == RTC_CalibSign_Negative))\r
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_DayLightSaving_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)\r
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \\r
+ ((SAVE) == RTC_DayLightSaving_ADD1H))\r
+\r
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)\r
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)\r
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \\r
+ ((OPERATION) == RTC_StoreOperation_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Trigger_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)\r
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Pins_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E\r
+#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RTC_Output_Type_ALARM_OUT \r
+ * @{\r
+ */ \r
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)\r
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)\r
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \\r
+ ((TYPE) == RTC_OutputType_PushPull)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Backup_Registers_Definitions \r
+ * @{\r
+ */ \r
+\r
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)\r
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)\r
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)\r
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)\r
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)\r
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)\r
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)\r
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)\r
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)\r
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)\r
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)\r
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)\r
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)\r
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)\r
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)\r
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \\r
+ ((BKP) == RTC_BKP_DR1) || \\r
+ ((BKP) == RTC_BKP_DR2) || \\r
+ ((BKP) == RTC_BKP_DR3) || \\r
+ ((BKP) == RTC_BKP_DR4) || \\r
+ ((BKP) == RTC_BKP_DR5) || \\r
+ ((BKP) == RTC_BKP_DR6) || \\r
+ ((BKP) == RTC_BKP_DR7) || \\r
+ ((BKP) == RTC_BKP_DR8) || \\r
+ ((BKP) == RTC_BKP_DR9) || \\r
+ ((BKP) == RTC_BKP_DR10) || \\r
+ ((BKP) == RTC_BKP_DR11) || \\r
+ ((BKP) == RTC_BKP_DR12) || \\r
+ ((BKP) == RTC_BKP_DR13) || \\r
+ ((BKP) == RTC_BKP_DR14) || \\r
+ ((BKP) == RTC_BKP_DR15) || \\r
+ ((BKP) == RTC_BKP_DR16) || \\r
+ ((BKP) == RTC_BKP_DR17) || \\r
+ ((BKP) == RTC_BKP_DR18) || \\r
+ ((BKP) == RTC_BKP_DR19))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Input_parameter_format_definitions \r
+ * @{\r
+ */ \r
+#define RTC_Format_BIN ((uint32_t)0x000000000)\r
+#define RTC_Format_BCD ((uint32_t)0x000000001)\r
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Flags_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)\r
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)\r
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)\r
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)\r
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)\r
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \\r
+ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \\r
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \\r
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \\r
+ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \\r
+ ((FLAG) == RTC_FLAG_TAMP1F))\r
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Interrupts_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_IT_TS ((uint32_t)0x00008000)\r
+#define RTC_IT_WUT ((uint32_t)0x00004000)\r
+#define RTC_IT_ALRB ((uint32_t)0x00002000)\r
+#define RTC_IT_ALRA ((uint32_t)0x00001000)\r
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */\r
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)\r
+\r
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \\r
+ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \\r
+ ((IT) == RTC_IT_TAMP1))\r
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the RTC configuration to the default reset state *****/ \r
+ErrorStatus RTC_DeInit(void);\r
+\r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_WriteProtectionCmd(FunctionalState NewState);\r
+ErrorStatus RTC_EnterInitMode(void);\r
+void RTC_ExitInitMode(void);\r
+ErrorStatus RTC_WaitForSynchro(void);\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);\r
+\r
+/* Time and Date configuration functions **************************************/ \r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+\r
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/ \r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);\r
+\r
+/* WakeUp Timer configuration functions ***************************************/ \r
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);\r
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);\r
+uint32_t RTC_GetWakeUpCounter(void);\r
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);\r
+\r
+/* Daylight Saving configuration functions ************************************/ \r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);\r
+uint32_t RTC_GetStoreOperation(void);\r
+\r
+/* Output pin Configuration function ******************************************/ \r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);\r
+\r
+/* Digital Calibration configuration functions ********************************/ \r
+ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);\r
+ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState);\r
+void RTC_CalibOutputCmd(FunctionalState NewState);\r
+\r
+/* TimeStamp configuration functions ******************************************/ \r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
+ RTC_DateTypeDef* RTC_StampDateStruct);\r
+ \r
+\r
+/* Tampers configuration functions ********************************************/ \r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);\r
+\r
+/* Backup Data Registers configuration functions ******************************/ \r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);\r
+\r
+/* Output Type Config configuration functions *********************************/ \r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);\r
+\r
+\r
+/* Interrupts and flags management functions **********************************/ \r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);\r
+void RTC_ClearFlag(uint32_t RTC_FLAG);\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_RTC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_spi.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the SPI \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SPI_H\r
+#define __STM32L1xx_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief SPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+ This parameter can be any combination of @ref SPI_data_direction */\r
+\r
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be any combination of @ref SPI_mode */\r
+\r
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be any combination of @ref SPI_data_size */\r
+\r
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
+ This parameter can be any combination of @ref SPI_Clock_Polarity */\r
+\r
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be any combination of @ref SPI_Clock_Phase */\r
+\r
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be any combination of @ref SPI_Slave_Select_management */\r
+ \r
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be any combination of @ref SPI_BaudRate_Prescaler.\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be any combination of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2))\r
+\r
+/** @defgroup SPI_data_direction \r
+ * @{\r
+ */\r
+ \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_mode \r
+ * @{\r
+ */\r
+\r
+#define SPI_Mode_Master ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_data_size \r
+ * @{\r
+ */\r
+\r
+#define SPI_DataSize_16b ((uint16_t)0x0800)\r
+#define SPI_DataSize_8b ((uint16_t)0x0000)\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+ ((DATASIZE) == SPI_DataSize_8b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPOL_Low ((uint16_t)0x0000)\r
+#define SPI_CPOL_High ((uint16_t)0x0002)\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSS_Soft ((uint16_t)0x0200)\r
+#define SPI_NSS_Hard ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+ * @{\r
+ */\r
+\r
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSS_internal_software_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_CRC_Tx ((uint8_t)0x00)\r
+#define SPI_CRC_Rx ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+\r
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
+#define SPI_IT_MODF ((uint8_t)0x55)\r
+#define SPI_IT_CRCERR ((uint8_t)0x54)\r
+\r
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
+\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \\r
+ ((IT) == SPI_I2S_IT_OVR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
+#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Legacy \r
+ * @{\r
+ */\r
+\r
+#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx\r
+#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx\r
+#define SPI_IT_TXE SPI_I2S_IT_TXE\r
+#define SPI_IT_RXNE SPI_I2S_IT_RXNE\r
+#define SPI_IT_ERR SPI_I2S_IT_ERR\r
+#define SPI_IT_OVR SPI_I2S_IT_OVR\r
+#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE\r
+#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE\r
+#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR\r
+#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY\r
+#define SPI_DeInit SPI_I2S_DeInit\r
+#define SPI_ITConfig SPI_I2S_ITConfig\r
+#define SPI_DMACmd SPI_I2S_DMACmd\r
+#define SPI_SendData SPI_I2S_SendData\r
+#define SPI_ReceiveData SPI_I2S_ReceiveData\r
+#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus\r
+#define SPI_ClearFlag SPI_I2S_ClearFlag\r
+#define SPI_GetITStatus SPI_I2S_GetITStatus\r
+#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the SPI configuration to the default reset state *****/ \r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
+\r
+/* Hardware CRC Calculation functions *****************************************/\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SPI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_syscfg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the SYSCFG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/*!< Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SYSCFG_H\r
+#define __STM32L1xx_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SYSCFG\r
+ * @{\r
+ */ \r
+ \r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup EXTI_Port_Sources \r
+ * @{\r
+ */ \r
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04)\r
+#define EXTI_PortSourceGPIOH ((uint8_t)0x05)\r
+ \r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOH)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Pin_sources \r
+ * @{\r
+ */ \r
+#define EXTI_PinSource0 ((uint8_t)0x00)\r
+#define EXTI_PinSource1 ((uint8_t)0x01)\r
+#define EXTI_PinSource2 ((uint8_t)0x02)\r
+#define EXTI_PinSource3 ((uint8_t)0x03)\r
+#define EXTI_PinSource4 ((uint8_t)0x04)\r
+#define EXTI_PinSource5 ((uint8_t)0x05)\r
+#define EXTI_PinSource6 ((uint8_t)0x06)\r
+#define EXTI_PinSource7 ((uint8_t)0x07)\r
+#define EXTI_PinSource8 ((uint8_t)0x08)\r
+#define EXTI_PinSource9 ((uint8_t)0x09)\r
+#define EXTI_PinSource10 ((uint8_t)0x0A)\r
+#define EXTI_PinSource11 ((uint8_t)0x0B)\r
+#define EXTI_PinSource12 ((uint8_t)0x0C)\r
+#define EXTI_PinSource13 ((uint8_t)0x0D)\r
+#define EXTI_PinSource14 ((uint8_t)0x0E)\r
+#define EXTI_PinSource15 ((uint8_t)0x0F)\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+ ((PINSOURCE) == EXTI_PinSource1) || \\r
+ ((PINSOURCE) == EXTI_PinSource2) || \\r
+ ((PINSOURCE) == EXTI_PinSource3) || \\r
+ ((PINSOURCE) == EXTI_PinSource4) || \\r
+ ((PINSOURCE) == EXTI_PinSource5) || \\r
+ ((PINSOURCE) == EXTI_PinSource6) || \\r
+ ((PINSOURCE) == EXTI_PinSource7) || \\r
+ ((PINSOURCE) == EXTI_PinSource8) || \\r
+ ((PINSOURCE) == EXTI_PinSource9) || \\r
+ ((PINSOURCE) == EXTI_PinSource10) || \\r
+ ((PINSOURCE) == EXTI_PinSource11) || \\r
+ ((PINSOURCE) == EXTI_PinSource12) || \\r
+ ((PINSOURCE) == EXTI_PinSource13) || \\r
+ ((PINSOURCE) == EXTI_PinSource14) || \\r
+ ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r
+ \r
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RI_Resistor\r
+ * @{\r
+ */\r
+\r
+#define RI_Resistor_10KPU COMP_CSR_10KPU\r
+#define RI_Resistor_400KPU COMP_CSR_400KPU\r
+#define RI_Resistor_10KPD COMP_CSR_10KPD\r
+#define RI_Resistor_400KPD COMP_CSR_400KPD\r
+\r
+#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \\r
+ ((RESISTOR) == COMP_CSR_400KPU) || \\r
+ ((RESISTOR) == COMP_CSR_10KPD) || \\r
+ ((RESISTOR) == COMP_CSR_400KPD))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_InputCapture\r
+ * @{\r
+ */ \r
+ \r
+#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */\r
+#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */\r
+#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */\r
+#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */\r
+\r
+#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Select\r
+ * @{\r
+ */ \r
+ \r
+#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */\r
+#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */\r
+#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */\r
+#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \\r
+ ((TIM) == TIM_Select_TIM2) || \\r
+ ((TIM) == TIM_Select_TIM3) || \\r
+ ((TIM) == TIM_Select_TIM4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RI_InputCaptureRouting\r
+ * @{\r
+ */ \r
+ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ \r
+#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */\r
+#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */\r
+#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */\r
+#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */\r
+#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */\r
+#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */\r
+#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */\r
+#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */\r
+#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */\r
+#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */\r
+#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */\r
+#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */\r
+#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */\r
+#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */\r
+#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */\r
+#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_1) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_2) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_3) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_4) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_5) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_6) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_7) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_8) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_9) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_10) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_11) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_12) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_13) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_14) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_15))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_IOSwitch\r
+ * @{\r
+ */ \r
+ \r
+/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)\r
+#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)\r
+#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)\r
+#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)\r
+#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)\r
+#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)\r
+#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)\r
+#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)\r
+#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)\r
+#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)\r
+#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)\r
+#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)\r
+#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)\r
+#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)\r
+#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)\r
+#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)\r
+#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)\r
+#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)\r
+#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)\r
+#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)\r
+#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)\r
+#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)\r
+#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)\r
+#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)\r
+#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect \r
+ selected channel to COMP1 non inverting input */\r
+\r
+/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ \r
+#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)\r
+#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)\r
+#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)\r
+#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)\r
+#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)\r
+#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)\r
+#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)\r
+#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)\r
+#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)\r
+#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)\r
+#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)\r
+#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)\r
+\r
+#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH5) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH6) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH7) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH8) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH9) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH10) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH11) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH12) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH13) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH14) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH15) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH18) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH19) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH20) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH21) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH22) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH23) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH24) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH25) || \\r
+ ((IOSWITCH) == RI_IOSwitch_VCOMP) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Port\r
+ * @{\r
+ */\r
+\r
+#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */\r
+#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */\r
+#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */\r
+#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */\r
+#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */\r
+\r
+#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \\r
+ ((PORT) == RI_PortB) || \\r
+ ((PORT) == RI_PortC) || \\r
+ ((PORT) == RI_PortD) || \\r
+ ((PORT) == RI_PortE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Pin define \r
+ * @{\r
+ */\r
+#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RTC configuration to the default reset state *****/\r
+void SYSCFG_DeInit(void);\r
+void SYSCFG_RIDeInit(void);\r
+\r
+/* SYSCFG Initialization and Configuration functions **************************/ \r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
+void SYSCFG_USBPuCmd(FunctionalState NewState);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+\r
+/* RI Initialization and Configuration functions ******************************/ \r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select);\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+ FunctionalState NewState);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SYSCFG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_tim.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the TIM firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_TIM_H\r
+#define __STM32L1xx_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition\r
+ * @note This structure is used with all TIMx except for TIM6 and TIM7. \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+ \r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11))\r
+\r
+/* LIST1: TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11 */\r
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11))\r
+\r
+/* LIST3: TIM2, TIM3 and TIM4 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4))\r
+\r
+/* LIST2: TIM2, TIM3, TIM4 and TIM9 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) ||\\r
+ ((PERIPH) == TIM9))\r
+\r
+/* LIST5: TIM2, TIM3, TIM4, TIM6, TIM7 and TIM9 */\r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) ||\\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) ||\\r
+ ((PERIPH) == TIM9))\r
+\r
+/* LIST4: TIM2, TIM3, TIM4, TIM6 and TIM7 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) ||\\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7))\r
+\r
+/* LIST6: TIM9, TIM10 and TIM11 */\r
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) ||\\r
+ ((PERIPH) == TIM11))\r
+\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+ \r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_state\r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+ ((POLARITY) == TIM_ICPolarity_BothEdge))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_Trigger))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_DCR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000)) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OCReferenceClear \r
+ * @{\r
+ */\r
+#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)\r
+#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)\r
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \\r
+ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Remap \r
+ * @{\r
+ */\r
+\r
+#define TIM9_GPIO ((uint16_t)0x0000)\r
+#define TIM9_LSE ((uint16_t)0x0001)\r
+\r
+#define TIM10_GPIO ((uint16_t)0x0000)\r
+#define TIM10_LSI ((uint16_t)0x0001)\r
+#define TIM10_LSE ((uint16_t)0x0002)\r
+#define TIM10_RTC ((uint16_t)0x0003)\r
+\r
+#define TIM11_GPIO ((uint16_t)0x0000)\r
+#define TIM11_MSI ((uint16_t)0x0001)\r
+#define TIM11_HSE_RTC ((uint16_t)0x0002)\r
+\r
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM9_GPIO)||\\r
+ ((TIM_REMAP) == TIM9_LSE)||\\r
+ ((TIM_REMAP) == TIM10_GPIO)||\\r
+ ((TIM_REMAP) == TIM10_LSI)||\\r
+ ((TIM_REMAP) == TIM10_LSE)||\\r
+ ((TIM_REMAP) == TIM10_RTC)||\\r
+ ((TIM_REMAP) == TIM11_GPIO)||\\r
+ ((TIM_REMAP) == TIM11_MSI)||\\r
+ ((TIM_REMAP) == TIM11_HSE_RTC)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* TimeBase management ********************************************************/\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Output Compare management **************************************************/\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+\r
+/* Input Capture management ***************************************************/\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+\r
+/* Interrupts, DMA and flags management ***************************************/\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Clocks management **********************************************************/\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+\r
+\r
+/* Synchronization management *************************************************/\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+\r
+/* Specific interface management **********************************************/ \r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Specific remapping management **********************************************/\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_TIM_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_usart.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the USART \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_USART_H\r
+#define __STM32L1xx_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** \r
+ * @brief USART Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
+\r
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USART_Word_Length */\r
+\r
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint16_t USART_Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+ * @brief USART Clock Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+\r
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Clock */\r
+\r
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3))\r
+\r
+/** @defgroup USART_Word_Length \r
+ * @{\r
+ */ \r
+ \r
+#define USART_WordLength_8b ((uint16_t)0x0000)\r
+#define USART_WordLength_9b ((uint16_t)0x1000)\r
+ \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+ * @{\r
+ */ \r
+ \r
+#define USART_StopBits_1 ((uint16_t)0x0000)\r
+#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
+#define USART_StopBits_2 ((uint16_t)0x2000)\r
+#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_0_5) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Parity \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Parity_No ((uint16_t)0x0000)\r
+#define USART_Parity_Even ((uint16_t)0x0400)\r
+#define USART_Parity_Odd ((uint16_t)0x0600) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Mode \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Mode_Rx ((uint16_t)0x0004)\r
+#define USART_Mode_Tx ((uint16_t)0x0008)\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+ * @{\r
+ */ \r
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock \r
+ * @{\r
+ */ \r
+#define USART_Clock_Disable ((uint16_t)0x0000)\r
+#define USART_Clock_Enable ((uint16_t)0x0800)\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define USART_CPOL_Low ((uint16_t)0x0000)\r
+#define USART_CPOL_High ((uint16_t)0x0400)\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+ * @{\r
+ */\r
+\r
+#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
+#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit\r
+ * @{\r
+ */\r
+\r
+#define USART_LastBit_Disable ((uint16_t)0x0000)\r
+#define USART_LastBit_Enable ((uint16_t)0x0100)\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+ * @{\r
+ */\r
+ \r
+#define USART_IT_PE ((uint16_t)0x0028)\r
+#define USART_IT_TXE ((uint16_t)0x0727)\r
+#define USART_IT_TC ((uint16_t)0x0626)\r
+#define USART_IT_RXNE ((uint16_t)0x0525)\r
+#define USART_IT_IDLE ((uint16_t)0x0424)\r
+#define USART_IT_LBD ((uint16_t)0x0846)\r
+#define USART_IT_CTS ((uint16_t)0x096A)\r
+#define USART_IT_ERR ((uint16_t)0x0060)\r
+#define USART_IT_ORE ((uint16_t)0x0360)\r
+#define USART_IT_NE ((uint16_t)0x0260)\r
+#define USART_IT_FE ((uint16_t)0x0160)\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_DMA_Requests \r
+ * @{\r
+ */\r
+\r
+#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
+#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_WakeUp_methods\r
+ * @{\r
+ */\r
+\r
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+ * @{\r
+ */\r
+ \r
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Flags \r
+ * @{\r
+ */\r
+\r
+#define USART_FLAG_CTS ((uint16_t)0x0200)\r
+#define USART_FLAG_LBD ((uint16_t)0x0100)\r
+#define USART_FLAG_TXE ((uint16_t)0x0080)\r
+#define USART_FLAG_TC ((uint16_t)0x0040)\r
+#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
+#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
+#define USART_FLAG_ORE ((uint16_t)0x0008)\r
+#define USART_FLAG_NE ((uint16_t)0x0004)\r
+#define USART_FLAG_FE ((uint16_t)0x0002)\r
+#define USART_FLAG_PE ((uint16_t)0x0001)\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the USART configuration to the default reset state ***/ \r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+\r
+/* Multi-Processor Communication functions ************************************/\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* LIN mode functions *********************************************************/\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+\r
+/* Half-duplex mode function **************************************************/\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Smartcard mode functions ***************************************************/\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+\r
+/* IrDA mode functions ********************************************************/\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_USART_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the WWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_WWDG_H\r
+#define __STM32L1xx_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup WWDG_Prescaler \r
+ * @{\r
+ */ \r
+ \r
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the WWDG configuration to the default reset state ****/ \r
+void WWDG_DeInit(void);\r
+\r
+/* Prescaler, Refresh window and Counter configuration functions **************/\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+\r
+/* WWDG activation functions **************************************************/\r
+void WWDG_Enable(uint8_t Counter);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the miscellaneous firmware functions (add-on\r
+ * to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+/**\r
+ *\r
+@verbatim \r
+ *******************************************************************************\r
+ Interrupts configuration functions\r
+ ******************************************************************************* \r
+ \r
+ This section provide functions allowing to configure the NVIC interrupts (IRQ).\r
+ The Cortex-M3 exceptions are managed by CMSIS functions.\r
+ \r
+ 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() function\r
+ according to the following table.\r
+ \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ============================================================================================================================ \r
+\r
+\r
+ 2. Enable and Configure the priority of the selected IRQ Channels. \r
+\r
+@note When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,\r
+ the IRQ priority will be managed only by subpriority.\r
+ The sub-priority is only used to sort pending exception priorities, \r
+ and does not affect active exceptions.\r
+\r
+@note Lower priority values gives higher priority.\r
+\r
+@note Priority Order:\r
+ 1. Lowest Preemption priority\r
+ 2. Lowest Subpriority\r
+ 3. Lowest hardware priority (IRQn position)\r
+ \r
+@endverbatim\r
+*/\r
+\r
+/**\r
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested \r
+ * interrupt. This interrupts priority is managed only with subpriority. \r
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @retval None\r
+ */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+ * the configuration information for the specified NVIC peripheral.\r
+ * @retval None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+\r
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+ tmppriority = tmppriority << 0x04;\r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the vector table location and Offset.\r
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_VectTab_RAM\r
+ * @arg NVIC_VectTab_FLASH\r
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.\r
+ * @retval None\r
+ */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND\r
+ * @arg NVIC_LP_SLEEPDEEP\r
+ * @arg NVIC_LP_SLEEPONEXIT\r
+ * @param NewState: new state of LP condition. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ \r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral: \r
+ * - Initialization and Configuration\r
+ * - Power saving\r
+ * - Analog Watchdog configuration \r
+ * - Temperature Sensor & Vrefint (Voltage Reference internal) management \r
+ * - Regular Channels Configuration\r
+ * - Regular Channels DMA Configuration\r
+ * - Injected channels Configuration \r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * How to use this driver\r
+ * =================================================================== \r
+ * - Configure the ADC Prescaler, conversion resolution and data \r
+ * alignment using the ADC_Init() function.\r
+ * - Activate the ADC peripheral using ADC_Cmd() function. \r
+ *\r
+ * Regular channels group configuration\r
+ * ==================================== \r
+ * - To configure the ADC regular channels group features, use \r
+ * ADC_Init() and ADC_RegularChannelConfig() functions.\r
+ * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ * function.\r
+ * - To configurate and activate the Discontinuous mode, use the \r
+ * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. \r
+ * - To read the ADC converted values, use the ADC_GetConversionValue()\r
+ * function.\r
+ *\r
+ * DMA for Regular channels group features configuration\r
+ * ====================================================== \r
+ * - To enable the DMA mode for regular channels group, use the \r
+ * ADC_DMACmd() function.\r
+ * - To enable the generation of DMA requests continuously at the end\r
+ * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() \r
+ * function. \r
+ \r
+ * Injected channels group configuration\r
+ * ===================================== \r
+ * - To configure the ADC Injected channels group features, use \r
+ * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()\r
+ * functions.\r
+ * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ * function.\r
+ * - To activate the Injected Discontinuous mode, use the \r
+ * ADC_InjectedDiscModeCmd() function. \r
+ * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() \r
+ * function. \r
+ * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() \r
+ * function.\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_adc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC \r
+ * @brief ADC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r
+ \r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) \r
+ \r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)\r
+ \r
+/* CR1 register Mask */\r
+#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) \r
+ \r
+/* ADC DELAY mask */ \r
+#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)\r
+ \r
+/* ADC JEXTEN mask */\r
+#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)\r
+ \r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)\r
+ \r
+/* CR2 register Mask */\r
+#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)\r
+\r
+/* ADC SQx mask */\r
+#define SQR5_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR4_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR3_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR2_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR1_SQ_SET ((uint32_t)0x0000001F)\r
+\r
+/* ADC L Mask */\r
+#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) \r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_SET ((uint32_t)0x0000001F) \r
+ \r
+/* ADC JL mask */\r
+#define JSQR_JL_SET ((uint32_t)0x00300000) \r
+#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) \r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_SET ((uint32_t)0x00000007) \r
+#define SMPR2_SMP_SET ((uint32_t)0x00000007)\r
+#define SMPR3_SMP_SET ((uint32_t)0x00000007) \r
+\r
+/* ADC JDRx registers offset */\r
+#define JDR_OFFSET ((uint8_t)0x30) \r
+ \r
+/* ADC CCR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+ This section provides functions allowing to:\r
+ - Initialize and configure the ADC Prescaler\r
+ - ADC Conversion Resolution (12bit..6bit)\r
+ - Scan Conversion Mode (multichannels or one channel) for regular group\r
+ - ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group\r
+ - External trigger Edge and source of regular group, \r
+ - Converted data alignment (left or right)\r
+ - The number of ADC conversions that will be done using the sequencer for regular channel group\r
+ - Enable or disable the ADC peripheral\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes ADC1 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters\r
+ * in the ADC_InitStruct.\r
+ * @note This function is used to configure the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer). \r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains \r
+ * the configuration information for the specified ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint8_t tmpreg2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); \r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); \r
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));\r
+ \r
+ /*---------------------------- ADCx CR1 Configuration -----------------*/\r
+ /* Get the ADCx CR1 value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear RES and SCAN bits */ \r
+ tmpreg1 &= CR1_CLEAR_MASK;\r
+ /* Configure ADCx: scan conversion mode and resolution */\r
+ /* Set SCAN bit according to ADC_ScanConvMode value */\r
+ /* Set RES bit according to ADC_Resolution value */ \r
+ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);\r
+ /* Write to ADCx CR1 */\r
+ ADCx->CR1 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx CR2 Configuration -----------------*/\r
+ /* Get the ADCx CR2 value */\r
+ tmpreg1 = ADCx->CR2;\r
+ /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */\r
+ tmpreg1 &= CR2_CLEAR_MASK;\r
+ /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ \r
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | \r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
+ /* Write to ADCx CR2 */\r
+ ADCx->CR2 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
+ /* Get the ADCx SQR1 value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Clear L bits */\r
+ tmpreg1 &= SQR1_L_RESET;\r
+ /* Configure ADCx: regular channel sequence length */\r
+ /* Set L bits according to ADC_NbrOfConversion value */ \r
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);\r
+ tmpreg1 |= ((uint32_t)tmpreg2 << 20);\r
+ /* Write to ADCx SQR1 */\r
+ ADCx->SQR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_InitStruct member with its default value.\r
+ * @note This function is used to initialize the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer). \r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Resolution member */\r
+ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r
+\r
+ /* Initialize the ADC_ScanConvMode member */\r
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ExternalTrigConvEdge member */\r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
+\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;\r
+\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+\r
+ /* Initialize the ADC_NbrOfConversion member */\r
+ ADC_InitStruct->ADC_NbrOfConversion = 1;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCs peripherals according to the specified parameters\r
+ * in the ADC_CommonInitStruct.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure \r
+ * that contains the configuration information (Prescaler) for ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));\r
+\r
+ /*---------------------------- ADC CCR Configuration -----------------*/\r
+ /* Get the ADC CCR value */\r
+ tmpreg = ADC->CCR;\r
+\r
+ /* Clear ADCPRE bit */ \r
+ tmpreg &= CR_CLEAR_MASK;\r
+ \r
+ /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ \r
+ tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); \r
+ \r
+ /* Write to ADC CCR */\r
+ ADC->CCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_CommonInitStruct member with its default value.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Prescaler member */\r
+ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC peripheral.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADON bit to wake up the ADC from power down mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC peripheral */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group2 Power saving functions\r
+ * @brief Power saving functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Power saving functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to reduce power consumption.\r
+ The two function must be combined to get the maximal benefits:\r
+ When the ADC frequency is higher than the CPU one, it is recommended to \r
+ 1. Insert a freeze delay : \r
+ ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze);\r
+ 2. Enable the power down in Idle and Delay phases :\r
+ ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase.\r
+ * @note ADC power-on and power-off can be managed by hardware to cut the \r
+ * consumption when the ADC is not converting. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_PowerDown: The ADC power down configuration. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase \r
+ * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase \r
+ * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases\r
+ * @note The ADC can be powered down: \r
+ * - During the hardware delay insertion (using the ADC_PowerDown_Delay\r
+ * parameter) \r
+ * => The ADC is powered up again at the end of the delay. \r
+ * - During the ADC is waiting for a trigger event ( using the \r
+ * ADC_PowerDown_Idle parameter) \r
+ * => The ADC is powered up at the next trigger event.\r
+ * - During the hardware delay insertion or the ADC is waiting for a \r
+ * trigger event (using the ADC_PowerDown_Idle_Delay parameter) \r
+ * => The ADC is powered up only at the end of the delay and at the \r
+ * next trigger event. \r
+ * @param NewState: new state of the ADCx power down. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 |= ADC_PowerDown;\r
+ }\r
+ else\r
+ {\r
+ /* Disable The ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 &= (uint32_t)~ADC_PowerDown;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Defines the length of the delay which is applied after a conversion \r
+ * or a sequence of conversion.\r
+ * @note When the CPU clock is not fast enough to manage the data rate, a \r
+ * Hardware delay can be introduced between ADC conversions to reduce \r
+ * this data rate. \r
+ * @note The Hardware delay is inserted after :\r
+ * - each regular conversion\r
+ * - after each sequence of injected conversions\r
+ * @note No Hardware delay is inserted between conversions of different groups.\r
+ * @note When the hardware delay is not enough, the Freeze Delay Mode can be \r
+ * selected and a new conversion can start only if all the previous data \r
+ * of the same group have been treated:\r
+ * - for a regular conversion: once the ADC conversion data register has \r
+ * been read (using ADC_GetConversionValue() function) or if the EOC \r
+ * Flag has been cleared (using ADC_ClearFlag() function).\r
+ * - for an injected conversion: when the JEOC bit has been cleared \r
+ * (using ADC_ClearFlag() function).\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_DelayLength: The length of delay which is applied after a \r
+ * conversion or a sequence of conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_DelayLength_None: No delay \r
+ * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.\r
+ * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles\r
+ * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles \r
+ * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles \r
+ * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles \r
+ * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles \r
+ * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles \r
+ * @retval None\r
+ */\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));\r
+\r
+ /* Get the old register value */ \r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old delay length */\r
+ tmpreg &= CR2_DELS_RESET;\r
+ /* Set the delay length */\r
+ tmpreg |= ADC_DelayLength;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group3 Analog Watchdog configuration functions\r
+ * @brief Analog Watchdog configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Analog Watchdog configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the Analog Watchdog\r
+ (AWD) feature in the ADC.\r
+ \r
+ A typical configuration Analog Watchdog is done following these steps :\r
+ 1. the ADC guarded channel(s) is (are) selected using the \r
+ ADC_AnalogWatchdogSingleChannelConfig() function.\r
+ 2. The Analog watchdog lower and higher threshold are configured using the \r
+ ADC_AnalogWatchdogThresholdsConfig() function.\r
+ 3. The Analog watchdog is enabled and configured to enable the check, on one\r
+ or more channels, using the ADC_AnalogWatchdogCmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the analog watchdog on single/all regular\r
+ * or injected channels\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single \r
+ * regular channel\r
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single \r
+ * injected channel\r
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a \r
+ * single regular or injected channel \r
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular \r
+ * channel\r
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected \r
+ * channel\r
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all \r
+ * regular and injected channels\r
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
+ * @retval None \r
+ */\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */ \r
+ tmpreg &= CR1_AWDMODE_RESET;\r
+ /* Set the analog watchdog enable mode */\r
+ tmpreg |= ADC_AnalogWatchdog;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the high and low thresholds of the analog watchdog. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param HighThreshold: the ADC analog watchdog High threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
+ uint16_t LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
+\r
+ /* Set the ADCx high threshold */\r
+ ADCx->HTR = HighThreshold;\r
+ /* Set the ADCx low threshold */\r
+ ADCx->LTR = LowThreshold;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog guarded single channel\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected\r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= CR1_AWDCH_RESET;\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_Channel;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
+ * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
+ =============================================================================== \r
+\r
+ This section provides a function allowing to enable/ disable the internal \r
+ connections between the ADC and the Temperature Sensor and the Vrefint source.\r
+ \r
+ A typical configuration to get the Temperature sensor and Vrefint channels \r
+ voltages or is done following these steps :\r
+ 1. Enable the internal connection of Temperature sensor and Vrefint sources \r
+ with the ADC channels using ADC_TempSensorVrefintCmd() function. \r
+ 2. select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using \r
+ ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions \r
+ 3. Get the voltage values, using ADC_GetConversionValue() or \r
+ ADC_GetInjectedConversionValue().\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the temperature sensor and Vrefint channel.\r
+ * @param NewState: new state of the temperature sensor and Vref int channels.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group5 Regular Channels Configuration functions\r
+ * @brief Regular Channels Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Regular Channels Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to manage the ADC regular channels,\r
+ it is composed of 2 sub sections : \r
+ \r
+ 1. Configuration and management functions for regular channels: This subsection \r
+ provides functions allowing to configure the ADC regular channels : \r
+ - Configure the rank in the regular group sequencer for each channel\r
+ - Configure the sampling time for each channel\r
+ - select the conversion Trigger for regular channels\r
+ - select the desired EOC event behavior configuration\r
+ - Activate the continuous Mode (*)\r
+ - Activate the Discontinuous Mode \r
+ Please Note that the following features for regular channels are configurated\r
+ using the ADC_Init() function : \r
+ - scan mode activation \r
+ - continuous mode activation (**) \r
+ - External trigger source \r
+ - External trigger edge \r
+ - number of conversion in the regular channels group sequencer.\r
+ \r
+ @note : (*) and (**) are performing the same configuration\r
+ \r
+ 2. Get the conversion data: This subsection provides an important function in \r
+ the ADC peripheral since it returns the converted data of the current \r
+ regular channel. When the Conversion value is read, the EOC Flag is \r
+ automatically cleared.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sampling time.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @param Rank: The rank in the regular group sequencer. This parameter\r
+ * must be between 1 to 26.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+\r
+ /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
+ if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ \r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ /* For Rank 1 to 6 */\r
+ if (Rank < 7)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR5;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR5 = tmpreg1;\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (Rank < 13)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR4;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR4 = tmpreg1;\r
+ } \r
+ /* For Rank 13 to 18 */\r
+ else if (Rank < 19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR3 = tmpreg1;\r
+ }\r
+ \r
+ /* For Rank 19 to 24 */\r
+ else if (Rank < 25)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR2 = tmpreg1;\r
+ } \r
+ \r
+ /* For Rank 25 to 27 */\r
+ else\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR1 = tmpreg1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the regular channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Enable the selected ADC conversion for regular group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start regular conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of SWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* SWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the EOC on each regular channel conversion\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 |= ADC_CR2_EOCS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC continuous conversion mode \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC continuous conversion mode\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the discontinuous mode for the selected ADC regular\r
+ * group channel.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Number: specifies the discontinuous mode regular channel count value. \r
+ * This number must be between 1 and 8.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
+\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= CR1_DISCNUM_RESET;\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg2 = Number - 1;\r
+ tmpreg1 |= tmpreg2 << 13;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode on regular group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode on regular \r
+ * group channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADCx conversion result data for regular channel. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Return the selected ADC conversion value */\r
+ return (uint16_t) ADCx->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions\r
+ * @brief Regular Channels DMA Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Regular Channels DMA Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the DMA for ADC regular \r
+ channels.\r
+ Since converted regular channel values are stored into a unique data register, \r
+ it is useful to use DMA for conversion of more than one regular channel. This \r
+ avoids the loss of the data already stored in the ADC Data register. \r
+ \r
+ When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r
+ conversion of a regular channel, a DMA request is generated.\r
+ \r
+ Depending on the "DMA disable selection" configuration (using the \r
+ ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA \r
+ transfer, two possibilities are allowed:\r
+ - No new DMA request is issued to the DMA controller (feature DISABLED) \r
+ - Requests can continue to be generated (feature ENABLED).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC DMA request.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 |= ADC_CR2_DDS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group7 Injected channels Configuration functions\r
+ * @brief Injected channels Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Injected channels Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the ADC Injected channels,\r
+ it is composed of 2 sub sections : \r
+ \r
+ 1. Configuration functions for Injected channels: This subsection provides \r
+ functions allowing to configure the ADC injected channels : \r
+ - Configure the rank in the injected group sequencer for each channel\r
+ - Configure the sampling time for each channel \r
+ - Activate the Auto injected Mode \r
+ - Activate the Discontinuous Mode \r
+ - scan mode activation \r
+ - External/software trigger source \r
+ - External trigger edge \r
+ - injected channels sequencer.\r
+ \r
+ 2. Get the Specified Injected channel conversion data: This subsection \r
+ provides an important function in the ADC peripheral since it returns the \r
+ converted data of the specific injected channel.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @param Rank: The rank in the injected group sequencer. This parameter\r
+ * must be between 1 to 4.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_INJECTED_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ \r
+ /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
+ if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ \r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ \r
+ /* Rank configuration */\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Get JL value: Number = JL+1 */\r
+ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;\r
+ /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Clear the old JSQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Set the JSQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the sequencer length for injected channels\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Length: The sequencer length. \r
+ * This parameter must be a number between 1 to 4.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Clear the old injected sequence length JL bits */\r
+ tmpreg1 &= JSQR_JL_RESET;\r
+ /* Set the injected sequence length JL bits */\r
+ tmpreg2 = Length - 1; \r
+ tmpreg1 |= tmpreg2 << 20;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Set the injected channels conversion value offset\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @param Offset: the offset value for the selected ADC injected channel\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+ assert_param(IS_ADC_OFFSET(Offset)); \r
+ \r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel;\r
+ \r
+ /* Set the selected injected channel data offset */\r
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected \r
+ * conversion. This parameter can be one of the following values: \r
+ * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected \r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external event selection for injected group */\r
+ tmpreg &= CR2_JEXTSEL_RESET;\r
+ /* Set the external event selection for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConv;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger edge for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger\r
+ * edge to start injected conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for \r
+ * injected conversion\r
+ * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge\r
+ * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge\r
+ * @arg ADC_External ADC_ExternalTrigConvEdge_RisingFalling: detection on \r
+ * both rising and falling edge\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external trigger edge for injected group */\r
+ tmpreg &= CR2_JEXTEN_RESET;\r
+ /* Set the new external trigger edge for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConvEdge;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the injected \r
+ * channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Enable the selected ADC conversion for injected group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start injected conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start injected conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of JSWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* JSWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* JSWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the JSWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC automatic injected group\r
+ * conversion after regular one.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC auto injected\r
+ * conversion. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode for injected group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on injected group channel. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the ADC injected channel conversion result\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the converted ADC injected channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+\r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel + JDR_OFFSET;\r
+ \r
+ /* Returns the selected injected channel conversion data value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group8 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the ADC Interrupts and get \r
+ the status and clear flags and Interrupts pending bits.\r
+ \r
+ The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 3 groups:\r
+ \r
+ I. Flags and Interrupts for ADC regular channels\r
+ =================================================\r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost\r
+\r
+ 2. ADC_FLAG_EOC : Regular channel end of conversion + to indicate (depending \r
+ on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of :\r
+ ==> a regular CHANNEL conversion \r
+ ==> sequence of regular GROUP conversions .\r
+\r
+ 3. ADC_FLAG_STRT: Regular channel start + to indicate when regular CHANNEL \r
+ conversion starts.\r
+ \r
+ 4. ADC_FLAG_RCNR: Regular channel not ready+ to indicate if a new regular \r
+ conversion can be launched\r
+ \r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_OVR \r
+ 2. ADC_IT_EOC \r
+ \r
+ \r
+ II. Flags and Interrupts for ADC Injected channels\r
+ =================================================\r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at \r
+ the end of injected GROUP conversion \r
+ \r
+ 2. ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when \r
+ injected GROUP conversion starts.\r
+\r
+ 3. ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new \r
+ injected conversion can be launched.\r
+\r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_JEOC \r
+\r
+ III. General Flags and Interrupts for the ADC\r
+ ================================================= \r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage \r
+ crosses the programmed thresholds values.\r
+ \r
+ 2. ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready to convert.\r
+ \r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_AWD \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC interrupts.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: overrun interrupt \r
+ * @param NewState: new state of the specified ADC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) \r
+{\r
+ uint32_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)ADC_IT;\r
+ itmask = (uint32_t)0x01 << itmask; \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->CR1 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->CR1 &= (~(uint32_t)itmask);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC flag is set or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: Overrun flag \r
+ * @arg ADC_FLAG_ADONS: ADC ON status \r
+ * @arg ADC_FLAG_RCNR: Regular channel not ready \r
+ * @arg ADC_FLAG_JCNR: Injected channel not ready \r
+ * @retval The new state of ADC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
+\r
+ /* Check the status of the specified ADC flag */\r
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's pending flags.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: overrun flag \r
+ * @retval None\r
+ */\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+\r
+ /* Clear the selected ADC flags */\r
+ ADCx->SR = ~(uint32_t)ADC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC interrupt has occurred or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: Overrun interrupt \r
+ * @retval The new state of ADC_IT (SET or RESET).\r
+ */\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint32_t)((uint32_t)ADC_IT >> 8);\r
+\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); \r
+\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ { \r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx\92s interrupt pending bits.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: Overrun interrupt \r
+ * @retval None\r
+ */\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ uint8_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)(ADC_IT >> 8);\r
+\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->SR = ~(uint32_t)itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_comp.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the comparators (COMP1 and COMP2) peripheral: \r
+ * - Comparators configuration\r
+ * - Window mode control\r
+ * - Internal Reference Voltage (VREFINT) output\r
+ *\r
+ * @verbatim\r
+ *\r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * \r
+ * The device integrates two analog comparators COMP1 and COMP2: \r
+ * - COMP1 is a fixed threshold (VREFINT) that shares the non inverting\r
+ * input with the ADC channels.\r
+ *\r
+ * - COMP2 is a rail-to-rail comparator whose the inverting input \r
+ * can be selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT,\r
+ * 1/2 VERFINT, 3/4 VREFINT, VREFINT, PB3 and whose the output\r
+ * can be redirected to embedded timers: TIM2, TIM3, TIM4, TIM10\r
+ *\r
+ * - The two comparators COMP1 and COMP2 can be combined in window\r
+ * mode.\r
+ *\r
+ * @note\r
+ * 1- Comparator APB clock must be enabled to get write access\r
+ * to comparator register using\r
+ * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE);\r
+ *\r
+ * 2- COMP1 comparator and ADC can't be used at the same time since\r
+ * they share the same ADC switch matrix (analog switches).\r
+ *\r
+ * 3- When an I/O is used as comparator input, the corresponding GPIO \r
+ * registers should be configured in analog mode.\r
+ *\r
+ * 4- Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on\r
+ * GPIO pin. They are only internal.\r
+ * To get the comparator output level, use COMP_GetOutputLevel()\r
+ *\r
+ * 5- COMP1 and COMP2 outputs are internally connected to EXTI Line 21\r
+ * and EXTI Line 22 respectively.\r
+ * Interrupts can be used by configuring the EXTI Line using the \r
+ * EXTI peripheral driver.\r
+ *\r
+ * 6- After enabling the comparator (COMP1 or COMP2), user should wait\r
+ * for start-up time (tSTART) to get right output levels.\r
+ * Please refer to product datasheet for more information on tSTART. \r
+ *\r
+ * 7- Comparators cannot be used to exit the device from Sleep or Stop \r
+ * mode when the internal reference voltage is switched off using \r
+ * the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).\r
+ *\r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_comp.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP \r
+ * @brief COMP driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup COMP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes COMP peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void COMP_DeInit(void)\r
+{\r
+ COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the COMP2 peripheral according to the specified parameters\r
+ * in the COMP_InitStruct:\r
+ * - COMP_InvertingInput specify the inverting input of COMP2\r
+ * - COMP_OutputSelect connect the output of COMP2 to selected timer\r
+ * input (Input capture / Output Compare Reference Clear)\r
+ * - COMP_Speed configures COMP2 speed for optimum speed/consumption ratio\r
+ * @note This function configures only COMP2.\r
+ * @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are \r
+ * different from "000".\r
+ * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains \r
+ * the configuration information for the specified COMP peripheral.\r
+ * @retval None\r
+ */\r
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));\r
+ assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));\r
+ assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));\r
+\r
+ /*!< Get the COMP CSR value */\r
+ tmpreg = COMP->CSR;\r
+\r
+ /*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */ \r
+ tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));\r
+ \r
+ /*!< Configure COMP: speed, inversion input selection and output redirection */\r
+ /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */\r
+ /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ \r
+ /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */ \r
+ tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput \r
+ | COMP_InitStruct->COMP_OutputSelect));\r
+\r
+ /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are \r
+ different from "000" */\r
+ /*!< Write to COMP_CSR register */\r
+ COMP->CSR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the COMP1 peripheral.\r
+ * After enabling COMP1, the following functions should be called to \r
+ * connect the selected GPIO input to COMP1 non inverting input:\r
+ * - Enable switch control mode using SYSCFG_RISwitchControlModeCmd()\r
+ * - Close VCOMP switch using SYSCFG_RIIOSwitchConfig()\r
+ * - Close the I/O switch number n corresponding to the I/O \r
+ * using SYSCFG_RIIOSwitchConfig()\r
+ * @param NewState: new state of the COMP1 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note This function enables/disables only the COMP1.\r
+ * @retval None\r
+ */\r
+void COMP_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the COMP1 */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the COMP1 */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the output level (high or low) of the selected comparator:\r
+ * - Comparator output is low when the non-inverting input is at a lower\r
+ * voltage than the inverting input\r
+ * - Comparator output is high when the non-inverting input is at a higher\r
+ * voltage than the inverting input\r
+ * @note Comparators outputs aren't available on GPIO (outputs levels are \r
+ * only internal). The COMP1 and COMP2 outputs are connected internally \r
+ * to the EXTI Line 21 and Line 22 respectively. \r
+ * @param COMP_Selection: the selected comparator. \r
+ * This parameter can be one of the following values:\r
+ * @arg COMP_Selection_COMP1: COMP1 selected\r
+ * @arg COMP_Selection_COMP2: COMP2 selected \r
+ * @retval Returns the selected comparator output level.\r
+ */\r
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)\r
+{\r
+ uint8_t compout = 0x0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
+\r
+ /* Check if Comparator 1 is selected */\r
+ if(COMP_Selection == COMP_Selection_COMP1)\r
+ {\r
+ /* Check if comparator 1 output level is high */\r
+ if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)\r
+ {\r
+ /* Get Comparator 1 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_High;\r
+ }\r
+ /* comparator 1 output level is low */\r
+ else\r
+ {\r
+ /* Get Comparator 1 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_Low;\r
+ }\r
+ }\r
+ /* Comparator 2 is selected */\r
+ else\r
+ {\r
+ /* Check if comparator 2 output level is high */\r
+ if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)\r
+ {\r
+ /* Get Comparator output level */\r
+ compout = (uint8_t) COMP_OutputLevel_High;\r
+ }\r
+ /* comparator 2 output level is low */\r
+ else\r
+ {\r
+ /* Get Comparator 2 output level */\r
+ compout = (uint8_t) COMP_OutputLevel_Low;\r
+ }\r
+ }\r
+ /* Return the comparator output level */\r
+ return (uint8_t)(compout);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group2 Window mode control function\r
+ * @brief Window mode control function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Window mode control function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the window mode.\r
+ * In window mode:\r
+ * - COMP1 inverting input is fixed to VREFINT defining the first\r
+ * threshold\r
+ * - COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT\r
+ * sub-multiples, PB3) defining the second threshold\r
+ * - COMP1 and COMP2 non inverting inputs are connected together.\r
+ * @note In window mode, only the Group 6 (PB4 or PB5) can be used as\r
+ * non-inverting inputs.\r
+ * param NewState: new state of the window mode. \r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void COMP_WindowCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the window mode */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the window mode */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group3 Internal Reference Voltage output function\r
+ * @brief Internal Reference Voltage (VREFINT) output function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Internal Reference Voltage (VREFINT) output function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the output of internal reference voltage (VREFINT).\r
+ * The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or\r
+ * CH9 (PB1).\r
+ * To correctly use this function, the SYSCFG_RIIOSwitchConfig() function\r
+ * should be called after.\r
+ * @param NewState: new state of the Vrefint output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void COMP_VrefintOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the output of internal reference voltage */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the output of internal reference voltage */\r
+ COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_crc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the CRC firmware functions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_crc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC \r
+ * @brief CRC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the CRC Data register (DR).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CRC_ResetDR(void)\r
+{\r
+ /* Reset CRC generator */\r
+ CRC->CR = CRC_CR_RESET;\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
+ * @param Data: data word(32-bit) to compute its CRC\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcCRC(uint32_t Data)\r
+{\r
+ CRC->DR = Data;\r
+ \r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
+ * @param pBuffer: pointer to the buffer containing the data to be computed\r
+ * @param BufferLength: length of the buffer to be computed \r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0;\r
+ \r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ CRC->DR = pBuffer[index];\r
+ }\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current CRC value.\r
+ * @param None\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_GetCRC(void)\r
+{\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
+ * @param IDValue: 8-bit value to be stored in the ID register \r
+ * @retval None\r
+ */\r
+void CRC_SetIDRegister(uint8_t IDValue)\r
+{\r
+ CRC->IDR = IDValue;\r
+}\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
+ * @param None\r
+ * @retval 8-bit value of the ID register \r
+ */\r
+uint8_t CRC_GetIDRegister(void)\r
+{\r
+ return (CRC->IDR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dac.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Digital-to-Analog Converter (DAC) peripheral: \r
+ * - DAC channels configuration: trigger, output buffer, data format\r
+ * - DMA management \r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * DAC Peripheral features\r
+ * ===================================================================\r
+ * The device integrates two 12-bit Digital Analog Converters that can \r
+ * be used independently or simultaneously (dual mode):\r
+ * 1- DAC channel1 with DAC_OUT1 (PA4) as output\r
+ * 1- DAC channel2 with DAC_OUT2 (PA5) as output\r
+ *\r
+ * Digital to Analog conversion can be non-triggered using DAC_Trigger_None\r
+ * and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using \r
+ * DAC_SetChannel1Data()/DAC_SetChannel2Data.\r
+ * \r
+ * Digital to Analog conversion can be triggered by:\r
+ * 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.\r
+ * The used pin (GPIOx_Pin9) must be configured in input mode.\r
+ *\r
+ * 2- Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 \r
+ * (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)\r
+ * The timer TRGO event should be selected using TIM_SelectOutputTrigger()\r
+ *\r
+ * 3- Software using DAC_Trigger_Software\r
+ *\r
+ * Each DAC channel integrates an output buffer that can be used to \r
+ * reduce the output impedance, and to drive external loads directly\r
+ * without having to add an external operational amplifier.\r
+ * To enable, the output buffer use \r
+ * DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+ * \r
+ * Refer to the device datasheet for more details about output impedance\r
+ * value with and without output buffer.\r
+ *\r
+ * Both DAC channels can be used to generate\r
+ * 1- Noise wave using DAC_WaveGeneration_Noise\r
+ * 2- Triangle wave using DAC_WaveGeneration_Triangle\r
+ * \r
+ * Wave generation can be disabled using DAC_WaveGeneration_None\r
+ *\r
+ * The DAC data format can be:\r
+ * 1- 8-bit right alignment using DAC_Align_8b_R\r
+ * 2- 12-bit left alignment using DAC_Align_12b_L\r
+ * 3- 12-bit right alignment using DAC_Align_12b_R\r
+ *\r
+ * The analog output voltage on each DAC channel pin is determined\r
+ * by the following equation: DAC_OUTx = VREF+ * DOR / 4095\r
+ * with DOR is the Data Output Register\r
+ * VEF+ is the input voltage reference (refer to the device datasheet)\r
+ * e.g. To set DAC_OUT1 to 0.7V, use\r
+ * DAC_SetChannel1Data(DAC_Align_12b_R, 868);\r
+ * Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V\r
+ *\r
+ * A DMA1 request can be generated when an external trigger (but not\r
+ * a software trigger) occurs if DMA1 requests are enabled using\r
+ * DAC_DMACmd()\r
+ * DMA1 requests are mapped as following:\r
+ * 1- DAC channel1 is mapped on DMA1 channel3 which must be already \r
+ * configured\r
+ * 2- DAC channel2 is mapped on DMA1 channel4 which must be already \r
+ * configured\r
+ *\r
+ * =================================================================== \r
+ * How to use this driver \r
+ * =================================================================== \r
+ * - DAC APB clock must be enabled to get write access to DAC\r
+ * registers using\r
+ * RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)\r
+ * - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r
+ * - Configure the DAC channel using DAC_Init()\r
+ * - Enable the DAC channel using DAC_Cmd()\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dac.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* CR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
+\r
+/* DAC Dual Channels SWTRIG masks */\r
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
+\r
+/* DOR register offset */\r
+#define DOR_OFFSET ((uint32_t)0x0000002C)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Group1 DAC channels configuration\r
+ * @brief DAC channels configuration: trigger, output buffer, data format \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DAC channels configuration: trigger, output buffer, data format\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified DAC channel.\r
+ * DAC_Trigger selects the trigger source: EXTI Line 9, TIM2, TIM4....\r
+ * DAC_WaveGeneration selects the waveform to be generated: noise, triangle\r
+ * DAC_LFSRUnmask_TriangleAmplitude \r
+ * defines the LFSR when noise waveform is selected by DAC_WaveGeneration\r
+ * or defines the amplitude of the triangle waveform when it is \r
+ * selected by DAC_WaveGeneration\r
+ * DAC_OutputBuffer enables/disables the output buffer on DAC_OUTx\r
+ * @retval None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+\r
+/*---------------------------- DAC CR Configuration --------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,\r
+ mask/amplitude for wave generation */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set WAVEx bits according to DAC_WaveGeneration value */\r
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_WaveGeneration member */\r
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the DAC channel is enabled the trigger source can no more\r
+ * be modified.\r
+ * @retval None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables simultaneously the two DAC channels software\r
+ * triggers.\r
+ * @param NewState: new state of the DAC channels software triggers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for both DAC channels */\r
+ DAC->SWTRIGR |= DUAL_SWTRIG_SET;\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for both DAC channels */\r
+ DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_Wave: Specifies the wave type to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Wave_Noise: noise wave generation\r
+ * @arg DAC_Wave_Triangle: triangle wave generation\r
+ * @param NewState: new state of the selected DAC channel wave generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note \r
+ * @retval None\r
+ */\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_WAVE(DAC_Wave)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ DAC->CR |= DAC_Wave << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected wave generation for the selected DAC channel */\r
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE; \r
+ tmp += DHR12R1_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel2.\r
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12R2_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel2 selected data holding register */\r
+ *(__IO uint32_t *)tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual channel DAC.\r
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
+ * holding register.\r
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
+ * holding register.\r
+ * @note In dual mode, a unique register access is required to write in both\r
+ * DAC channels at the same time.\r
+ * @retval None\r
+ */\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
+{\r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (DAC_Align == DAC_Align_8b_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12RD_OFFSET + DAC_Align;\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ \r
+ tmp = (uint32_t) DAC_BASE ;\r
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group2 DMA management functions\r
+ * @brief DMA management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * When enabled DMA1 is generated when an external trigger (EXTI Line9,\r
+ * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs\r
+ * @param DAC_Channel: the selected DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which \r
+ * must be already configured. \r
+ * @retval None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC interrupts.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @param NewState: new state of the specified DAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */ \r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC interrupts */\r
+ DAC->CR |= (DAC_IT << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC interrupts */\r
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC flag is set or not.\r
+ * @param DAC_Channel: thee selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to check. \r
+ * This parameter can be only of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Check the status of the specified DAC flag */\r
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
+ {\r
+ /* DAC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel's pending flags.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to clear. \r
+ * This parameter can be of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval None\r
+ */\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Clear the selected DAC flags */\r
+ DAC->SR = (DAC_FLAG << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC interrupt has occurred or not.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt source to check. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_IT (SET or RESET).\r
+ */\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT));\r
+\r
+ /* Get the DAC_IT enable bit status */\r
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
+ \r
+ /* Check the status of the specified DAC interrupt */\r
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* DAC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel\92s interrupt pending bits.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval None\r
+ */\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ /* Clear the selected DAC interrupt pending bits */\r
+ DAC->SR = (DAC_IT << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dbgmcu.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the DBGMCU firmware functions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dbgmcu.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU \r
+ * @brief DBGMCU driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @param None\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t DBGMCU_GetREVID(void)\r
+{\r
+ return(DBGMCU->IDCODE >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @param None\r
+ * @retval Device identifier\r
+ */\r
+uint32_t DBGMCU_GetDEVID(void)\r
+{\r
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Configures low power mode behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the low power mode.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
+ * @param NewState: new state of the specified low power mode in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->CR |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->CR &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB1 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted\r
+ * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted \r
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted\r
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted\r
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is \r
+ * halted\r
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is \r
+ * halted \r
+ * @param NewState: new state of the specified APB1 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB1FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB1FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB2 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted \r
+ * @param NewState: new state of the specified APB2 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB2FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB2FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_dma.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Direct Memory Access controller (DMA): \r
+ * - Initialization and Configuration\r
+ * - Data Counter\r
+ * - Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable The DMA controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE)\r
+ * function for DMA1 or using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE)\r
+ * function for DMA2.\r
+ *\r
+ * 2. Enable and configure the peripheral to be connected to the DMA channel\r
+ * (except for internal SRAM / FLASH memories: no initialization is \r
+ * necessary). \r
+ * \r
+ * 3. For a given Channel, program the Source and Destination addresses, \r
+ * the transfer Direction, the Buffer Size, the Peripheral and Memory\r
+ * Incrementation mode and Data Size, the Circular or Normal mode, \r
+ * the channel transfer Priority and the Memory-to-Memory transfer \r
+ * mode (if needed) using the DMA_Init() function.\r
+ *\r
+ * 4. Enable the NVIC and the corresponding interrupt(s) using the function \r
+ * DMA_ITConfig() if you need to use DMA interrupts. \r
+ *\r
+ * 5. Enable the DMA channel using the DMA_Cmd() function. \r
+ * \r
+ * 6. Activate the needed channel Request using PPP_DMACmd() function for\r
+ * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)\r
+ * The function allowing this operation is provided in each PPP peripheral\r
+ * driver (ie. SPI_DMACmd for SPI peripheral). \r
+ *\r
+ * 7. Optionally, you can configure the number of data to be transferred\r
+ * when the channel is disabled (ie. after each Transfer Complete event\r
+ * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r
+ * And you can get the number of remaining data to be transferred using \r
+ * the function DMA_GetCurrDataCounter() at run time (when the DMA channel is\r
+ * enabled and running). \r
+ * \r
+ * 8. To control DMA events you can use one of the following \r
+ * two methods:\r
+ * a- Check on DMA channel flags using the function DMA_GetFlagStatus(). \r
+ * b- Use DMA interrupts through the function DMA_ITConfig() at initialization\r
+ * phase and DMA_GetITStatus() function into interrupt routines in\r
+ * communication phase. \r
+ * After checking on a flag you should clear it using DMA_ClearFlag()\r
+ * function. And after checking on an interrupt event you should \r
+ * clear it using DMA_ClearITPendingBit() function. \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_dma.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA \r
+ * @brief DMA driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* DMA1 Channelx interrupt pending bit masks */\r
+#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
+#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
+\r
+/* DMA FLAG mask */\r
+#define FLAG_MASK ((uint32_t)0x10000000)\r
+\r
+/* DMA registers Masks */\r
+#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This subsection provides functions allowing to initialize the DMA channel source\r
+ and destination addresses, incrementation and data sizes, transfer direction, \r
+ buffer size, circular/normal mode selection, memory-to-memory mode selection \r
+ and channel priority value.\r
+ \r
+ The DMA_Init() function follows the DMA configuration procedures as described in\r
+ reference manual (RM0038).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the DMAy Channelx registers to their default reset\r
+ * values.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+\r
+ /* Reset DMAy Channelx control register */\r
+ DMAy_Channelx->CCR = 0;\r
+ \r
+ /* Reset DMAy Channelx remaining bytes register */\r
+ DMAy_Channelx->CNDTR = 0;\r
+ \r
+ /* Reset DMAy Channelx peripheral address register */\r
+ DMAy_Channelx->CPAR = 0;\r
+ \r
+ /* Reset DMAy Channelx memory address register */\r
+ DMAy_Channelx->CMAR = 0;\r
+ \r
+ if (DMAy_Channelx == DMA1_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel1 */\r
+ DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel2 */\r
+ DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel3 */\r
+ DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel4 */\r
+ DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel5 */\r
+ DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel6)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel6 */\r
+ DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;\r
+ }\r
+ else\r
+ {\r
+ if (DMAy_Channelx == DMA1_Channel7)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel7 */\r
+ DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMAy Channelx according to the specified\r
+ * parameters in the DMA_InitStruct.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+ * contains the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
+ /* Get the DMAy_Channelx CCR value */\r
+ tmpreg = DMAy_Channelx->CCR;\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
+ tmpreg &= CCR_CLEAR_MASK;\r
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRC bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+\r
+ /* Write to DMAy Channelx CCR */\r
+ DMAy_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CPAR */\r
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CMAR */\r
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DMA_InitStruct member with its default value.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param NewState: new state of the DMAy Channelx. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group2 Data Counter functions\r
+ * @brief Data Counter functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data Counter functions\r
+ =============================================================================== \r
+\r
+ This subsection provides function allowing to configure and read the buffer size\r
+ (number of data to be transferred). \r
+\r
+ The DMA data counter can be written only when the DMA channel is disabled \r
+ (ie. after transfer complete event).\r
+\r
+ The following function can be used to write the Channel data counter value:\r
+ - void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
+\r
+@note It is advised to use this function rather than DMA_Init() in situations where\r
+ only the Data buffer needs to be reloaded.\r
+\r
+ The DMA data counter can be read to indicate the number of remaining transfers for\r
+ the relative DMA channel. This counter is decremented at the end of each data \r
+ transfer and when the transfer is complete: \r
+ - If Normal mode is selected: the counter is set to 0.\r
+ - If Circular mode is selected: the counter is reloaded with the initial value\r
+ (configured before enabling the DMA channel)\r
+ \r
+ The following function can be used to read the Channel data counter value:\r
+ - uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param DataNumber: The number of data units in the current DMAy Channelx\r
+ * transfer. \r
+ * @note This function can only be used when the DMAy_Channelx is disabled. \r
+ * @retval None.\r
+ */\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ \r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DataNumber; \r
+}\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current\r
+ * DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @retval The number of remaining data units in the current DMAy Channelx\r
+ * transfer.\r
+ */\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Return the number of remaining data units for DMAy Channelx */\r
+ return ((uint16_t)(DMAy_Channelx->CNDTR));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This subsection provides functions allowing to configure the DMA Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage the\r
+ DMA controller events: Polling mode or Interrupt mode. \r
+ \r
+ Polling Mode\r
+ =============\r
+ Each DMA channel can be managed through 4 event Flags:\r
+ (y : DMA Controller number \r
+ x : DMA channel number )\r
+ 1. DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred\r
+ 2. DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occured\r
+ 3. DMAy_FLAG_TEx : to indicate that a Transfer Error occured.\r
+ 4. DMAy_FLAG_GLx : to indicate that at least one of the events described \r
+ above occured. \r
+\r
+@note Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the \r
+ same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+ - void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+\r
+ Interrupt Mode\r
+ ===============\r
+ Each DMA channel can be managed through 4 Interrupts:\r
+\r
+ Interrupt Source\r
+ ----------------\r
+ 1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete event. \r
+ 2. DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete event.\r
+ 3. DMA_IT_TE : specifies the interrupt source for the transfer errors event.\r
+ 4. DMA_IT_GL : to indicate that at least one of the interrupts described \r
+ above occurred. \r
+\r
+@note Clearing DMA_IT_GL interrupt results in clearing all other interrupts of the \r
+ same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).\r
+ \r
+ In this Mode it is advised to use the following functions:\r
+ - void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+ - ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+ - void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx interrupts.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
+ * or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @param NewState: new state of the specified DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
+ * @param DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * \r
+ * @note\r
+ * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags \r
+ * relative to the same channel is set (Transfer Complete, Half-transfer \r
+ * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or \r
+ * DMAy_FLAG_TEx). \r
+ * \r
+ * @retval The new state of DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA flag */\r
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the DMA_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's pending flags.\r
+ * @param DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * \r
+ * @note\r
+ * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags\r
+ * relative to the same channel (Transfer Complete, Half-transfer Complete and \r
+ * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). \r
+ * \r
+ * @retval None\r
+ */\r
+void DMA_ClearFlag(uint32_t DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
+\r
+ if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA1->IFCR = DMA_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
+ * @param DMA_IT: specifies the DMA interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * \r
+ * @note\r
+ * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other \r
+ * interrupts relative to the same channel is set (Transfer Complete, \r
+ * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, \r
+ * DMAy_IT_HTx or DMAy_IT_TEx). \r
+ * \r
+ * @retval The new state of DMA_IT (SET or RESET).\r
+ */\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA interrupt */\r
+ if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * \r
+ * @note\r
+ * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other \r
+ * interrupts relative to the same channel (Transfer Complete, Half-transfer \r
+ * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and \r
+ * DMAy_IT_TEx). \r
+ * \r
+ * @retval None\r
+ */\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA1->IFCR = DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_exti.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the EXTI peripheral: \r
+ * - Initialization and Configuration\r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim \r
+ * \r
+ * ===================================================================\r
+ * EXTI features\r
+ * ===================================================================\r
+ * \r
+ * External interrupt/event lines are mapped as following:\r
+ * 1- All available GPIO pins are connected to the 16 external \r
+ * interrupt/event lines from EXTI0 to EXTI15.\r
+ * 2- EXTI line 16 is connected to the PVD output\r
+ * 3- EXTI line 17 is connected to the RTC Alarm event\r
+ * 4- EXTI line 18 is connected to the USB Device FS wakeup event\r
+ * 5- EXTI line 19 is connected to the RTC Tamper and TimeStamp events\r
+ * 6- EXTI line 20 is connected to the RTC Wakeup event\r
+ * 7- EXTI line 21 is connected to the Comparator 1 wakeup event \r
+ * 8- EXTI line 22 is connected to the Comparator 2 wakeup event\r
+ *\r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * \r
+ * In order to use an I/O pin as an external interrupt source, follow\r
+ * steps below:\r
+ * 1- Configure the I/O in input mode using GPIO_Init()\r
+ * 2- Select the input source pin for the EXTI line using \r
+ * SYSCFG_EXTILineConfig()\r
+ * 3- Select the mode(interrupt, event) and configure the trigger \r
+ * selection (Rising, falling or both) using EXTI_Init()\r
+ * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()\r
+ * \r
+ *@note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx\r
+ * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_exti.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI \r
+ * @brief EXTI driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x00000000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000; \r
+ EXTI->FTSR = 0x00000000; \r
+ EXTI->PR = 0x007FFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the EXTI peripheral according to the specified\r
+ * parameters in the EXTI_InitStruct.\r
+ * EXTI_Line specifies the EXTI line (EXTI0....EXTI22) \r
+ * EXTI_Mode specifies which EXTI line is used as interrupt or an event\r
+ * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt\r
+ * pending bit will be set\r
+ * EXTI_LineCmd controls (Enable/Disable) the EXTI line\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+ * that contains the configuration information for the EXTI peripheral.\r
+ * @retval None\r
+ */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ \r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ /* Disable the selected external lines */\r
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each EXTI_InitStruct member with its reset value.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param EXTI_Line: specifies the EXTI line on which the software interrupt\r
+ * will be generated.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+ * @retval None\r
+ */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Group2 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param EXTI_Line: specifies the EXTI line flag to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending flags.\r
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param EXTI_Line: specifies the EXTI line to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending bits.\r
+ * @param EXTI_Line: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the Flash firmware functions. These functions \r
+ * can be executed from Internal FLASH or Internal SRAM memories. \r
+ * The functions that should be called from SRAM are defined inside \r
+ * the "stm32l1xx_flash_ramfunc.c" file.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the FLASH peripheral:\r
+ * - FLASH Interface configuration\r
+ * - FLASH Memory Programming\r
+ * - DATA EEPROM Programming\r
+ * - Option Bytes Programming\r
+ * - Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * \r
+ * This driver provides functions to configure and program the Flash \r
+ * memory of all STM32L1xx devices\r
+ * These functions are split in 5 groups\r
+ * \r
+ * 1. FLASH Interface configuration functions: this group includes \r
+ * the management of following features:\r
+ * - Set the latency\r
+ * - Enable/Disable the prefetch buffer\r
+ * - Enable/Disable the 64 bit Read Access \r
+ * - Enable/Disable the RUN PowerDown mode\r
+ * - Enable/Disable the SLEEP PowerDown mode \r
+ * \r
+ * 2. FLASH Memory Programming functions: this group includes all \r
+ * needed functions to erase and program the main memory:\r
+ * - Lock and Unlock the Flash interface.\r
+ * - Erase function: Erase Page.\r
+ * - Program functions: Fast Word and Half Page(should be \r
+ * executed from internal SRAM).\r
+ * \r
+ * 3. DATA EEPROM Programming functions: this group includes all \r
+ * needed functions to erase and program the DATA EEPROM memory:\r
+ * - Lock and Unlock the DATA EEPROM interface.\r
+ * - Erase function: Erase Word, erase Double Word (should be \r
+ * executed from internal SRAM).\r
+ * - Program functions: Fast Program Byte, Fast Program Half-Word, \r
+ * FastProgramWord, Program Byte, Program Half-Word, \r
+ * Program Word and Program Double-Word (should be executed \r
+ * from internal SRAM).\r
+ * \r
+ * 4. FLASH Option Bytes Programming functions: this group includes \r
+ * all needed functions to:\r
+ * - Lock and Unlock the Flash Option bytes. \r
+ * - Set/Reset the write protection\r
+ * - Set the Read protection Level\r
+ * - Set the BOR level\r
+ * - Program the user option Bytes \r
+ * - Launch the Option Bytes loader\r
+ * - Get the Write protection\r
+ * - Get the read protection status\r
+ * - Get the BOR level\r
+ * - Get the user option bytes \r
+ * \r
+ * 5. FLASH Interrupts and flag management functions: this group \r
+ * includes all needed functions to:\r
+ * - Enable/Disable the flash interrupt sources\r
+ * - Get flags status\r
+ * - Clear flags\r
+ * - Get Flash operation status\r
+ * - Wait for last flash operation \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_flash.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+ \r
+/* FLASH Mask */\r
+#define RDPRT_MASK ((uint32_t)0x00000002)\r
+#define WRP01_MASK ((uint32_t)0x0000FFFF)\r
+#define WRP23_MASK ((uint32_t)0xFFFF0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions\r
+ * @brief FLASH Interface configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ FLASH Interface configuration functions\r
+ =============================================================================== \r
+\r
+ FLASH_Interface configuration_Functions, includes the following functions:\r
+ - void FLASH_SetLatency(uint32_t FLASH_Latency):\r
+ To correctly read data from Flash memory, the number of wait states (LATENCY) \r
+ must be correctly programmed according to the frequency of the CPU clock \r
+ (HCLK) and the supply voltage of the device.\r
+ ---------------------------------------------------------------- \r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------| \r
+ | (Latency) | voltage range | voltage range | \r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------| \r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |-------------- |----------------|---------------|---------------| \r
+ |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |---------------|----------------|---------------|---------------| \r
+ |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| \r
+ ---------------------------------------------------------------- \r
+ \r
+ - void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+ - void FLASH_ReadAccess64Cmd(FunctionalState NewState);\r
+ - void FLASH_RUNPowerDownCmd(FunctionalState NewState);\r
+ - void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);\r
+ - void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+ \r
+ Here below the allowed configuration of Latency, 64Bit access and prefetch buffer\r
+ -------------------------------------------------------------------------------- \r
+ | | ACC64 = 0 | ACC64 = 1 |\r
+ | Latency |----------------|---------------|---------------|---------------| \r
+ | | PRFTEN = 0 | PRFTEN = 1 | PRFTEN = 0 | PRFTEN = 1 | \r
+ |---------------|----------------|---------------|---------------|---------------| \r
+ |0WS(1CPU cycle)| YES | NO | YES | YES |\r
+ |---------------|----------------|---------------|---------------|---------------| \r
+ |1WS(2CPU cycle)| NO | NO | YES | YES | \r
+ -------------------------------------------------------------------------------- \r
+ All these functions don't need the unlock sequence.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the code latency value.\r
+ * @param FLASH_Latency: specifies the FLASH Latency value.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
+ * @arg FLASH_Latency_1: FLASH One Latency cycle\r
+ * @retval None\r
+ */\r
+void FLASH_SetLatency(uint32_t FLASH_Latency)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
+ \r
+ /* Read the ACR register */\r
+ tmpreg = FLASH->ACR; \r
+ \r
+ /* Sets the Latency value */\r
+ tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));\r
+ tmpreg |= FLASH_Latency;\r
+ \r
+ /* Write the ACR register */\r
+ FLASH->ACR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Prefetch Buffer.\r
+ * @param NewState: new state of the FLASH prefetch buffer.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables read access to flash by 64 bits.\r
+ * @param NewState: new state of the FLASH read access mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @note - If this bit is set, the Read access 64 bit is used.\r
+ * - If this bit is reset, the Read access 32 bit is used.\r
+ * @note - This bit cannot be written at the same time as the LATENCY and \r
+ * PRFTEN bits. \r
+ * - To reset this bit, the LATENCY should be zero wait state and the \r
+ * prefetch off.\r
+ * @retval None\r
+ */\r
+void FLASH_ReadAccess64Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->ACR |= FLASH_ACR_ACC64;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the power down mode during Sleep mode.\r
+ * @note This function is used to power down the FLASH when the system is in SLEEP LP mode. \r
+ * @param NewState: new state of the power down mode during sleep mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */\r
+ FLASH->ACR |= FLASH_ACR_SLEEP_PD;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions\r
+ * @brief FLASH Memory Programming functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ FLASH Memory Programming functions\r
+ =============================================================================== \r
+\r
+ The FLASH Memory Programming functions, includes the following functions:\r
+ - void FLASH_Unlock(void);\r
+ - void FLASH_Lock(void);\r
+ - FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+ - FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);\r
+ \r
+ Any operation of erase or program should follow these steps:\r
+\r
+ 1. Call the FLASH_Unlock() function to enable the flash control register and \r
+ program memory access\r
+\r
+ 2. Call the desired function to erase page or program data\r
+\r
+ 3. Call the FLASH_Lock() to disable the flash program memory access \r
+ (recommended to protect the FLASH memory against possible unwanted operation)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the FLASH control register and program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)\r
+ {\r
+ /* Unlocking the data memory and FLASH_PECR register access */\r
+ DATA_EEPROM_Unlock();\r
+ \r
+ /* Unlocking the program memory access */\r
+ FLASH->PRGKEYR = FLASH_PRGKEY1;\r
+ FLASH->PRGKEYR = FLASH_PRGKEY2; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the Program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Lock(void)\r
+{\r
+ /* Set the PRGLOCK Bit to lock the program memory access */\r
+ FLASH->PECR |= FLASH_PECR_PRGLOCK;\r
+}\r
+\r
+/**\r
+ * @brief Erases a specified page in program memory.\r
+ * @note - To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param Page_Address: The page address in program memory to be erased.\r
+ * @note A Page is erased in the Program memory only if the address to load \r
+ * is the start address of a page (multiple of 256 bytes). \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to erase the page */\r
+\r
+ /* Set the ERASE bit */\r
+ FLASH->PECR |= FLASH_PECR_ERASE;\r
+\r
+ /* Set PROG bit */\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write 00000000h to the first word of the program page to erase */\r
+ *(__IO uint32_t *)Page_Address = 0x00000000;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ /* If the erase operation is completed, disable the ERASE and PROG bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); \r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in program memory.\r
+ * @note - To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new word */ \r
+ *(__IO uint32_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Group3 DATA EEPROM Programming functions\r
+ * @brief DATA EEPROM Programming functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DATA EEPROM Programming functions\r
+ =============================================================================== \r
+\r
+ The DATA_EEPROM Programming_Functions, includes the following functions:\r
+ - void DATA_EEPROM_Unlock(void);\r
+ - void DATA_EEPROM_Lock(void);\r
+ - FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);\r
+ - FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);\r
+ - FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);\r
+ - FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);\r
+ - FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);\r
+ - FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+ - FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);\r
+ \r
+ Any operation of erase or program should follow these steps:\r
+\r
+ 1. Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access\r
+ and Flash program erase control register access.\r
+\r
+ 2. Call the desired function to erase or program data\r
+\r
+ 3. Call the DATA_EEPROM_Lock() to disable the data EEPROM access\r
+ and Flash program erase control register access(recommended\r
+ to protect the DATA_EEPROM against possible unwanted operation)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the data memory and FLASH_PECR register access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)\r
+ { \r
+ /* Unlocking the Data memory and FLASH_PECR register access*/\r
+ FLASH->PEKEYR = FLASH_PEKEY1;\r
+ FLASH->PEKEYR = FLASH_PEKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the Data memory and FLASH_PECR register access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_Lock(void)\r
+{\r
+ /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */\r
+ FLASH->PECR |= FLASH_PECR_PELOCK;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables DATA EEPROM fixed Time programming (2*Tprog).\r
+ * @param NewState: new state of the DATA EEPROM fixed Time programming mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;\r
+ }\r
+ else\r
+ {\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Erase a word in data memory.\r
+ * @param Address: specifies the address to be erased\r
+ * @note1 - A data memory word is erased in the data memory only if the address \r
+ * to load is the start address of a word (multiple of a word).\r
+ * @note2 - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Write "00000000h" to valid address in the data memory" */\r
+ *(__IO uint32_t *) Address = 0x00000000;\r
+ }\r
+ \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ \r
+ if(Data != (uint8_t)0x00) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new Data */ \r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr;\r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ } \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ \r
+ if(Data != (uint16_t)0x0000) \r
+ {\r
+ /* If the previous operation is completed, proceed to write the new data */ \r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ else\r
+ {\r
+ if((Address & 0x3) != 0x3)\r
+ { \r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ }\r
+ else\r
+ {\r
+ DATA_EEPROM_FastProgramByte(Address, 0x00);\r
+ DATA_EEPROM_FastProgramByte(Address + 1, 0x00); \r
+ } \r
+ } \r
+ } \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to the data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note This function assumes that the is data word is already erased. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Clear the FTDW bit */\r
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */ \r
+ *(__IO uint32_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a Byte at a specified address in data memory without erase.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming. \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address)); \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if(Data != (uint8_t) 0x00)\r
+ { \r
+ *(__IO uint8_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ }\r
+ else\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ } \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a half word at a specified address in data memory without erase.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation)\r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmpaddr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if(Data != (uint16_t)0x0000)\r
+ {\r
+ *(__IO uint16_t *)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ else\r
+ {\r
+ if((Address & 0x3) != 0x3)\r
+ {\r
+ tmpaddr = Address & 0xFFFFFFFC;\r
+ tmp = * (__IO uint32_t *) tmpaddr;\r
+ tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));\r
+ tmp &= ~tmpaddr; \r
+ status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);\r
+ status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); \r
+ }\r
+ else\r
+ {\r
+ DATA_EEPROM_FastProgramByte(Address, 0x00);\r
+ DATA_EEPROM_FastProgramByte(Address + 1, 0x00); \r
+ } \r
+ } \r
+ } \r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address in data memory without erase.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before \r
+ * this function to configure the Fixed Time Programming. \r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ *(__IO uint32_t *)Address = Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group4 Option Bytes Programming functions\r
+ * @brief Option Bytes Programming functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Option Bytes Programming functions\r
+ =============================================================================== \r
+\r
+ The FLASH_Option Bytes Programming_functions, includes the following functions:\r
+ - void FLASH_OB_Unlock(void);\r
+ - void FLASH_OB_Lock(void);\r
+ - void FLASH_OB_Launch(void);\r
+ - FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+ - FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+ - FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+ - FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+ - uint8_t FLASH_OB_GetUser(void);\r
+ - uint32_t FLASH_OB_GetWRP(void);\r
+ - FlagStatus FLASH_OB_GetRDP(void);\r
+ - uint8_t FLASH_OB_GetBOR(void);\r
+ \r
+ Any operation of erase or program should follow these steps:\r
+ \r
+ 1. Call the FLASH_OB_Unlock() function to enable the Flash option control register access\r
+ \r
+ 2. Call one or several functions to program the desired option bytes \r
+ - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable \r
+ the desired sector write protection\r
+ - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level\r
+ - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure \r
+ the user option Bytes: IWDG, STOP and the Standby.\r
+ - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level \r
+ - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes \r
+ \r
+ 3. Once all needed option bytes to be programmed are correctly written, call the\r
+ FLASH_OB_Launch(void) function to launch the Option Bytes programming process. \r
+ \r
+ 4. Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended\r
+ to protect the option Bytes against possible unwanted operations)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Unlock(void)\r
+{\r
+ if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)\r
+ {\r
+ /* Unlocking the data memory and FLASH_PECR register access */\r
+ DATA_EEPROM_Unlock();\r
+ \r
+ /* Unlocking the option bytes block access */\r
+ FLASH->OPTKEYR = FLASH_OPTKEY1;\r
+ FLASH->OPTKEYR = FLASH_OPTKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTLOCK Bit to lock the option bytes block access */\r
+ FLASH->PECR |= FLASH_PECR_OPTLOCK;\r
+}\r
+\r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OBL_Launch bit to lauch the option byte loading */\r
+ FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param OB_WRP: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @arg value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511\r
+ * @arg OB_WRP_AllPages\r
+ * @param NewState: new state of the specified FLASH Pages Wtite protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)\r
+{\r
+ uint32_t WRP01_Data = 0, WRP23_Data = 0;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(OB_WRP));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));\r
+ WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); \r
+ tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);\r
+ OB->WRP01 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data);\r
+ OB->WRP23 = tmp2; \r
+ } \r
+ \r
+ else\r
+ {\r
+ WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));\r
+ WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); \r
+\r
+ tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);\r
+ OB->WRP01 = tmp1;\r
+ \r
+ tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data);\r
+ OB->WRP23 = tmp2;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+\r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param FLASH_ReadProtection_Level: specifies the read protection level. \r
+ * This parameter can be:\r
+ * @arg OB_RDP_Level_0: No protection\r
+ * @arg OB_RDP_Level_1: Read protection of the memory \r
+ * @arg OB_RDP_Level_2: Chip protection\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint8_t tmp1 = 0;\r
+ uint32_t tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP(OB_RDP));\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* calculate the option byte to write */\r
+ tmp1 = (uint8_t)(~(OB_RDP ));\r
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* program read protection level */\r
+ OB->RDP = tmp2;\r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Read protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param OB_IWDG: Selects the WDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software WDG selected\r
+ * @arg OB_IWDG_HW: Hardware WDG selected\r
+ * @param OB_STOP: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param OB_STDBY: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = (FLASH->OBR & 0x000F0000) >> 16;\r
+ \r
+ /* Calculate the user option byte to write */ \r
+ tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10));\r
+ tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Write the User Option Byte */ \r
+ OB->USER = tmp; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH brownout reset threshold level Option Byte.\r
+ * @note - To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation) \r
+ * @param OB_BOR: Selects the brownout reset threshold level\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD \r
+ * power supply reaches the PDR(Power Down Reset) threshold (1.5V)\r
+ * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply\r
+ * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply\r
+ * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply\r
+ * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply\r
+ * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOR_LEVEL(OB_BOR));\r
+\r
+ /* Get the User Option byte register */\r
+ tmp1 = (FLASH->OBR & 0x00700000) >> 16;\r
+ \r
+ /* Calculate the option byte to write */\r
+ tmp = (uint32_t)~(OB_BOR | tmp1)<<16;\r
+ tmp |= (OB_BOR | tmp1);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Write the BOR Option Byte */ \r
+ OB->USER = tmp; \r
+ }\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes .\r
+ */\r
+uint8_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint8_t)(FLASH->OBR >> 20);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes value.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes value\r
+ */\r
+uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Read out Protection Status is set or not.\r
+ * @param None\r
+ * @retval FLASH ReadOut Protection Status(SET or RESET)\r
+ */\r
+FlagStatus FLASH_OB_GetRDP(void)\r
+{\r
+ FlagStatus readstatus = RESET;\r
+ \r
+ if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)\r
+ {\r
+ readstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ readstatus = RESET;\r
+ }\r
+ return readstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH BOR level.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes .\r
+ */\r
+uint8_t FLASH_OB_GetBOR(void)\r
+{\r
+ /* Return the BOR level */\r
+ return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified FLASH interrupts.\r
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or \r
+ * disabled.\r
+ * This parameter can be any combination of the following values: \r
+ * @arg FLASH_IT_EOP: FLASH end of programming Interrupt\r
+ * @arg FLASH_IT_ERR: FLASH Error Interrupt \r
+ * @retval None \r
+ */\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->PECR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->PECR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @param FLASH_FLAG: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode\r
+ * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag \r
+ * @retval The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));\r
+\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH_FLAG (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the FLASH\92s pending flags.\r
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag \r
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag \r
+ * @retval None\r
+ */\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.\r
+ */\r
+FLASH_Status FLASH_GetStatus(void)\r
+{\r
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ FLASHstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
+ { \r
+ FLASHstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00)\r
+ {\r
+ FLASHstatus = FLASH_ERROR_PROGRAM; \r
+ }\r
+ else\r
+ {\r
+ FLASHstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the FLASH Status */\r
+ return FLASHstatus;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH programming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the FLASH Status */\r
+ status = FLASH_GetStatus();\r
+ \r
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetStatus();\r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_flash_ramfunc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides all the Flash firmware functions which should be\r
+ * executed from the internal SRAM. This file should be placed in \r
+ * internal SRAM. \r
+ * Other FLASH memory functions that can be used from the FLASH are \r
+ * defined in the "stm32l1xx_flash.c" file. \r
+ * @verbatim \r
+ * \r
+ * ARM Compiler\r
+ * ------------\r
+ * RAM functions are defined using the toolchain options. \r
+ * Functions that are be executed in RAM should reside in a separate\r
+ * source module. Using the 'Options for File' dialog you can simply change\r
+ * the 'Code / Const' area of a module to a memory space in physical RAM.\r
+ * Available memory areas are declared in the 'Target' tab of the \r
+ * 'Options for Target' dialog.\r
+ * \r
+ * ICCARM Compiler\r
+ * ---------------\r
+ * RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+ * \r
+ * GNU Compiler\r
+ * ------------\r
+ * RAM functions are defined using a specific toolchain attribute\r
+ * "__attribute__((section(".data")))".\r
+ * \r
+ * TASKING Compiler\r
+ * ----------------\r
+ * RAM functions are defined using a specific toolchain pragma. This \r
+ * pragma is defined inside this file. \r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_flash.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static __RAM_FUNC GetStatus(void);\r
+static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup FLASH_Group1\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */ \r
+#if defined ( __TASKING__ )\r
+#pragma section_code_init on\r
+#endif\r
+\r
+/**\r
+ * @brief Enable or disable the power down mode during RUN mode.\r
+ * @note: This function can be used only when the user code is running from Internal SRAM\r
+ * @param NewState: new state of the power down mode during RUN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Unlock the RUN_PD bit */\r
+ FLASH->PDKEYR = FLASH_PDKEY1;\r
+ FLASH->PDKEYR = FLASH_PDKEY2;\r
+ \r
+ /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;\r
+\r
+ if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)\r
+ {\r
+ status = FLASH_ERROR_PROGRAM;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */\r
+ FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);\r
+ }\r
+\r
+ /* Return the Write Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Group2\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Programs a half page in program memory.\r
+ * @param Address: specifies the address to be written.\r
+ * @param pBuffer: pointer to the buffer containing the data to be written to \r
+ * the half page.\r
+ * @note - To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * - Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @note Half page write is possible only from SRAM.\r
+ * @note If there are more than 32 words to write, after 32 words another \r
+ * Half Page programming operation starts and has to be finished.\r
+ * @note A half page is written to the program memory only if the first \r
+ * address to load is the start address of a half page (multiple of 128 \r
+ * bytes) and the 31 remaining words to load are in the same half page.\r
+ * @note During the Program memory half page write all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.)\r
+ * @note If a PGAERR is set during a Program memory half page write, the \r
+ * complete write operation is aborted. Software should then reset the \r
+ * FPRG and PROG/DATA bits and restart the write operation from the \r
+ * beginning. \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)\r
+{\r
+ uint32_t count = 0; \r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new \r
+ half page */\r
+ FLASH->PECR |= FLASH_PECR_FPRG;\r
+ FLASH->PECR |= FLASH_PECR_PROG;\r
+ \r
+ /* Write one half page directly with 32 different words */\r
+ while(count < 32)\r
+ {\r
+ *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);\r
+ count ++; \r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* if the write operation is completed, disable the PROG and FPRG bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Group3\r
+ *\r
+@verbatim \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Erase a double word in data memory.\r
+ * @param Address: specifies the address to be erased\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note Data memory double word erase is possible only from SRAM.\r
+ * @note A double word is erased to the data memory only if the first address \r
+ * to load is the start address of a double word (multiple of 8 bytes) \r
+ * @note During the Data memory double word erase, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.) \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+\r
+__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to erase the next double word */\r
+ /* Set the ERASE bit */\r
+ FLASH->PECR |= FLASH_PECR_ERASE;\r
+\r
+ /* Set DATA bit */\r
+ FLASH->PECR |= FLASH_PECR_DATA;\r
+ \r
+ /* Write 00000000h to the 2 words to erase */\r
+ *(__IO uint64_t *)Address = 0x00000000;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* If the erase operation is completed, disable the ERASE and DATA bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);\r
+ } \r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write a double word in data memory without erase.\r
+ * @param Address: specifies the address to be written.\r
+ * @param Data: specifies the data to be written.\r
+ * @note - To correctly run this function, the DATA_EEPROM_Unlock() function\r
+ * must be called before.\r
+ * - Call the DATA_EEPROM_Lock() to he data EEPROM access\r
+ * and Flash program erase control register access(recommended to protect \r
+ * the DATA_EEPROM against possible unwanted operation) \r
+ * @note Data memory double word write is possible only from SRAM.\r
+ * @note A data memory double word is written to the data memory only if the \r
+ * first address to load is the start address of a double word (multiple \r
+ * of double word). \r
+ * @note During the Data memory double word write, all read operations are \r
+ * forbidden (this includes DMA read operations and debugger read \r
+ * operations such as breakpoints, periodic updates, etc.) \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */ \r
+__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new data*/\r
+ FLASH->PECR |= FLASH_PECR_FPRG;\r
+ FLASH->PECR |= FLASH_PECR_DATA;\r
+ \r
+ /* Write the 2 words */ \r
+ *(__IO uint32_t *)Address = (uint32_t) Data;\r
+ Address += 4;\r
+ *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* If the write operation is completed, disable the FPRG and DATA bits */\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);\r
+ FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); \r
+ }\r
+ /* Return the Write Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+static __RAM_FUNC GetStatus(void)\r
+{\r
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ FLASHstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
+ { \r
+ FLASHstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00)\r
+ {\r
+ FLASHstatus = FLASH_ERROR_PROGRAM; \r
+ }\r
+ else\r
+ {\r
+ FLASHstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the FLASH Status */\r
+ return FLASHstatus;\r
+}\r
+\r
+/**\r
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH programming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+static __RAM_FUNC WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the FLASH Status */\r
+ status = GetStatus();\r
+ \r
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = GetStatus();\r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+#if defined ( __TASKING__ )\r
+#pragma section_code_init restore\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the GPIO peripheral: \r
+ * - Initialization and Configuration\r
+ * - GPIO Read and Write\r
+ * - GPIO Alternate functions configuration\r
+ * \r
+ * @verbatim\r
+ *\r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()\r
+ * \r
+ * 2. Configure the GPIO pin(s) using GPIO_Init()\r
+ * Four possible configuration are available for each pin:\r
+ * - Input: Floating, Pull-up, Pull-down.\r
+ * - Output: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ * Open Drain (Pull-up, Pull-down or no Pull).\r
+ * In output mode, the speed is configurable: Very Low, Low,\r
+ * Medium or High.\r
+ * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ * Open Drain (Pull-up, Pull-down or no Pull).\r
+ * - Analog: required mode when a pin is to be used as ADC channel,\r
+ * DAC output or comparator input.\r
+ * \r
+ * 3- Peripherals alternate function:\r
+ * - For ADC, DAC and comparators, configure the desired pin in \r
+ * analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN\r
+ * - For other peripherals (TIM, USART...):\r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function mode using\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()\r
+ * \r
+ * 5. To set/reset the level of a pin configured in output mode use\r
+ * GPIO_SetBits()/GPIO_ResetBits()\r
+ * \r
+ * 6. During and just after reset, the alternate functions are not \r
+ * active and the GPIO pins are configured in input floating mode\r
+ * (except JTAG pins).\r
+ *\r
+ * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as \r
+ * general-purpose (PC14 and PC15, respectively) when the LSE\r
+ * oscillator is off. The LSE has priority over the GPIO function.\r
+ *\r
+ * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ * general-purpose PH0 and PH1, respectively, when the HSE \r
+ * oscillator is off. The HSE has priority over the GPIO function.\r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Group1 Initialization and Configuration\r
+ * @brief Initialization and Configuration\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset \r
+ * values.\r
+ * By default, The GPIO pins are configured in input floating mode\r
+ * (except JTAG pins).\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ if(GPIOx == GPIOA)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); \r
+ }\r
+ else if(GPIOx == GPIOB)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOC)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOD)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOE)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if(GPIOx == GPIOH)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified \r
+ * parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that \r
+ * contains the configuration information for the specified GPIO\r
+ * peripheral.\r
+ * GPIO_Pin: selects the pin to be configured: GPIO_Pin_0 -> GPIO_Pin_15\r
+ * GPIO_Mode: selects the mode of the pin: \r
+ * - Input mode: GPIO_Mode_IN\r
+ * - Output mode: GPIO_Mode_OUT\r
+ * - Alternate Function mode: GPIO_Mode_AF\r
+ * - Analog mode: GPIO_Mode_AN\r
+ * GPIO_Speed: selects the speed of the pin if configured in Output:\r
+ * - Very Low: GPIO_Speed_400KHz\r
+ * - Low: GPIO_Speed_2MHz\r
+ * - Medium: GPIO_Speed_10MHz\r
+ * - High: GPIO_Speed_40MHz\r
+ * GPIO_OType: selects the Output type (if the selected mode is output):\r
+ * - Push-pull: GPIO_OType_PP\r
+ * - Open Drain: GPIO_OType_OD\r
+ * GPIO_PuPd: configures the Pull-up/Pull-down resistor on the pin:\r
+ * - pull-up: GPIO_PuPd_UP\r
+ * - pull-down: GPIO_PuPd_DOWN\r
+ * - Neither pull-up nor Pull-down: GPIO_PuPd_NOPULL\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
+\r
+ /* -------------------------Configure the port pins---------------- */\r
+ /*-- GPIO Mode Configuration --*/\r
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+ if (currentpin == pos)\r
+ {\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
+\r
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
+\r
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
+ {\r
+ /* Check Speed mode parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+\r
+ /* Speed mode configuration */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
+\r
+ /*Check Output mode parameters */\r
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
+\r
+ /* Output mode configuration */\r
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
+ }\r
+\r
+ /* Pull-up Pull down resistor configuration */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
+ GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;\r
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint32_t tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group2 GPIO Read and Write\r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ GPIO Read and Write\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRRL = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRRH = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enum values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRRL = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRRH = GPIO_Pin ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data \r
+ * register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions\r
+ * @brief GPIO Alternate functions configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ GPIO Alternate functions configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @param GPIO_AFSelection: selects the pin to used as Alternat function.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization\r
+ * @arg GPIO_AF_MCO: Microcontroller clock output\r
+ * @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out,\r
+ * 512 Hz clock output (with an LSE oscillator of 32.768 kHz)\r
+ * @arg GPIO_AF_WKUP: wakeup\r
+ * @arg GPIO_AF_SWJ: SWJ (SW and JTAG)\r
+ * @arg GPIO_AF_TRACE\r
+ * @arg GPIO_AF_TIM2\r
+ * @arg GPIO_AF_TIM3\r
+ * @arg GPIO_AF_TIM4\r
+ * @arg GPIO_AF_TIM9\r
+ * @arg GPIO_AF_TIM10\r
+ * @arg GPIO_AF_TIM11\r
+ * @arg GPIO_AF_I2C1\r
+ * @arg GPIO_AF_I2C2\r
+ * @arg GPIO_AF_SPI1\r
+ * @arg GPIO_AF_SPI2\r
+ * @arg GPIO_AF_USART1\r
+ * @arg GPIO_AF_USART2\r
+ * @arg GPIO_AF_USART3\r
+ * @arg GPIO_AF_USB\r
+ * @arg GPIO_AF_LCD\r
+ * @arg GPIO_AF_RI\r
+ * @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal\r
+ * @note: The pin should already been configured in Alternate Function mode(AF)\r
+ * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * @note: Please refer to the Alternate function mapping table in the device \r
+ * datasheet for the detailed mapping of the system and peripherals\92\r
+ * alternate function I/O pins. \r
+ * @note: EVENTOUT is not mapped on PH0, PH1 and PH2. \r
+ * @retval None\r
+ */\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
+{\r
+ uint32_t temp = 0x00;\r
+ uint32_t temp_2 = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ assert_param(IS_GPIO_AF(GPIO_AF));\r
+ \r
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Inter-integrated circuit (I2C)\r
+ * - Initialization and Configuration\r
+ * - Data transfers\r
+ * - PEC management\r
+ * - DMA transfers management\r
+ * - Interrupts, events and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)\r
+ * function for I2C1 or I2C2.\r
+ *\r
+ * 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using \r
+ * RCC_AHBPeriphClockCmd() function. \r
+ *\r
+ * 3. Peripherals alternate function: \r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function by:\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged\r
+ * Address using the I2C_Init() function.\r
+ *\r
+ * 5. Optionally you can enable/configure the following parameters without\r
+ * re-initialization (i.e there is no need to call again I2C_Init() function):\r
+ * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function\r
+ * - Enable the dual addressing mode using I2C_DualAddressCmd() function\r
+ * - Enable the general call using the I2C_GeneralCallCmd() function\r
+ * - Enable the clock stretching using I2C_StretchClockCmd() function\r
+ * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()\r
+ * function\r
+ * - Enable the PEC Calculation using I2C_CalculatePEC() function\r
+ * - For SMBus Mode: \r
+ * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function\r
+ * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function\r
+ *\r
+ * 6. Enable the NVIC and the corresponding interrupt using the function \r
+ * I2C_ITConfig() if you need to use interrupt mode. \r
+ *\r
+ * 7. When using the DMA mode \r
+ * - Configure the DMA using DMA_Init() function\r
+ * - Active the needed channel Request using I2C_DMACmd() or\r
+ I2C_DMALastTransferCmd() function\r
+ * \r
+ * 8. Enable the I2C using the I2C_Cmd() function.\r
+ * \r
+ * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the \r
+ * transfers. \r
+ *\r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_i2c.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C \r
+ * @brief I2C driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*<! I2C registers Masks */\r
+#define FLAG_MASK ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */\r
+#define ITEN_MASK ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ if (I2Cx == I2C1)\r
+ {\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the I2Cx peripheral according to the specified \r
+ * parameters in the I2C_InitStruct.\r
+ * @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency \r
+ * (I2C peripheral input clock) must be a multiple of 10 MHz. \r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+ * contains the configuration information for the specified I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, freqrange = 0;\r
+ uint16_t result = 0x04;\r
+ uint32_t pclk1 = 8000000;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+\r
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear frequency FREQ[5:0] bits */\r
+ tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);\r
+ /* Get pclk1 frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ pclk1 = rcc_clocks.PCLK1_Frequency;\r
+ /* Set frequency bits depending on pclk1 value */\r
+ freqrange = (uint16_t)(pclk1 / 1000000);\r
+ tmpreg |= freqrange;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+\r
+/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
+ /* Disable the selected I2C peripheral to configure TRISE */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
+ /* Reset tmpreg value */\r
+ /* Clear F/S, DUTY and CCR[11:0] bits */\r
+ tmpreg = 0;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
+ /* Test if CCR value is under 0x4*/\r
+ if (result < 0x04)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result = 0x04; \r
+ }\r
+ /* Set speed value for standard mode */\r
+ tmpreg |= result; \r
+ /* Set Maximum Rise Time for standard mode */\r
+ I2Cx->TRISE = freqrange + 1; \r
+ }\r
+ /* Configure speed in fast mode */\r
+ /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral\r
+ input clock) must be a multiple of 10 MHz */\r
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
+ {\r
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
+ }\r
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
+ /* Set DUTY bit */\r
+ result |= I2C_DutyCycle_16_9;\r
+ }\r
+\r
+ /* Test if CCR value is under 0x1*/\r
+ if ((result & I2C_CCR_CCR) == 0)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result |= (uint16_t)0x0001; \r
+ }\r
+ /* Set speed value and set F/S bit for fast mode */\r
+ tmpreg |= (uint16_t)(result | I2C_CCR_FS);\r
+ /* Set Maximum Rise Time for fast mode */\r
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
+ }\r
+\r
+ /* Write to I2Cx CCR */\r
+ I2Cx->CCR = tmpreg;\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+\r
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear ACK, SMBTYPE and SMBUS bits */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure I2Cx: mode and acknowledgement */\r
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
+ /* Set ACK bit according to I2C_Ack value */\r
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
+ /* Set I2Cx Own Address1 and acknowledged address */\r
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2C_InitStruct member with its default value.\r
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+/*---------------- Reset I2C init structure parameters values ----------------*/\r
+ /* initialize the I2C_ClockSpeed member */\r
+ I2C_InitStruct->I2C_ClockSpeed = 5000;\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+ /* Initialize the I2C_DutyCycle member */\r
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication START condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C START condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR1 |= I2C_CR1_START;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication STOP condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C STOP condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR1 |= I2C_CR1_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C acknowledge feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C Acknowledgement.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2Cx->CR1 |= I2C_CR1_ACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified I2C own address2.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the 7bit I2C own address2.\r
+ * @retval None.\r
+ */\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
+{\r
+ uint16_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+\r
+ /* Reset I2Cx Own address2 bit [7:1] */\r
+ tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);\r
+\r
+ /* Set I2Cx Own address2 */\r
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
+\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C dual addressing mode.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C dual addressing mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable dual addressing mode */\r
+ I2Cx->OAR2 |= I2C_OAR2_ENDUAL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable dual addressing mode */\r
+ I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C general call feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C General call.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable generall call */\r
+ I2Cx->CR1 |= I2C_CR1_ENGC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable generall call */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C software reset.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C software reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= I2C_CR1_SWRST;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
+ * @retval None\r
+ */\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
+ {\r
+ /* Drive the SMBusAlert pin Low */\r
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
+ }\r
+ else\r
+ {\r
+ /* Drive the SMBusAlert pin High */\r
+ I2Cx->CR1 &= I2C_SMBusAlert_High;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C ARP.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx ARP. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C ARP */\r
+ I2Cx->CR1 |= I2C_CR1_ENARP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C ARP */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C Clock stretching.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Clock stretching.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable the selected I2C Clock stretching */\r
+ I2Cx->CR1 |= I2C_CR1_NOSTRETCH;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C Clock stretching */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C fast mode duty cycle.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
+ * @retval None\r
+ */\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=2 */\r
+ I2Cx->CCR &= I2C_DutyCycle_2;\r
+ }\r
+ else\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=16/9 */\r
+ I2Cx->CCR |= I2C_DutyCycle_16_9;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits the address byte to select the slave device.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the slave address which will be transmitted\r
+ * @param I2C_Direction: specifies whether the I2C device will be a\r
+ * Transmitter or a Receiver. This parameter can be one of the following values\r
+ * @arg I2C_Direction_Transmitter: Transmitter mode\r
+ * @arg I2C_Direction_Receiver: Receiver mode\r
+ * @retval None.\r
+ */\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction != I2C_Direction_Transmitter)\r
+ {\r
+ /* Set the address bit0 for read */\r
+ Address |= I2C_OAR1_ADD0;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);\r
+ }\r
+ /* Send the address */\r
+ I2Cx->DR = Address;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group2 Data transfers functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data transfers functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends a data byte through the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Data: Byte to be transmitted..\r
+ * @retval None\r
+ */\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the data in the DR register */\r
+ return (uint8_t)I2Cx->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group3 PEC management functions\r
+ * @brief PEC management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ PEC management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C PEC transfer.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C PEC transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC transmission */\r
+ I2Cx->CR1 |= I2C_CR1_PEC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC transmission */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C PEC position.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_PECPosition: specifies the PEC position. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
+ * @retval None\r
+ */\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
+ if (I2C_PECPosition == I2C_PECPosition_Next)\r
+ {\r
+ /* Next byte in shift register is PEC */\r
+ I2Cx->CR1 |= I2C_PECPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* Current byte in shift register is PEC */\r
+ I2Cx->CR1 &= I2C_PECPosition_Current;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx PEC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC calculation */\r
+ I2Cx->CR1 |= I2C_CR1_ENPEC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC calculation */\r
+ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the PEC value for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The PEC value.\r
+ */\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the selected I2C PEC value */\r
+ return ((I2Cx->SR2) >> 8);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA transfers management functions\r
+ =============================================================================== \r
+ This section provides functions allowing to configure the I2C DMA channels \r
+ requests.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C DMA requests.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR2 |= I2C_CR2_DMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Specifies that the next DMA transfer is the last one.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA last transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Next DMA transfer is the last transfer */\r
+ I2Cx->CR2 |= I2C_CR2_LAST;\r
+ }\r
+ else\r
+ {\r
+ /* Next DMA transfer is not the last transfer */\r
+ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Group5 Interrupts events and flags management functions\r
+ * @brief Interrupts, events and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts, events and flags management functions\r
+ =============================================================================== \r
+ This section provides functions allowing to configure the I2C Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+\r
+ ===============================================================================\r
+ I2C State Monitoring Functions \r
+ =============================================================================== \r
+ This I2C driver provides three different ways for I2C state monitoring\r
+ depending on the application requirements and constraints:\r
+ \r
+ \r
+ 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
+ -----------------------------------------------------------\r
+ It compares the status registers (SR1 and SR2) content to a given event\r
+ (can be the combination of one or more flags).\r
+ It returns SUCCESS if the current status includes the given flags \r
+ and returns ERROR if one or more flags are missing in the current status.\r
+\r
+ - When to use\r
+ - This function is suitable for most applications as well as for startup \r
+ activity since the events are fully described in the product reference \r
+ manual (RM0038).\r
+ - It is also suitable for users who need to define their own events.\r
+\r
+ - Limitations\r
+ - If an error occurs (ie. error flags are set besides to the monitored \r
+ flags), the I2C_CheckEvent() function may return SUCCESS despite \r
+ the communication hold or corrupted real state. \r
+ In this case, it is advised to use error interrupts to monitor \r
+ the error events and handle them in the interrupt IRQ handler.\r
+ \r
+ @note \r
+ For error management, it is advised to use the following functions:\r
+ - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
+ Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
+ - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
+ and/or I2C_GenerateStop() in order to clear the error flag and source \r
+ and return to correct communication status.\r
+ \r
+ \r
+ 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
+ -------------------------------------------------------------------- \r
+ Using the function I2C_GetLastEvent() which returns the image of both status \r
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ by 16 bits and concatenated to Status Register 1).\r
+\r
+ - When to use\r
+ - This function is suitable for the same applications above but it \r
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
+ function.\r
+ - The returned value could be compared to events already defined in \r
+ the library (stm32l1xx_i2c.h) or to custom values defined by user.\r
+ This function is suitable when multiple flags are monitored at the \r
+ same time.\r
+ - At the opposite of I2C_CheckEvent() function, this function allows \r
+ user to choose when an event is accepted (when all events flags are \r
+ set and no other flags are set or just when the needed flags are set \r
+ like I2C_CheckEvent() function.\r
+\r
+ - Limitations\r
+ - User may need to define his own events.\r
+ - Same remark concerning the error management is applicable for this \r
+ function if user decides to check only regular communication flags \r
+ (and ignores error flags).\r
+ \r
+ \r
+ 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
+ -----------------------------------------------------------------------\r
+ \r
+ Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ one single flag (ie. I2C_FLAG_RXNE ...). \r
+\r
+ - When to use\r
+ - This function could be used for specific applications or in debug \r
+ phase.\r
+ - It is suitable when only one flag checking is needed (most I2C \r
+ events are monitored through multiple flags).\r
+ - Limitations: \r
+ - When calling this function, the Status register is accessed. \r
+ Some flags are cleared when the status register is accessed. \r
+ So checking the status of one Flag, may clear other ones.\r
+ - Function may need to be called twice or more in order to monitor \r
+ one single event.\r
+ \r
+ For detailed description of Events, please refer to section I2C_Events in \r
+ stm32l1xx_i2c.h file.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Reads the specified I2C register and returns its value.\r
+ * @param I2C_Register: specifies the register to read.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Register_CR1: CR1 register.\r
+ * @arg I2C_Register_CR2: CR2 register.\r
+ * @arg I2C_Register_OAR1: OAR1 register.\r
+ * @arg I2C_Register_OAR2: OAR2 register.\r
+ * @arg I2C_Register_DR: DR register.\r
+ * @arg I2C_Register_SR1: SR1 register.\r
+ * @arg I2C_Register_SR2: SR2 register.\r
+ * @arg I2C_Register_CCR: CCR register.\r
+ * @arg I2C_Register_TRISE: TRISE register.\r
+ * @retval The value of the read register.\r
+ */\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ tmp = (uint32_t) I2Cx;\r
+ tmp += I2C_Register;\r
+\r
+ /* Return the selected register value */\r
+ return (*(__IO uint16_t *) tmp);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C interrupts.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_BUF: Buffer interrupt mask\r
+ * @arg I2C_IT_EVT: Event interrupt mask\r
+ * @arg I2C_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified I2C interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR2 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ ===============================================================================\r
+ 1. Basic state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the last I2Cx Event is equal to the one passed\r
+ * as parameter.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_EVENT: specifies the event to be checked. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 \r
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32l1xx_i2c.h file.\r
+ * \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Last event is equal to the I2C_EVENT\r
+ * - ERROR: Last event is different from the I2C_EVENT\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_EVENT(I2C_EVENT));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_MASK;\r
+\r
+ /* Check whether the last event contains the I2C_EVENT */\r
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ ===============================================================================\r
+ 2. Advanced state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Returns the last I2Cx Event.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32l1xx_i2c.h file.\r
+ * \r
+ * @retval The last event\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_MASK;\r
+\r
+ /* Return status */\r
+ return lastevent;\r
+}\r
+\r
+/**\r
+ ===============================================================================\r
+ 3. Flag-based state monitoring \r
+ =============================================================================== \r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C flag is set or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
+ * @arg I2C_FLAG_BUSY: Bus busy flag\r
+ * @arg I2C_FLAG_MSL: Master/Slave flag\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ __IO uint32_t i2creg = 0, i2cxbase = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
+\r
+ /* Get the I2Cx peripheral base address */\r
+ i2cxbase = (uint32_t)I2Cx;\r
+ \r
+ /* Read flag register index */\r
+ i2creg = I2C_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_FLAG &= FLAG_MASK;\r
+ \r
+ if(i2creg != 0)\r
+ {\r
+ /* Get the I2Cx SR1 register address */\r
+ i2cxbase += 0x14;\r
+ }\r
+ else\r
+ {\r
+ /* Flag in I2Cx SR2 Register */\r
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
+ /* Get the I2Cx SR2 register address */\r
+ i2cxbase += 0x18;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the I2C_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx's pending flags.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
+ * second byte of the address in DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
+ * register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_FLAG & FLAG_MASK;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C interrupt has occurred or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_IT_PECERR: PEC error in reception flag\r
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure flag\r
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error flag\r
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_IT_BTF: Byte transfer finished flag\r
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_IT_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_IT (SET or RESET).\r
+ */\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_IT(I2C_IT));\r
+\r
+ /* Check if the interrupt source is enabled or not */\r
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_IT &= FLAG_MASK;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx\92s interrupt pending bits.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure interrupt\r
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error interrupt\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
+ * byte of the address in I2C_DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_DR register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_IT & FLAG_MASK;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Independent watchdog (IWDG) peripheral: \r
+ * - Prescaler and Counter configuration\r
+ * - IWDG activation\r
+ * - Flag management\r
+ *\r
+ * @verbatim \r
+ * \r
+ * ===================================================================\r
+ * IWDG features\r
+ * ===================================================================\r
+ * \r
+ * The IWDG can be started by either software or hardware (configurable\r
+ * through option byte).\r
+ * \r
+ * The IWDG is clocked by its own dedicated low-speed clock (LSI) and\r
+ * thus stays active even if the main clock fails.\r
+ * Once the IWDG is started, the LSI is forced ON and cannot be disabled\r
+ * (LSI cannot be disabled too), and the counter starts counting down from \r
+ * the reset value of 0xFFF. When it reaches the end of count value (0x000)\r
+ * a system reset is generated.\r
+ * The IWDG counter should be reloaded at regular intervals to prevent\r
+ * an MCU reset.\r
+ * \r
+ * The IWDG is implemented in the VDD voltage domain that is still functional\r
+ * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY) \r
+ * \r
+ * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG\r
+ * reset occurs\r
+ * \r
+ * Min-max timeout value @37KHz (LSI): ~108us / ~28.3s\r
+ * The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx\r
+ * devices provide the capability to measure the LSI frequency (LSI clock\r
+ * connected internally to TIM10 CH1 input capture). The measured value\r
+ * can be used to have an IWDG timeout with an acceptable accuracy. \r
+ * For more information, please refer to the STM32L1xx Reference manual\r
+ * \r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable write access to IWDG_PR and IWDG_RLR registers using\r
+ * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function\r
+ * \r
+ * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function\r
+ * \r
+ * 3. Configure the IWDG counter value using IWDG_SetReload() function.\r
+ * This value will be loaded in the IWDG counter each time the counter\r
+ * is reloaded, then the IWDG will start counting down from this value.\r
+ * \r
+ * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used\r
+ * in software mode (no need to enable the LSI, it will be enabled\r
+ * by hardware)\r
+ * \r
+ * 5. Then the application program must reload the IWDG counter at regular\r
+ * intervals during normal operation to prevent an MCU reset, using\r
+ * IWDG_ReloadCounter() function. \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_iwdg.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG \r
+ * @brief IWDG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- IWDG registers bit mask ----------------------------*/\r
+/* KR register bit mask */\r
+#define KR_KEY_RELOAD ((uint16_t)0xAAAA)\r
+#define KR_KEY_ENABLE ((uint16_t)0xCCCC)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions\r
+ * @brief Prescaler and Counter configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Prescaler and Counter configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
+ * @retval None\r
+ */\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
+ IWDG->KR = IWDG_WriteAccess;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Prescaler value.\r
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
+ * @retval None\r
+ */\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
+ IWDG->PR = IWDG_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Reload value.\r
+ * @param Reload: specifies the IWDG Reload value.\r
+ * This parameter must be a number between 0 and 0x0FFF.\r
+ * @retval None\r
+ */\r
+void IWDG_SetReload(uint16_t Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_RELOAD(Reload));\r
+ IWDG->RLR = Reload;\r
+}\r
+\r
+/**\r
+ * @brief Reloads IWDG counter with value defined in the reload register\r
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = KR_KEY_RELOAD;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group2 IWDG activation function\r
+ * @brief IWDG activation function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ IWDG activation function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = KR_KEY_ENABLE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group3 Flag management function \r
+ * @brief Flag management function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Flag management function \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified IWDG flag is set or not.\r
+ * @param IWDG_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
+ * @retval The new state of IWDG_FLAG (SET or RESET).\r
+ */\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_lcd.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the LCD controller (LCD) peripheral: \r
+ * - Initialization and configuration\r
+ * - LCD RAM memory write\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * LCD Clock\r
+ * =================================================================== \r
+ * LCDCLK is the same as RTCCLK. \r
+ * To configure the RTCCLK/LCDCLK, proceed as follows:\r
+ * - Enable the Power Controller (PWR) APB1 interface clock using the\r
+ * RCC_APB1PeriphClockCmd() function.\r
+ * - Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
+ * - Select the RTC clock source using the RCC_RTCCLKConfig() function. \r
+ * \r
+ * The frequency generator allows you to achieve various LCD frame rates \r
+ * starting from an LCD input clock frequency (LCDCLK) which can vary \r
+ * from 32 kHz up to 1 MHz.\r
+ * \r
+ * =================================================================== \r
+ * LCD and low power modes\r
+ * =================================================================== \r
+ * The LCD still active during STOP mode.\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable LCD clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function\r
+ * \r
+ * 2. Configure the LCD prescaler, divider, duty, bias and voltage source\r
+ * using LCD_Init() function \r
+ * \r
+ * 3. Optionally you can enable/configure:\r
+ * - LCD High Drive using the LCD_HighDriveCmd() function\r
+ * - LCD High Drive using the LCD_MuxSegmentCmd() function \r
+ * - LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function\r
+ * - LCD Dead Time using the LCD_DeadTimeConfig() function \r
+ * - The LCD Blink mode and frequency using the LCD_BlinkConfig() function\r
+ * - The LCD Contrast using the LCD_ContrastConfig() function \r
+ *\r
+ * 4. Call the LCD_WaitForSynchro() function to wait for LCD_FCR register\r
+ * synchronization.\r
+ * \r
+ * 5. Call the LCD_Cmd() to enable the LCD controller\r
+ * \r
+ * 6. Wait until the LCD Controller status is enabled and the step-up\r
+ * converter is ready using the LCD_GetFlagStatus() and\r
+ * LCD_FLAG_ENS and LCD_FLAG_RDY flags. \r
+ * \r
+ * 7. Write to the LCD RAM memory using the LCD_Write() function.\r
+ * \r
+ * 8. Request an update display using the LCD_UpdateDisplayRequest()\r
+ * function.\r
+ * \r
+ * 9. Wait until the update display is finished by checking the UDD\r
+ * flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD)\r
+ * \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_lcd.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD \r
+ * @brief LCD driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ LCD registers bit address in the alias region --------------- */\r
+#define LCD_OFFSET (LCD_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of LCDEN bit */\r
+#define CR_OFFSET (LCD_OFFSET + 0x00)\r
+#define LCDEN_BitNumber 0x00\r
+#define CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))\r
+\r
+/* Alias word address of MUX_SEG bit */\r
+#define MUX_SEG_BitNumber 0x07\r
+#define CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))\r
+\r
+\r
+/* --- FCR Register ---*/\r
+\r
+/* Alias word address of HD bit */\r
+#define FCR_OFFSET (LCD_OFFSET + 0x04)\r
+#define HD_BitNumber 0x00\r
+#define FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))\r
+\r
+/* --- SR Register ---*/\r
+\r
+/* Alias word address of UDR bit */\r
+#define SR_OFFSET (LCD_OFFSET + 0x08)\r
+#define UDR_BitNumber 0x02\r
+#define SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))\r
+\r
+#define FCR_MASK ((uint32_t)0xFC03FFFF) /* LCD FCR Mask */\r
+#define CR_MASK ((uint32_t)0xFFFFFF81) /* LCD CR Mask */\r
+#define PON_MASK ((uint32_t)0xFFFFFF8F) /* LCD PON Mask */\r
+#define DEAD_MASK ((uint32_t)0xFFFFFC7F) /* LCD DEAD Mask */\r
+#define BLINK_MASK ((uint32_t)0xFFFC1FFF) /* LCD BLINK Mask */\r
+#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF) /* LCD CONTRAST Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup LCD_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LCD_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the LCD peripheral registers to their default reset \r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_DeInit(void)\r
+{\r
+ /* Enable LCD reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE);\r
+ /* Release LCD from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LCD peripheral according to the specified parameters \r
+ * in the LCD_InitStruct.\r
+ * @note This function can be used only when the LCD is disabled. \r
+ * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains \r
+ * the configuration information for the specified LCD peripheral.\r
+ * @retval None\r
+ */\r
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler));\r
+ assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider));\r
+ assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty));\r
+ assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias)); \r
+ assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource));\r
+\r
+ LCD->FCR &= (uint32_t)FCR_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider);\r
+\r
+ LCD_WaitForSynchro();\r
+\r
+ LCD->CR &= (uint32_t)CR_MASK;\r
+ LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \\r
+ LCD_InitStruct->LCD_VoltageSource);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Fills each LCD_InitStruct member with its default value.\r
+ * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct)\r
+{\r
+/*--------------- Reset LCD init structure parameters values -----------------*/\r
+ LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */\r
+ \r
+ LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */\r
+ \r
+ LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */\r
+ \r
+ LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */\r
+ \r
+ LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the LCD Controller.\r
+ * @param NewState: new state of the LCD peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_Cmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain.\r
+ * This function must be called after any write operation to LCD_FCR register.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_WaitForSynchro(void)\r
+{\r
+ /* Loop until FCRSF flag is set */\r
+ while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the low resistance divider. Displays with high \r
+ * internal resistance may need a longer drive time to achieve \r
+ * satisfactory contrast. This function is useful in this case if some \r
+ * additional power consumption can be tolerated.\r
+ * @note When this mode is enabled, the PulseOn Duration (PON) have to be \r
+ * programmed to 1/CK_PS (LCD_PulseOnDuration_1). \r
+ * @param NewState: new state of the low resistance divider.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_HighDriveCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Mux Segment.\r
+ * @note This function can be used only when the LCD is disabled. \r
+ * @param NewState: new state of the Mux Segment.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_MuxSegmentCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD pulses on duration.\r
+ * @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of \r
+ * CK_PS (prescaled LCD clock period) pulses.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_PulseOnDuration_0: 0 pulse\r
+ * @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS\r
+ * @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS\r
+ * @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS\r
+ * @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS\r
+ * @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS\r
+ * @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS\r
+ * @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS\r
+ * @retval None\r
+ */\r
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration));\r
+\r
+ LCD->FCR &= (uint32_t)PON_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_PulseOnDuration);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD dead time.\r
+ * @param LCD_DeadTime: specifies the LCD dead time.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_DeadTime_0: No dead Time\r
+ * @arg LCD_DeadTime_1: One Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_2: Two Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_3: Three Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_4: Four Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_5: Five Phase between different couple of Frame\r
+ * @arg LCD_DeadTime_6: Six Phase between different couple of Frame \r
+ * @arg LCD_DeadTime_7: Seven Phase between different couple of Frame\r
+ * @retval None\r
+ */\r
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));\r
+\r
+ LCD->FCR &= (uint32_t)DEAD_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_DeadTime);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD Blink mode and Blink frequency.\r
+ * @param LCD_BlinkMode: specifies the LCD blink mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_BlinkMode_Off: Blink disabled\r
+ * @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)\r
+ * @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8 \r
+ * pixels according to the programmed duty)\r
+ * @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM \r
+ * (all pixels)\r
+ * @param LCD_BlinkFrequency: specifies the LCD blink frequency.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8\r
+ * @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16\r
+ * @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32\r
+ * @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64 \r
+ * @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128\r
+ * @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256\r
+ * @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512\r
+ * @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024\r
+ * @retval None\r
+ */\r
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));\r
+ assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));\r
+ \r
+ LCD->FCR &= (uint32_t)BLINK_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency);\r
+}\r
+\r
+/**\r
+ * @brief Configures the LCD Contrast.\r
+ * @param LCD_Contrast: specifies the LCD Contrast.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V\r
+ * @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V\r
+ * @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V\r
+ * @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V\r
+ * @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V\r
+ * @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V\r
+ * @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V\r
+ * @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V\r
+ * @retval None\r
+ */\r
+void LCD_ContrastConfig(uint32_t LCD_Contrast)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_CONTRAST(LCD_Contrast));\r
+\r
+ LCD->FCR &= (uint32_t)CONTRAST_MASK;\r
+ LCD->FCR |= (uint32_t)(LCD_Contrast);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Group2 LCD RAM memory write functions\r
+ * @brief LCD RAM memory write functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ LCD RAM memory write functions\r
+ =============================================================================== \r
+\r
+ Using its double buffer memory the LCD controller ensures the coherency of the \r
+ displayed information without having to use interrupts to control LCD_RAM \r
+ modification.\r
+ The application software can access the first buffer level (LCD_RAM) through \r
+ the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag in \r
+ the LCD_SR register using the LCD_UpdateDisplayRequest() function.\r
+ This UDR flag (update display request) requests the updated information to be \r
+ moved into the second buffer level (LCD_DISPLAY).\r
+ This operation is done synchronously with the frame (at the beginning of the \r
+ next frame), until the update is completed, the LCD_RAM is write protected and \r
+ the UDR flag stays high.\r
+ Once the update is completed another flag (UDD - Update Display Done) is set and\r
+ generates an interrupt if the UDDIE bit in the LCD_FCR register is set.\r
+ The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one \r
+ even frame.\r
+ The update will not occur (UDR = 1 and UDD = 0) until the display is \r
+ enabled (LCDEN = 1).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a word in the specific LCD RAM.\r
+ * @param LCD_RAMRegister: specifies the LCD Contrast.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_RAMRegister_0: LCD RAM Register 0\r
+ * @arg LCD_RAMRegister_1: LCD RAM Register 1\r
+ * @arg LCD_RAMRegister_2: LCD RAM Register 2\r
+ * @arg LCD_RAMRegister_3: LCD RAM Register 3\r
+ * @arg LCD_RAMRegister_4: LCD RAM Register 4\r
+ * @arg LCD_RAMRegister_5: LCD RAM Register 5\r
+ * @arg LCD_RAMRegister_6: LCD RAM Register 6 \r
+ * @arg LCD_RAMRegister_7: LCD RAM Register 7 \r
+ * @arg LCD_RAMRegister_8: LCD RAM Register 8\r
+ * @arg LCD_RAMRegister_9: LCD RAM Register 9\r
+ * @arg LCD_RAMRegister_10: LCD RAM Register 10\r
+ * @arg LCD_RAMRegister_11: LCD RAM Register 11\r
+ * @arg LCD_RAMRegister_12: LCD RAM Register 12 \r
+ * @arg LCD_RAMRegister_13: LCD RAM Register 13 \r
+ * @arg LCD_RAMRegister_14: LCD RAM Register 14 \r
+ * @arg LCD_RAMRegister_15: LCD RAM Register 15 \r
+ * @param LCD_Data: specifies LCD Data Value to be written.\r
+ * @retval None\r
+ */\r
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));\r
+\r
+ /* Copy data bytes to RAM register */\r
+ LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Update Display Request.\r
+ * @note Each time software modifies the LCD_RAM it must set the UDR bit to \r
+ * transfer the updated data to the second level buffer. \r
+ * The UDR bit stays set until the end of the update and during this \r
+ * time the LCD_RAM is write protected. \r
+ * @note When the display is disabled, the update is performed for all \r
+ * LCD_DISPLAY locations.\r
+ * When the display is enabled, the update is performed only for locations \r
+ * for which commons are active (depending on DUTY). For example if \r
+ * DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LCD_UpdateDisplayRequest(void)\r
+{\r
+ *(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LCD_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified LCD interrupts.\r
+ * @param LCD_IT: specifies the LCD interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt\r
+ * @param NewState: new state of the specified LCD interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_IT(LCD_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ LCD->FCR |= LCD_IT;\r
+ }\r
+ else\r
+ {\r
+ LCD->FCR &= (uint32_t)~LCD_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified LCD flag is set or not.\r
+ * @param LCD_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.\r
+ * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR \r
+ * goes from 0 to 1. On deactivation it reflects the real status of \r
+ * LCD so it becomes 0 at the end of the last displayed frame. \r
+ * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at \r
+ * the beginning of a new frame, at the same time as the display data is \r
+ * updated.\r
+ * @arg LCD_FLAG_UDR: Update Display Request flag.\r
+ * @arg LCD_FLAG_UDD: Update Display Done flag. \r
+ * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status \r
+ * of the step-up converter.\r
+ * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. \r
+ * This flag is set by hardware each time the LCD_FCR register is updated \r
+ * in the LCDCLK domain. \r
+ * @retval The new state of LCD_FLAG (SET or RESET).\r
+ */\r
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_GET_FLAG(LCD_FLAG));\r
+ \r
+ if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the LCD's pending flags.\r
+ * @param LCD_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_FLAG_SOF: Start of Frame Interrupt\r
+ * @arg LCD_FLAG_UDD: Update Display Done Interrupt\r
+ * @retval None\r
+ */\r
+void LCD_ClearFlag(uint32_t LCD_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG));\r
+ \r
+ /* Clear the corresponding LCD flag */\r
+ LCD->CLR = (uint32_t)LCD_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occurred or not.\r
+ * @param RTC_IT: specifies the RTC interrupts sources to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt.\r
+ * @note If the device is in STOP mode (PCLK not provided) UDD will not \r
+ * generate an interrupt even if UDDIE = 1. \r
+ * If the display is not enabled the UDD interrupt will never occur. \r
+ * @retval The new state of the LCD_IT (SET or RESET).\r
+ */\r
+ITStatus LCD_GetITStatus(uint32_t LCD_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_GET_IT(LCD_IT));\r
+ \r
+ if ((LCD->SR & LCD_IT) != (uint16_t)RESET) \r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the LCD's interrupt pending bits.\r
+ * @param LCD_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LCD_IT_SOF: Start of Frame Interrupt\r
+ * @arg LCD_IT_UDD: Update Display Done Interrupt\r
+ * @retval None\r
+ */\r
+void LCD_ClearITPendingBit(uint32_t LCD_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LCD_IT(LCD_IT));\r
+ \r
+ /* Clear the corresponding LCD pending bit */\r
+ LCD->CLR = (uint32_t)LCD_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral: \r
+ * - RTC Domain Access\r
+ * - PVD configuration\r
+ * - WakeUp pins configuration\r
+ * - Ultra Low Power mode configuration\r
+ * - Voltage Scaling configuration\r
+ * - Low Power modes configuration\r
+ * - Flags management\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR \r
+ * @brief PWR driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber 0x08\r
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber 0x04\r
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* Alias word address of ULP bit */\r
+#define ULP_BitNumber 0x09\r
+#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))\r
+\r
+/* Alias word address of FWU bit */\r
+#define FWU_BitNumber 0x0A\r
+#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber 0x08\r
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
+#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Group1 RTC Domain Access function \r
+ * @brief RTC Domain Access function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ RTC Domain Access function \r
+ =============================================================================== \r
+\r
+ After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup \r
+ registers) are protected against possible stray write accesses.\r
+ To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @note Before calling this function, the VOS[1:0] bits should be configured \r
+ * to "10" and the system frequency has to be configured accordingly. \r
+ * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()\r
+ * function. \r
+ * @note ULP and FWU bits are not reset by this function. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables access to the RTC and backup registers.\r
+ * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the \r
+ * RTC Domain Access should be kept enabled.\r
+ * @param NewState: new state of the access to the RTC and backup registers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_RTCAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group2 PVD configuration functions\r
+ * @brief PVD configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ PVD configuration functions\r
+ =============================================================================== \r
+\r
+ - The PVD is used to monitor the VDD power supply by comparing it to a threshold\r
+ selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ - The PVD can use an external input analog voltage (PVD_IN) which is compared \r
+ internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode \r
+ when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).\r
+ - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the \r
+ PVD threshold. This event is internally connected to the EXTI line16\r
+ and can generate an interrupt if enabled through the EXTI registers.\r
+ - The PVD is stopped in Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param PWR_PVDLevel: specifies the PVD detection level\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V\r
+ * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V\r
+ * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V\r
+ * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V\r
+ * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V\r
+ * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V\r
+ * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V\r
+ * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)\r
+ * @retval None\r
+ */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+ \r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_MASK;\r
+ \r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Power Voltage Detector(PVD).\r
+ * @param NewState: new state of the PVD.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group3 WakeUp pins configuration functions\r
+ * @brief WakeUp pins configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ WakeUp pins configuration functions\r
+ =============================================================================== \r
+\r
+ - WakeUp pins are used to wakeup the system from Standby mode. These pins are \r
+ forced in input pull down configuration and are active on rising edges.\r
+ - There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and\r
+ WakeUp Pin 3 on PE.06.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the WakeUp Pin functionality.\r
+ * @param PWR_WakeUpPin: specifies the WakeUpPin.\r
+ * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.\r
+ * @param NewState: new state of the WakeUp Pin functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
+ \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ tmp = CSR_EWUP_BB + PWR_WakeUpPin;\r
+ \r
+ *(__IO uint32_t *) (tmp) = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions\r
+ * @brief Ultra Low Power mode configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Ultra Low Power mode configuration functions\r
+ =============================================================================== \r
+\r
+ - The internal voltage reference consumption is not negligible, in particular \r
+ in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()\r
+ function (ULP bit (Ultra low power) in the PWR_CR register) to disable the \r
+ internal voltage reference. However, in this case, when exiting from the \r
+ Stop/Standby mode, the functions managed through the internal voltage reference \r
+ are not reliable during the internal voltage reference startup time (up to 3 ms).\r
+ To reduce the wakeup time, the device can exit from Stop/Standby mode without \r
+ waiting for the internal voltage reference startup time. This is performed \r
+ by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast\r
+ wakeup) in the PWR_CR register) before entering Stop/Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.\r
+ * @param NewState: new state of the Fast WakeUp functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_FastWakeUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Ultra Low Power mode.\r
+ * @param NewState: new state of the Ultra Low Power mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group5 Voltage Scaling configuration functions\r
+ * @brief Voltage Scaling configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Voltage Scaling configuration functions\r
+ =============================================================================== \r
+\r
+ - The dynamic voltage scaling is a power management technique which consists in \r
+ increasing or decreasing the voltage used for the digital peripherals (VCORE), \r
+ according to the circumstances.\r
+ \r
+ Depending on the device voltage range, the maximum frequency and FLASH wait\r
+ state should be adapted accordingly:\r
+ \r
+ +------------------------------------------------------------------+ \r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------| \r
+ | (Latency) | voltage range | voltage range | \r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------|\r
+ | | Range 3 | Range 2 | Range 1 |\r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |---------------- |----------------|---------------|---------------| \r
+ | 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |-----------------|----------------|---------------|---------------| \r
+ | 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
+ |-----------------|----------------|---------------|---------------| \r
+ | CPU Performance | Low | Medium | High |\r
+ |-----__----------|----------------|---------------|---------------| \r
+ |Power Performance| High | Medium | Low | \r
+ +------------------------------------------------------------------+ \r
+\r
+ - To modify the Product voltage range, user application has to:\r
+ - Check VDD to identify which ranges are allowed (see table above)\r
+ - Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus() \r
+ function and wait until it is reset.\r
+ - Configure the Voltage range using the PWR_VoltageScalingConfig() function.\r
+\r
+ - When VCORE range 1 is selected and VDD drops below 2.0 V, the application must\r
+ reconfigure the system:\r
+ - Detect that VDD drops below 2.0 V using the PVD Level 1\r
+ - Adapt the clock frequency to the voltage range that will be selected at next step\r
+ - Select the required voltage range\r
+ - When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system\r
+ reconfiguration is required.\r
+ \r
+ - When VDD is above 2.0 V, any of the 3 voltage ranges can be selected\r
+ - When the voltage range is above the targeted voltage range (e.g. from range \r
+ 1 to 2):\r
+ - Adapt the clock frequency to the lower voltage range that will be selected \r
+ at next step.\r
+ - Select the required voltage range.\r
+ - When the voltage range is below the targeted voltage range (e.g. from range \r
+ 3 to 1):\r
+ - Select the required voltage range.\r
+ - Tune the clock frequency if needed.\r
+ \r
+ - When VDD is below 2.0 V, only range 2 and 3 can be selected:\r
+ - From range 2 to range 3\r
+ - Adapt the clock frequency to voltage range 3.\r
+ - Select voltage range 3.\r
+ - From range 3 to range 2\r
+ - Select the voltage range 2.\r
+ - Tune the clock frequency if needed.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage scaling range.\r
+ * @note During voltage scaling configuration, the system clock is stopped \r
+ * until the regulator is stabilized (VOSF = 0). This must be taken \r
+ * into account during application developement, in case a critical \r
+ * reaction time to interrupt is needed, and depending on peripheral \r
+ * used (timer, communication,...).\r
+ * \r
+ * @param PWR_VoltageScaling: specifies the voltage scaling range.\r
+ * This parameter can be:\r
+ * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V)\r
+ * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V)\r
+ * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V) \r
+ * @retval None\r
+ */\r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));\r
+ \r
+ tmp = PWR->CR;\r
+\r
+ tmp &= CR_VOS_MASK;\r
+ tmp |= PWR_VoltageScaling;\r
+ \r
+ PWR->CR = tmp & 0xFFFFFFF3;\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group6 Low Power modes configuration functions\r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Low Power modes configuration functions\r
+ =============================================================================== \r
+\r
+ The devices feature five low-power modes:\r
+ - Low power run mode: regulator in low power mode, limited clock frequency, \r
+ limited number of peripherals running.\r
+ - Sleep mode: Cortex-M3 core stopped, peripherals kept running.\r
+ - Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, \r
+ limited number of peripherals running, regulator in low power mode.\r
+ - Stop mode: all clocks are stopped, regulator running, regulator in low power mode\r
+ - Standby mode: VCORE domain powered off\r
+ \r
+ Low power run mode (LP run)\r
+ ===========================\r
+ - Entry:\r
+ - Decrease the system frequency.\r
+ - The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()\r
+ function.\r
+ - Exit:\r
+ - The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()\r
+ function.\r
+ - Increase the system frequency if needed.\r
+\r
+ Sleep mode\r
+ ===========\r
+ - Entry:\r
+ - The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,) \r
+ function with regulator ON.\r
+ - Exit:\r
+ - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ Low power sleep mode (LP sleep)\r
+ ===============================\r
+ - Entry:\r
+ - The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()\r
+ function.\r
+ - Decrease the system frequency.\r
+ - The regulator is forced in low power mode and the WFI or WFE instructions\r
+ are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function \r
+ with regulator in LowPower.\r
+ - Exit:\r
+ - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep LP mode.\r
+\r
+ Stop mode\r
+ ==========\r
+ In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,\r
+ the HSI and the HSE RC oscillators are disabled. Internal SRAM and register \r
+ contents are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering the Stop mode. They can be switched \r
+ on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()\r
+ function. \r
+ \r
+ - Entry:\r
+ - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) \r
+ function with regulator in LowPower or with Regulator ON.\r
+ - Exit:\r
+ - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+ \r
+ Standby mode\r
+ ============\r
+ The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. \r
+ The VCORE domain is consequently powered off. The PLL, the MSI, the HSI \r
+ oscillator and the HSE oscillator are also switched off. SRAM and register \r
+ contents are lost except for the RTC registers, RTC backup registers and \r
+ Standby circuitry.\r
+ \r
+ The voltage regulator is OFF.\r
+ \r
+ To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature\r
+ sensor can be switched off before entering the Standby mode. They can be switched \r
+ on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()\r
+ function. \r
+ \r
+ - Entry:\r
+ - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.\r
+ - Exit:\r
+ - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset. \r
+\r
+ Auto-wakeup (AWU) from low-power mode\r
+ =====================================\r
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
+ Wakeup event, a tamper event, a time-stamp event, or a comparator event, \r
+ without depending on an external interrupt (Auto-wakeup mode).\r
+\r
+ - RTC auto-wakeup (AWU) from the Stop mode\r
+ ----------------------------------------\r
+ \r
+ - To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r
+ - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ - To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ - Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function\r
+ - Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+ - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:\r
+ - Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
+ RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ - RTC auto-wakeup (AWU) from the Standby mode\r
+ -------------------------------------------\r
+ - To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r
+ - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ - To wake up from the Standby mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function\r
+ - Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+ - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:\r
+ - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
+ - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
+ RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ - Comparator auto-wakeup (AWU) from the Stop mode\r
+ -----------------------------------------------\r
+ - To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup\r
+ event, it is necessary to:\r
+ - Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 \r
+ to be sensitive to to the selected edges (falling, rising or falling \r
+ and rising) (Interrupt or Event modes) using the EXTI_Init() function.\r
+ - Configure the comparator to generate the event.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enters/Exits the Low Power Run mode.\r
+ * @note Low power run mode can only be entered when VCORE is in range 2.\r
+ * In addition, the dynamic voltage scaling must not be used when Low \r
+ * power run mode is selected. Only Stop and Sleep modes with regulator \r
+ * configured in Low power mode is allowed when Low power run mode is \r
+ * selected. \r
+ * @note In Low power run mode, all I/O pins keep the same state as in Run mode. \r
+ * @param NewState: new state of the Low Power Run mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ PWR->CR |= PWR_CR_LPSDSR;\r
+ PWR->CR |= PWR_CR_LPRUN; \r
+ }\r
+ else\r
+ {\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); \r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode. \r
+ * @param PWR_Regulator: specifies the regulator state in Sleep mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: Sleep mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode\r
+ * @note Low power sleep mode can only be entered when VCORE is in range 2.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Low power sleep mode.\r
+ * \r
+ * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+\r
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
+ \r
+ /* Select the regulator state in Sleep mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
+ \r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters STOP mode.\r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the MSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced. \r
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
+}\r
+\r
+/**\r
+ * @brief Enters STANDBY mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * - Reset pad (still available) \r
+ * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, \r
+ * time-stamp, RTC Alarm out, or RTC clock calibration out.\r
+ * - WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wakeup flag */\r
+ PWR->CR |= PWR_CR_CWUF;\r
+ \r
+ /* Select STANDBY mode */\r
+ PWR->CR |= PWR_CR_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM )\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group7 Flags management functions\r
+ * @brief Flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified PWR flag is set or not.\r
+ * @param PWR_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
+ * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), \r
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
+ * resumed from StandBy mode. \r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
+ * by the PWR_PVDCmd() function.\r
+ * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This \r
+ * flag indicates the state of the internal voltage reference, VREFINT.\r
+ * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for \r
+ * the internal regulator to be ready after the voltage range is changed.\r
+ * The VOSF flag indicates that the regulator has reached the voltage level \r
+ * defined with bits VOS[1:0] of PWR_CR register.\r
+ * @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware \r
+ * when the MCU is in Low power run mode.\r
+ * When the MCU exits from Low power run mode, this flag stays SET until \r
+ * the regulator is ready in main mode. A polling on this flag is \r
+ * recommended to wait for the regulator main mode. \r
+ * This flag is RESET by hardware when the regulator is ready. \r
+ * @retval The new state of PWR_FLAG (SET or RESET).\r
+ */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+ \r
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the PWR's pending flags.\r
+ * @param PWR_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @retval None\r
+ */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+ \r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Reset and clock control (RCC) peripheral: \r
+ * - Internal/external clocks, PLL, CSS and MCO configuration\r
+ * - System, AHB and APB busses clocks configuration\r
+ * - Peripheral clocks configuration\r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * RCC specific features\r
+ * ===================================================================\r
+ * \r
+ * After reset the device is running from MSI (2 MHz) with Flash 0 WS, \r
+ * all peripherals are off except internal SRAM, Flash and JTAG.\r
+ * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ * all peripherals mapped on these busses are running at MSI speed.\r
+ * - The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ * - All GPIOs are in input floating state, except the JTAG pins which\r
+ * are assigned to be used for debug purpose.\r
+ * \r
+ * Once the device started from reset, the user application has to: \r
+ * - Configure the clock source to be used to drive the System clock\r
+ * (if the application needs higher frequency/performance)\r
+ * - Configure the System clock frequency and Flash settings \r
+ * - Configure the AHB and APB busses prescalers\r
+ * - Enable the clock for the peripheral(s) to be used\r
+ * - Configure the clock source(s) for peripherals whose clocks are not\r
+ * derived from the System clock (ADC, RTC/LCD and IWDG) \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of MSION bit */\r
+#define MSION_BitNumber 0x08\r
+#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x1C\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x34)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define RTCEN_BitNumber 0x16\r
+#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of RTCRST bit */\r
+#define RTCRST_BitNumber 0x17\r
+#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))\r
+\r
+\r
+/* ---------------------- RCC registers mask -------------------------------- */\r
+/* RCC Flag Mask */\r
+#define FLAG_MASK ((uint8_t)0x1F)\r
+\r
+/* CR register byte 3 (Bits[23:16]) base address */\r
+#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)\r
+\r
+/* ICSCR register byte 4 (Bits[31:24]) base address */\r
+#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)\r
+\r
+/* CFGR register byte 3 (Bits[23:16]) base address */\r
+#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)\r
+\r
+/* CSR register byte 2 (Bits[15:8]) base address */\r
+#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Internal/external clocks, PLL, CSS and MCO configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the internal/external clocks,\r
+ PLL, CSS and MCO.\r
+ \r
+ 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+\r
+ 2. MSI (multi-speed internal), multispeed low power RC (65.536 KHz to 4.194 MHz)\r
+ MHz used as System clock source.\r
+\r
+ 3. LSI (low-speed internal), 37 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ 4. HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ 5. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
+\r
+ 6. PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).\r
+\r
+ 7. CSS (Clock security system), once enable and if a HSE clock failure occurs \r
+ (HSE used directly or through PLL as System clock source), the System clock\r
+ is automatically switched to MSI and an interrupt is generated if enabled. \r
+ The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) \r
+ exception vector. \r
+\r
+ 8. MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, HSE, PLL,\r
+ LSI or LSE clock (through a configurable prescaler) on PA8 pin.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note - The default reset state of the clock configuration is given below:\r
+ * - MSI ON and used as system clock source (MSI range is not modified\r
+ * by this function, it keep the value configured by user application)\r
+ * - HSI, HSE and PLL OFF\r
+ * - AHB, APB1 and APB2 prescaler set to 1.\r
+ * - CSS and MCO OFF\r
+ * - All interrupts disabled\r
+ * - However, this function doesn't modify the configuration of the\r
+ * - Peripheral clocks\r
+ * - LSI, LSE and RTC clocks \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ \r
+ /* Set MSION bit */\r
+ RCC->CR |= (uint32_t)0x00000100;\r
+\r
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+ \r
+ /* Reset HSION, HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note - After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * - HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * - The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint8_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
+\r
+ /* Set the new HSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r
+ * this flag is set, otherwise returns ERROR if the timeout is reached \r
+ * and this flag is not set. The timeout value is defined by the constant\r
+ * HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending\r
+ * on the HSE crystal used in your application. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus HSEStatus = RESET;\r
+ \r
+ /* Wait till HSE is ready and if timeout is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+ \r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal MSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the MSI.\r
+ * @param MSICalibrationValue: specifies the MSI calibration trimming value.\r
+ * This parameter must be a number between 0 and 0xFF.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
+{\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
+\r
+ *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; \r
+}\r
+\r
+/**\r
+ * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.\r
+ * @note - After restart from Reset or wakeup from STANDBY, the MSI clock is \r
+ * around 2.097 MHz. The MSI clock does not change after wake-up from\r
+ * STOP mode.\r
+ * - The MSI clock range can be modified on the fly. \r
+ * @param RCC_MSIRange: specifies the MSI Clock range.\r
+ * This parameter must be one of the following values:\r
+ * @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz\r
+ * @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz\r
+ * @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz\r
+ * @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz\r
+ * @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz\r
+ * @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
+ * @arg RCC_MSIRange_6: MSI clock is around \r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
+ \r
+ tmpreg = RCC->ICSCR;\r
+ \r
+ /* Clear MSIRANGE[2:0] bits */\r
+ tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
+ \r
+ /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
+ tmpreg |= (uint32_t)RCC_MSIRange;\r
+\r
+ /* Store the new value */\r
+ RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Multi Speed oscillator (MSI).\r
+ * @note - The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled). \r
+ * - MSI can not be stopped if it is used as system clock source.\r
+ * In this case, you have to select another source of the system\r
+ * clock then stop the MSI. \r
+ * - After enabling the MSI, the application software should wait on\r
+ * MSIRDY flag to be set indicating that MSI clock is stable and can\r
+ * be used as system clock source. \r
+ * @param NewState: new state of the MSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_MSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the HSI.\r
+ * @param HSICalibrationValue: specifies the HSI calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
+ \r
+ tmpreg = RCC->ICSCR;\r
+ \r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= ~RCC_ICSCR_HSITRIM;\r
+ \r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
+\r
+ /* Store the new value */\r
+ RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note - After enabling the HSI, the application software should wait on \r
+ * HSIRDY flag to be set indicating that HSI clock is stable and can\r
+ * be used to clock the PLL and/or system clock.\r
+ * - HSI can not be stopped if it is used directly or through the PLL\r
+ * as system clock. In this case, you have to select another source \r
+ * of the system clock then stop the HSI.\r
+ * - The HSI is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @param NewState: new state of the HSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @note - As the LSE is in the RTC domain and write access is denied to this\r
+ * domain after reset, you have to enable write access using \r
+ * PWR_RTCAccessCmd(ENABLE) function before to configure the LSE\r
+ * (to be done once after reset). \r
+ * - After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+ \r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
+\r
+ /* Set the new LSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI). \r
+ * @note - After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * - LSI can not be disabled if the IWDG is running. \r
+ * @param NewState: new state of the LSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL clock source and multiplication factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ * \r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source\r
+ * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source\r
+ * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as\r
+ * PLL source).\r
+ * \r
+ * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock\r
+ * This parameter can be:\r
+ * @arg RCC_PLLMul_3: PLL clock source multiplied by 3\r
+ * @arg RCC_PLLMul_4: PLL clock source multiplied by 4\r
+ * @arg RCC_PLLMul_6: PLL clock source multiplied by 6\r
+ * @arg RCC_PLLMul_8: PLL clock source multiplied by 8\r
+ * @arg RCC_PLLMul_12: PLL clock source multiplied by 12\r
+ * @arg RCC_PLLMul_16: PLL clock source multiplied by 16 \r
+ * @arg RCC_PLLMul_24: PLL clock source multiplied by 24\r
+ * @arg RCC_PLLMul_32: PLL clock source multiplied by 32\r
+ * @arg RCC_PLLMul_48: PLL clock source multiplied by 48\r
+ * @note The application software must set correctly the PLL multiplication\r
+ * factor to avoid exceeding\r
+ * - 96 MHz as PLLVCO when the product is in range 1\r
+ * - 48 MHz as PLLVCO when the product is in range 2\r
+ * - 24 MHz when the product is in range 3\r
+ * @note When using the USB the PLLVCO should be 96MHz\r
+ * \r
+ * @param RCC_PLLDiv: specifies the PLL division factor.\r
+ * This parameter can be:\r
+ * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 \r
+ * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 \r
+ * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 \r
+ * @note The application software must set correctly the output division to avoid\r
+ * exceeding 32 MHz as SYSCLK.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+ assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
+ \r
+ *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLL.\r
+ * @note - After enabling the PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * - The PLL can not be disabled if it is used as system clock source\r
+ * - The PLL is disabled by hardware when entering STOP and STANDBY modes. \r
+ * @param NewState: new state of the PLL.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to \r
+ * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. \r
+ * @param NewState: new state of the Clock Security System.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin (PA8).\r
+ * @note PA8 should be configured in alternate function mode. \r
+ * @param RCC_MCOSource: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCOSource_NoClock: No clock selected\r
+ * @arg RCC_MCOSource_SYSCLK: System clock selected\r
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCOSource_MSI: MSI oscillator clock selected \r
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
+ * @arg RCC_MCOSource_LSI: LSI clock selected\r
+ * @arg RCC_MCOSource_LSE: LSE clock selected \r
+ * @param RCC_MCODiv: specifies the MCO prescaler.\r
+ * This parameter can be one of the following values: \r
+ * @arg RCC_MCODiv_1: no division applied to MCO clock \r
+ * @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
+ * @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
+ * @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
+ * @arg RCC_MCODiv_16: division by 16 applied to MCO clock \r
+ * @retval None\r
+ */\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
+ assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
+ \r
+ /* Select MCO clock source and prescaler */\r
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r
+ * @brief System, AHB and APB busses clocks configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ System, AHB and APB busses clocks configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the System, AHB, APB1 and \r
+ APB2 busses clocks.\r
+ \r
+ 1. Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable prescaler\r
+ and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).\r
+ APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through \r
+ configurable prescalers and used to clock the peripherals mapped on these busses.\r
+ You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. \r
+\r
+Note: All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+==== - The USB 48 MHz clock which is derived from the PLL VCO clock.\r
+ - The ADC clock which is always the HSI clock. A divider by 1, 2 or 4 allows\r
+ to adapt the clock frequency to the device operating conditions. \r
+ - The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
+ divided by a programmable prescaler).\r
+ The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD\r
+ clock frequency.\r
+ - IWDG clock which is always the LSI clock.\r
+ \r
+ 2. The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.\r
+ Depending on the device voltage range, the maximum frequency should be \r
+ adapted accordingly:\r
+ +----------------------------------------------------------------+ \r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ | |------------------------------------------------| \r
+ | (Latency) | voltage range | voltage range | \r
+ | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
+ | |----------------|---------------|---------------| \r
+ | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
+ |-------------- |----------------|---------------|---------------| \r
+ |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
+ |---------------|----------------|---------------|---------------| \r
+ |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| \r
+ +----------------------------------------------------------------+ \r
+\r
+ 3. After reset, the System clock source is the MSI (2 MHz) with 0 WS, Flash\r
+ 32-bit access is enabled and prefetch is disabled.\r
+ \r
+ It is recommended to use the following software sequences to tune the number\r
+ of wait states needed to access the Flash memory with the CPU frequency (HCLK).\r
+ - Increasing the CPU frequency (in the same voltage range)\r
+ - Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" function\r
+ - Check that 64-bit access is taken into account by reading FLASH_ACR\r
+ - Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function\r
+ - Check that the new number of WS is taken into account by reading FLASH_ACR\r
+ - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
+ - Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function \r
+ - Decreasing the CPU frequency (in the same voltage range)\r
+ - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
+ - Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function\r
+ - Program the new number of WS, using "FLASH_SetLatency()" function\r
+ - Check that the new number of WS is taken into account by reading FLASH_ACR\r
+ - Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" function\r
+ - Check that 32-bit access is taken into account by reading FLASH_ACR\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @note - The MSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * - A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready. \r
+ * You can use RCC_GetSYSCLKSource() function to know which clock is\r
+ * currently used as system clock source. \r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock source \r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= ~RCC_CFGR_SW;\r
+ \r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can be one \r
+ * of the following values:\r
+ * - 0x00: MSI used as system clock\r
+ * - 0x04: HSI used as system clock \r
+ * - 0x08: HSE used as system clock\r
+ * - 0x0C: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * these bits to ensure that the system frequency does not exceed the\r
+ * maximum allowed frequency (for more details refer to section above\r
+ * "CPU, AHB and APB busses clocks configuration functions")\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= ~RCC_CFGR_HPRE;\r
+ \r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Low Speed APB clock (PCLK1).\r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE1;\r
+ \r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed APB clock (PCLK2).\r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE2;\r
+ \r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of the System, AHB and APB busses clocks.\r
+ * @note - The frequency returned by this function is not the real frequency\r
+ * in the chip. It is calculated based on the predefined constant and\r
+ * the source selected by RCC_SYSCLKConfig():\r
+ * \r
+ * - If SYSCLK source is MSI, function returns constant the MSI value\r
+ * as defined by the MSI range, refer to RCC_MSIRangeConfig()\r
+ * \r
+ * - If SYSCLK source is HSI, function returns constant HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, function returns constant HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, function returns constant HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * return wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal. \r
+ * \r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
+ * the clocks frequencies. \r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+ RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ case 0x04: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ case 0x08: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+ break;\r
+ case 0x0C: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+ pllmul = PLLMulTable[(pllmul >> 18)];\r
+ plldiv = (plldiv >> 22) + 1;\r
+ \r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock selected as PLL clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);\r
+ }\r
+ else\r
+ {\r
+ /* HSE selected as PLL clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);\r
+ }\r
+ break;\r
+ default: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+ RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ }\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp]; \r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
+ * @brief Peripheral clocks configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Peripheral clocks configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the Peripheral clocks. \r
+ \r
+ 1. The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
+ divided by a programmable prescaler).\r
+ \r
+ 2. After restart from Reset or wakeup from STANDBY, all peripherals are off\r
+ except internal SRAM, Flash and JTAG. Before to start using a peripheral you\r
+ have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()\r
+ , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.\r
+\r
+ 3. To reset the peripherals configuration (to the default state after device reset)\r
+ you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and \r
+ RCC_APB1PeriphResetCmd() functions.\r
+ \r
+ 4. To further reduce power consumption in SLEEP mode the peripheral clocks can\r
+ be disabled prior to executing the WFI or WFE instructions. You can do this\r
+ using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and\r
+ RCC_APB1PeriphClockLPModeCmd() functions. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).\r
+ * @note - As the RTC clock configuration bits are in the RTC domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using PWR_RTCAccessCmd(ENABLE) function before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * - Once the RTC clock is configured it can't be changed unless the RTC\r
+ * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)\r
+ * - The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).\r
+ * \r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock\r
+ * \r
+ * @note - If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes.\r
+ * \r
+ * - The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+ \r
+ if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
+ { \r
+ /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
+ tmpreg = RCC->CR;\r
+\r
+ /* Clear RTCPRE[1:0] bits */\r
+ tmpreg &= ~RCC_CR_RTCPRE;\r
+\r
+ /* Configure HSE division factor for RTC clock */\r
+ tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);\r
+\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+ }\r
+ \r
+ RCC->CSR &= ~RCC_CSR_RTCSEL;\r
+ \r
+ /* Select the RTC clock source */\r
+ RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock source was selected\r
+ * using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the RTC peripheral and associated resources reset.\r
+ * @note This function resets the RTC peripheral, RTC clock source selection\r
+ * (in RCC_CSR) and the backup registers.\r
+ * @param NewState: new state of the RTC reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA\r
+ * @arg RCC_AHBPeriph_GPIOB\r
+ * @arg RCC_AHBPeriph_GPIOC \r
+ * @arg RCC_AHBPeriph_GPIOD\r
+ * @arg RCC_AHBPeriph_GPIOE\r
+ * @arg RCC_AHBPeriph_GPIOH\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG\r
+ * @arg RCC_APB2Periph_TIM9\r
+ * @arg RCC_APB2Periph_TIM10\r
+ * @arg RCC_APB2Periph_TIM11\r
+ * @arg RCC_APB2Periph_ADC1\r
+ * @arg RCC_APB2Periph_SPI1\r
+ * @arg RCC_APB2Periph_USART1 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2\r
+ * @arg RCC_APB1Periph_TIM3\r
+ * @arg RCC_APB1Periph_TIM4\r
+ * @arg RCC_APB1Periph_TIM6\r
+ * @arg RCC_APB1Periph_TIM7\r
+ * @arg RCC_APB1Periph_LCD\r
+ * @arg RCC_APB1Periph_WWDG\r
+ * @arg RCC_APB1Periph_SPI2\r
+ * @arg RCC_APB1Periph_USART2\r
+ * @arg RCC_APB1Periph_USART3\r
+ * @arg RCC_APB1Periph_I2C1\r
+ * @arg RCC_APB1Periph_I2C2\r
+ * @arg RCC_APB1Periph_USB\r
+ * @arg RCC_APB1Periph_PWR\r
+ * @arg RCC_APB1Periph_DAC\r
+ * @arg RCC_APB1Periph_COMP \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA\r
+ * @arg RCC_AHBPeriph_GPIOB\r
+ * @arg RCC_AHBPeriph_GPIOC \r
+ * @arg RCC_AHBPeriph_GPIOD\r
+ * @arg RCC_AHBPeriph_GPIOE\r
+ * @arg RCC_AHBPeriph_GPIOH\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_DMA1 \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBRSTR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG\r
+ * @arg RCC_APB2Periph_TIM9\r
+ * @arg RCC_APB2Periph_TIM10\r
+ * @arg RCC_APB2Periph_TIM11\r
+ * @arg RCC_APB2Periph_ADC1\r
+ * @arg RCC_APB2Periph_SPI1\r
+ * @arg RCC_APB2Periph_USART1 \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2\r
+ * @arg RCC_APB1Periph_TIM3\r
+ * @arg RCC_APB1Periph_TIM4\r
+ * @arg RCC_APB1Periph_TIM6\r
+ * @arg RCC_APB1Periph_TIM7\r
+ * @arg RCC_APB1Periph_LCD\r
+ * @arg RCC_APB1Periph_WWDG\r
+ * @arg RCC_APB1Periph_SPI2\r
+ * @arg RCC_APB1Periph_USART2\r
+ * @arg RCC_APB1Periph_USART3\r
+ * @arg RCC_APB1Periph_I2C1\r
+ * @arg RCC_APB1Periph_I2C2\r
+ * @arg RCC_APB1Periph_USB\r
+ * @arg RCC_APB1Periph_PWR\r
+ * @arg RCC_APB1Periph_DAC\r
+ * @arg RCC_APB1Periph_COMP \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock during SLEEP mode.\r
+ * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA\r
+ * @arg RCC_AHBPeriph_GPIOB\r
+ * @arg RCC_AHBPeriph_GPIOC \r
+ * @arg RCC_AHBPeriph_GPIOD\r
+ * @arg RCC_AHBPeriph_GPIOE\r
+ * @arg RCC_AHBPeriph_GPIOH\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_SRAM \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBLPENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBLPENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB2 peripheral clock during SLEEP mode.\r
+ * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG\r
+ * @arg RCC_APB2Periph_TIM9\r
+ * @arg RCC_APB2Periph_TIM10\r
+ * @arg RCC_APB2Periph_TIM11\r
+ * @arg RCC_APB2Periph_ADC1\r
+ * @arg RCC_APB2Periph_SPI1\r
+ * @arg RCC_APB2Periph_USART1 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2LPENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2LPENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB1 peripheral clock during SLEEP mode.\r
+ * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * - By default, all peripheral clocks are enabled during SLEEP mode. \r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2\r
+ * @arg RCC_APB1Periph_TIM3\r
+ * @arg RCC_APB1Periph_TIM4\r
+ * @arg RCC_APB1Periph_TIM6\r
+ * @arg RCC_APB1Periph_TIM7\r
+ * @arg RCC_APB1Periph_LCD\r
+ * @arg RCC_APB1Periph_WWDG\r
+ * @arg RCC_APB1Periph_SPI2\r
+ * @arg RCC_APB1Periph_USART2\r
+ * @arg RCC_APB1Periph_USART3\r
+ * @arg RCC_APB1Periph_I2C1\r
+ * @arg RCC_APB1Periph_I2C2\r
+ * @arg RCC_APB1Periph_USB\r
+ * @arg RCC_APB1Periph_PWR\r
+ * @arg RCC_APB1Periph_DAC\r
+ * @arg RCC_APB1Periph_COMP \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1LPENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1LPENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group4 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled\r
+ * and if the HSE clock fails, the CSS interrupt occurs and an NMI is\r
+ * automatically generated. The NMI will be executed indefinitely, and \r
+ * since NMI has higher priority than any other IRQ (and main program)\r
+ * the application will be stacked in the NMI ISR unless the CSS interrupt\r
+ * pending bit is cleared.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt\r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready \r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else /* The flag to check is in CSR register (tmp == 2) */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_MASK;\r
+\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= RCC_CSR_RMVF;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+ \r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC's interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+ \r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Real-Time Clock (RTC) peripheral: \r
+ * - Initialization\r
+ * - Calendar (Time and Date) configuration\r
+ * - Alarms (Alarm A and Alarm B) configuration\r
+ * - WakeUp Timer configuration\r
+ * - Daylight Saving configuration\r
+ * - Output pin Configuration\r
+ * - Digital Calibration configuration\r
+ * - TimeStamp configuration\r
+ * - Tampers configuration\r
+ * - Backup Data Registers configuration\r
+ * - Output Type Config configuration\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * RTC Domain Reset\r
+ * =================================================================== \r
+ * After power-on reset, the RTC domain (RTC clock source configuration,\r
+ * RTC registers and RTC Backup data registers) is reset. You can also\r
+ * reset this domain by software using the RCC_RTCResetCmd() function. \r
+ * \r
+ * =================================================================== \r
+ * RTC Operating Condition\r
+ * =================================================================== \r
+ * As long as the supply voltage remains in the operating range, \r
+ * the RTC never stops, regardless of the device status (Run mode, \r
+ * low power modes or under reset).\r
+ * \r
+ * =================================================================== \r
+ * RTC Domain Access\r
+ * =================================================================== \r
+ * After reset, the RTC domain (RTC clock source configuration,\r
+ * RTC registers and RTC Backup data registers) are protected against \r
+ * possible stray write accesses. \r
+ * To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ * - Enable the Power Controller (PWR) APB1 interface clock using the\r
+ * RCC_APB1PeriphClockCmd() function.\r
+ * - Enable access to RTC domain using the PWR_RTCAccessCmd() function.\r
+ * - Select the RTC clock source using the RCC_RTCCLKConfig() function.\r
+ * - Enable RTC Clock using the RCC_RTCCLKCmd() function.\r
+ * \r
+ * =================================================================== \r
+ * RTC Driver: how to use it\r
+ * =================================================================== \r
+ * - Enable the RTC domain access (see description in the section above)\r
+ * - Configure the RTC Prescaler (Asynchronous and Synchronous) and\r
+ * RTC hour format using the RTC_Init() function.\r
+ * \r
+ * Time and Date configuration\r
+ * =========================== \r
+ * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()\r
+ * and RTC_SetDate() functions.\r
+ * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()\r
+ * functions.\r
+ * - Use the RTC_DayLightSavingConfig() function to add or sub one\r
+ * hour to the RTC Calendar. \r
+ * \r
+ * Alarm configuration\r
+ * =================== \r
+ * - To configure the RTC Alarm use the RTC_SetAlarm() function.\r
+ * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function \r
+ * - To read the RTC Alarm, use the RTC_GetAlarm() function.\r
+ * \r
+ * RTC Wakeup configuration\r
+ * ======================== \r
+ * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()\r
+ * function.\r
+ * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() \r
+ * function \r
+ * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function \r
+ * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() \r
+ * function.\r
+ * \r
+ * Outputs configuration\r
+ * ===================== \r
+ * The RTC has 2 different outputs:\r
+ * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B\r
+ * and WaKeUp signals. \r
+ * To output the selected RTC signal on RTC_AF1 pin, use the \r
+ * RTC_OutputConfig() function. \r
+ * - AFO_CALIB: this output is used to manage the RTC Clock divided \r
+ * by 64 (512Hz) signal.\r
+ * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()\r
+ * function. \r
+ * \r
+ * Digital Calibration configuration\r
+ * ================================= \r
+ * - Configure the RTC Digital Calibration Value and the corresponding\r
+ * sign using the RTC_DigitalCalibConfig() function.\r
+ * - Enable the RTC Digital Calibration using the RTC_DigitalCalibCmd() \r
+ * function \r
+ * \r
+ * TimeStamp configuration\r
+ * ======================= \r
+ * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp \r
+ * using the RTC_TimeStampCmd() function.\r
+ * - To read the RTC TimeStamp Time and Date register, use the \r
+ * RTC_GetTimeStamp() function. \r
+ *\r
+ * Tamper configuration\r
+ * ==================== \r
+ * - Configure the RTC Tamper trigger using the RTC_TamperConfig() \r
+ * function.\r
+ * - Enable the RTC Tamper using the RTC_TamperCmd() function.\r
+ *\r
+ * Backup Data Registers configuration\r
+ * =================================== \r
+ * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()\r
+ * function. \r
+ * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()\r
+ * function. \r
+ * \r
+ * =================================================================== \r
+ * RTC and low power modes\r
+ * =================================================================== \r
+ * The MCU can be woken up from a low power mode by an RTC alternate \r
+ * function.\r
+ * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r
+ * RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r
+ * These RTC alternate functions can wake up the system from the Stop \r
+ * and Standby lowpower modes.\r
+ * The system can also wake up from low power modes without depending \r
+ * on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r
+ * or the RTC wakeup events.\r
+ * The RTC provides a programmable time base for waking up from the \r
+ * Stop or Standby mode at regular intervals.\r
+ * Wakeup from STOP and Standby modes is possible only when the RTC \r
+ * clock source is LSE or LSI.\r
+ * \r
+ * =================================================================== \r
+ * Selection of RTC_AF1 alternate functions\r
+ * =================================================================== \r
+ * The RTC_AF1 pin (PC13) can be used for the following purposes:\r
+ * - Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.\r
+ * - AFO_ALARM output \r
+ * - AFO_CALIB output\r
+ * - AFI_TAMPER\r
+ * - AFI_TIMESTAMP\r
+ * \r
+ * +------------------------------------------------------------------------------------------+ \r
+ * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE |\r
+ * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM |\r
+ * | and function | | | | | |Configuration |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Alarm out | | | | | Don't | |\r
+ * | output OD | 1 | 0 |Don't care | Don't care | care | 0 |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Alarm out | | | | | Don't | |\r
+ * | output PP | 1 | 0 |Don't care | Don't care | care | 1 |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Calibration out | | | | | Don't | |\r
+ * | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | TAMPER input | | | | | Don't | | \r
+ * | floating | 0 | 0 | 1 | 0 | care | Don't care |\r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | TIMESTAMP and | | | | | Don't | |\r
+ * | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |\r
+ * | floating | | | | | | | \r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | TIMESTAMP input | | | | | Don't | | \r
+ * | floating | 0 | 0 | 0 | 1 | care | Don't care | \r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care | \r
+ * |-----------------|----------|----------|-----------|--------------|--------|--------------| \r
+ * | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care | \r
+ * +------------------------------------------------------------------------------------------+ \r
+ *\r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rtc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC \r
+ * @brief RTC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* Masks Definition */\r
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)\r
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) \r
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) \r
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)\r
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \\r
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \\r
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \\r
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F ))\r
+\r
+#define INITMODE_TIMEOUT ((uint32_t) 0x00002000)\r
+#define SYNCHRO_TIMEOUT ((uint32_t) 0x00001000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value);\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RTC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to initialize and configure the RTC\r
+ Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers\r
+ Write protection, enter and exit the RTC initialization mode, RTC registers\r
+ synchronization check and reference clock detection enable.\r
+ \r
+ 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is\r
+ split into 2 programmable prescalers to minimize power consumption.\r
+ - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.\r
+ - When both prescalers are used, it is recommended to configure the asynchronous\r
+ prescaler to a high value to minimize consumption.\r
+\r
+ 2. All RTC registers are Write protected. Writing to the RTC registers\r
+ is enabled by writing a key into the Write Protection register, RTC_WPR.\r
+\r
+ 3. To Configure the RTC Calendar, user application should enter initialization\r
+ mode. In this mode, the calendar counter is stopped and its value can be \r
+ updated. When the initialization sequence is complete, the calendar restarts \r
+ counting after 4 RTCCLK cycles.\r
+\r
+ 4. To read the calendar through the shadow registers after Calendar initialization,\r
+ calendar update or after wakeup from low power modes the software must first \r
+ clear the RSF flag. The software must then wait until it is set again before \r
+ reading the calendar, which means that the calendar registers have been \r
+ correctly copied into the RTC_TR and RTC_DR shadow registers.\r
+ The RTC_WaitForSynchro() function implements the above software sequence \r
+ (RSF clear and RSF check).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the RTC registers to their default reset values.\r
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data\r
+ * registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are deinitialized\r
+ * - ERROR: RTC registers are not deinitialized\r
+ */\r
+ErrorStatus RTC_DeInit(void)\r
+{\r
+ __IO uint32_t wutcounter = 0x00;\r
+ uint32_t wutwfstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Reset TR, DR and CR registers */\r
+ RTC->TR = (uint32_t)0x00000000;\r
+ RTC->DR = (uint32_t)0x00002101;\r
+ /* Reset All CR bits except CR[2:0] */\r
+ RTC->CR &= (uint32_t)0x00000007;\r
+ \r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
+ wutcounter++; \r
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Reset all RTC CR register bits */\r
+ RTC->CR &= (uint32_t)0x00000000;\r
+ RTC->WUTR = (uint32_t)0x0000FFFF;\r
+ RTC->PRER = (uint32_t)0x007F00FF;\r
+ RTC->CALIBR = (uint32_t)0x00000000;\r
+ RTC->ALRMAR = (uint32_t)0x00000000; \r
+ RTC->ALRMBR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset ISR register and exit initialization mode */\r
+ RTC->ISR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset Tamper and alternate functions configuration register */\r
+ RTC->TAFCR = 0x00000000;\r
+ \r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS; \r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RTC registers according to the specified parameters \r
+ * in RTC_InitStruct.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains \r
+ * the configuration information for the RTC peripheral.\r
+ * @note The RTC Prescaler register is write protected and can be written in \r
+ * initialization mode only. \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are initialized\r
+ * - ERROR: RTC registers are not initialized \r
+ */\r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));\r
+ assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));\r
+ assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Clear RTC CR FMT Bit */\r
+ RTC->CR &= ((uint32_t)~(RTC_CR_FMT));\r
+ /* Set RTC_CR register */\r
+ RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));\r
+ \r
+ /* Configure the RTC PRER */\r
+ RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);\r
+ RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+\r
+ status = SUCCESS; \r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_InitStruct member with its default value.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ /* Initialize the RTC_HourFormat member */\r
+ RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;\r
+ \r
+ /* Initialize the RTC_AsynchPrediv member */\r
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;\r
+\r
+ /* Initialize the RTC_SynchPrediv member */\r
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC registers write protection.\r
+ * @note All the RTC registers are write protected except for RTC_ISR[13:8], \r
+ * RTC_TAFCR and RTC_BKPxR.\r
+ * @note Writing a wrong key reactivates the write protection.\r
+ * @note The protection mechanism is not affected by system reset. \r
+ * @param NewState: new state of the write protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_WriteProtectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the RTC Initialization mode.\r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC is in Init mode\r
+ * - ERROR: RTC is not in Init mode \r
+ */\r
+ErrorStatus RTC_EnterInitMode(void)\r
+{\r
+ __IO uint32_t initcounter = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t initstatus = 0x00;\r
+ \r
+ /* Check if the Initialization mode is set */\r
+ if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ /* Set the Initialization mode */\r
+ RTC->ISR = (uint32_t)RTC_INIT_MASK;\r
+ \r
+ /* Wait till RTC is in INIT state and if Time out is reached exit */\r
+ do\r
+ {\r
+ initstatus = RTC->ISR & RTC_ISR_INITF;\r
+ initcounter++; \r
+ } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_INITF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS; \r
+ } \r
+ \r
+ return (status); \r
+}\r
+\r
+/**\r
+ * @brief Exits the RTC Initialization mode.\r
+ * @note When the initialization sequence is complete, the calendar restarts \r
+ * counting after 4 RTCCLK cycles. \r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_ExitInitMode(void)\r
+{ \r
+ /* Exit Initialization mode */\r
+ RTC->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+}\r
+\r
+/**\r
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r
+ * synchronized with RTC APB clock.\r
+ * @note The RTC Resynchronization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @note To read the calendar through the shadow registers after Calendar \r
+ * initialization, calendar update or after wakeup from low power modes \r
+ * the software must first clear the RSF flag. \r
+ * The software must then wait until it is set again before reading \r
+ * the calendar, which means that the calendar registers have been \r
+ * correctly copied into the RTC_TR and RTC_DR shadow registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are synchronised\r
+ * - ERROR: RTC registers are not synchronised\r
+ */\r
+ErrorStatus RTC_WaitForSynchro(void)\r
+{\r
+ __IO uint32_t synchrocounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t synchrostatus = 0x00;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Clear RSF flag */\r
+ RTC->ISR &= (uint32_t)RTC_RSF_MASK;\r
+ \r
+ /* Wait the registers to be synchronised */\r
+ do\r
+ {\r
+ synchrostatus = RTC->ISR & RTC_ISR_RSF;\r
+ synchrocounter++; \r
+ } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_RSF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return (status); \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC reference clock detection.\r
+ * @param NewState: new state of the RTC reference clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC reference clock detection is enabled\r
+ * - ERROR: RTC reference clock detection is disabled \r
+ */\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)\r
+{ \r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ { \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC reference clock detection */\r
+ RTC->CR |= RTC_CR_REFCKON; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the RTC reference clock detection */\r
+ RTC->CR &= ~RTC_CR_REFCKON; \r
+ }\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group2 Time and Date configuration functions\r
+ * @brief Time and Date configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Time and Date configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to program and read the RTC Calendar\r
+ (Time and Date).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the RTC current time.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains \r
+ * the time configuration information for the RTC. \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Time register is configured\r
+ * - ERROR: RTC Time register is not configured\r
+ */\r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); \r
+ } \r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));\r
+ }\r
+ \r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \\r
+ (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));\r
+ } \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_TR register */\r
+ RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ \r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_TimeStruct member with its default value\r
+ * (Time = 00h:00min:00sec).\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ /* Time = 00h:00min:00sec */\r
+ RTC_TimeStruct->RTC_H12 = RTC_H12_AM;\r
+ RTC_TimeStruct->RTC_Hours = 0;\r
+ RTC_TimeStruct->RTC_Minutes = 0;\r
+ RTC_TimeStruct->RTC_Seconds = 0; \r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current Time.\r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contain the returned current time configuration. \r
+ * @retval None\r
+ */\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); \r
+ \r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the RTC current date.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains \r
+ * the date configuration information for the RTC.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Date register is configured\r
+ * - ERROR: RTC Date register is not configured\r
+ */\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))\r
+ {\r
+ RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;\r
+ } \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));\r
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));\r
+ assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ assert_param(IS_RTC_MONTH(tmpreg));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
+ assert_param(IS_RTC_DATE(tmpreg));\r
+ }\r
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_Date) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_DR register */\r
+ RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_DateStruct member with its default value\r
+ * (Monday, January 01 xx00).\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ /* Monday, January 01 xx00 */\r
+ RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;\r
+ RTC_DateStruct->RTC_Date = 1;\r
+ RTC_DateStruct->RTC_Month = RTC_Month_January;\r
+ RTC_DateStruct->RTC_Year = 0;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current date. \r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contain the returned current date configuration. \r
+ * @retval None\r
+ */\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); \r
+\r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group3 Alarms configuration functions\r
+ * @brief Alarms (Alarm A and Alarm B) configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Alarms (Alarm A and Alarm B) configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to program and read the RTC Alarms.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the specified RTC Alarm.\r
+ * @note The Alarm register can only be written when the corresponding Alarm\r
+ * is disabled (Use the RTC_AlarmCmd(DISABLE)). \r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @arg RTC_Alarm_B: to select Alarm B \r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that \r
+ * contains the alarm configuration parameters. \r
+ * @retval None\r
+ */\r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm));\r
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ } \r
+ }\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ } \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm register */\r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ RTC->ALRMAR = (uint32_t)tmpreg;\r
+ }\r
+ else\r
+ {\r
+ RTC->ALRMBR = (uint32_t)tmpreg;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_AlarmStruct member with its default value\r
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =\r
+ * all fields are masked).\r
+ * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;\r
+\r
+ /* Alarm Date Settings : Date = 1st day of the month */\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;\r
+\r
+ /* Alarm Masks Settings : Mask = all fields are not masked */\r
+ RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC Alarm value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_Alarm: specifies the alarm to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @arg RTC_Alarm_B: to select Alarm B \r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will \r
+ * contains the output alarm configuration values. \r
+ * @retval None\r
+ */\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm)); \r
+\r
+ /* Get the RTC_ALRMxR register */\r
+ if (RTC_Alarm == RTC_Alarm_A)\r
+ {\r
+ tmpreg = (uint32_t)(RTC->ALRMAR);\r
+ }\r
+ else\r
+ {\r
+ tmpreg = (uint32_t)(RTC->ALRMBR);\r
+ }\r
+\r
+ /* Fill the structure with the read parameters */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \\r
+ RTC_ALRMAR_HU)) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \\r
+ RTC_ALRMAR_MNU)) >> 8);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \\r
+ RTC_ALRMAR_SU));\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r
+ RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Hours);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Minutes);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Seconds);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC Alarm.\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @arg RTC_Alarm_B: to select Alarm B \r
+ * @param NewState: new state of the specified alarm.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Alarm is enabled/disabled\r
+ * - ERROR: RTC Alarm is not enabled/disabled \r
+ */\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)\r
+{\r
+ __IO uint32_t alarmcounter = 0x00;\r
+ uint32_t alarmstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm state */\r
+ if (NewState != DISABLE)\r
+ {\r
+ RTC->CR |= (uint32_t)RTC_Alarm;\r
+\r
+ status = SUCCESS; \r
+ }\r
+ else\r
+ { \r
+ /* Disable the Alarm in RTC_CR register */\r
+ RTC->CR &= (uint32_t)~RTC_Alarm;\r
+ \r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ alarmstatus = RTC->ISR & (RTC_Alarm >> 8);\r
+ alarmcounter++; \r
+ } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ } \r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions\r
+ * @brief WakeUp Timer configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ WakeUp Timer configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to program and read the RTC WakeUp.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC Wakeup clock source.\r
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp\r
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r
+ * @param RTC_WakeUpClock: Wakeup Clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div16\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div8\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div4\r
+ * @arg RTC_WakeUpClock_RTCCLK_Div2\r
+ * @arg RTC_WakeUpClock_CK_SPRE_16bits\r
+ * @arg RTC_WakeUpClock_CK_SPRE_17bits\r
+ * @retval None\r
+ */\r
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the Wakeup Timer clock source bits in CR register */\r
+ RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
+\r
+ /* Configure the clock source */\r
+ RTC->CR |= (uint32_t)RTC_WakeUpClock;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Configures the RTC Wakeup counter.\r
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp\r
+ * is disabled (Use the RTC_WakeUpCmd(DISABLE)). \r
+ * @param RTC_WakeUpCounter: specifies the WakeUp counter.\r
+ * This parameter can be a value from 0x0000 to 0xFFFF. \r
+ * @retval None\r
+ */\r
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Configure the Wakeup Timer counter */\r
+ RTC->WUTR = (uint32_t)RTC_WakeUpCounter;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Returns the RTC WakeUp timer counter value.\r
+ * @param None\r
+ * @retval The RTC WakeUp Counter value.\r
+ */\r
+uint32_t RTC_GetWakeUpCounter(void)\r
+{\r
+ /* Get the counter value */\r
+ return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the RTC WakeUp timer.\r
+ * @param NewState: new state of the WakeUp timer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)\r
+{\r
+ __IO uint32_t wutcounter = 0x00;\r
+ uint32_t wutwfstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Wakeup Timer */\r
+ RTC->CR |= (uint32_t)RTC_CR_WUTE;\r
+ status = SUCCESS; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the Wakeup Timer */\r
+ RTC->CR &= (uint32_t)~RTC_CR_WUTE;\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;\r
+ wutcounter++; \r
+ } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ } \r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group5 Daylight Saving configuration functions\r
+ * @brief Daylight Saving configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Daylight Saving configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the RTC DayLight Saving.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Adds or substract one hour from the current time.\r
+ * @param RTC_DayLightSaveOperation: the value of hour adjustment. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)\r
+ * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)\r
+ * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit \r
+ * in CR register to store the operation.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_StoreOperation_Reset\r
+ * @arg RTC_StoreOperation_Set\r
+ * @retval None\r
+ */\r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));\r
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_BCK);\r
+\r
+ /* Configure the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Returns the RTC Day Light Saving stored operation.\r
+ * @param None\r
+ * @retval RTC Day Light Saving stored operation.\r
+ * - RTC_StoreOperation_Reset\r
+ * - RTC_StoreOperation_Set \r
+ */\r
+uint32_t RTC_GetStoreOperation(void)\r
+{\r
+ return (RTC->CR & RTC_CR_BCK);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group6 Output pin Configuration function\r
+ * @brief Output pin Configuration function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Output pin Configuration function\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the RTC Output source.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC output source (AFO_ALARM).\r
+ * @param RTC_Output: Specifies which signal will be routed to the RTC output. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Output_Disable: No output selected\r
+ * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output\r
+ * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output\r
+ * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output\r
+ * @param RTC_OutputPolarity: Specifies the polarity of the output signal. \r
+ * This parameter can be one of the following:\r
+ * @arg RTC_OutputPolarity_High: The output pin is high when the \r
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r
+ * @arg RTC_OutputPolarity_Low: The output pin is low when the \r
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL)\r
+ * @retval None\r
+ */\r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT(RTC_Output));\r
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);\r
+\r
+ /* Configure the output selection and polarity */\r
+ RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group7 Digital Calibration configuration functions\r
+ * @brief Digital Calibration configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Digital Calibration configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the digital calibration parameters.\r
+ * @param RTC_CalibSign: specifies the sign of the calibration value.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_CalibSign_Positive: The value sign is positive \r
+ * @arg RTC_CalibSign_Negative: The value sign is negative\r
+ * @param Value: value of calibration expressed in ppm (coded on 5 bits) \r
+ * - This value should be between 0 and 63 when using negative sign\r
+ * with a 2-ppm step.\r
+ * - This value should be between 0 and 126 when using positive sign\r
+ * with a 4-ppm step.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC digital calibration are initialized\r
+ * - ERROR: RTC digital calibration are not initialized \r
+ */\r
+ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));\r
+ assert_param(IS_RTC_CALIB_VALUE(Value)); \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the calibration value */\r
+ RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the digital calibration process.\r
+ * @param NewState: new state of the digital calibration.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC digital calibration are enabled/disabled\r
+ * - ERROR: RTC digital calibration are not enabled/disabled \r
+ */\r
+ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Digital Calibration */\r
+ RTC->CR |= (uint32_t)RTC_CR_DCE;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the Digital Calibration */\r
+ RTC->CR &= (uint32_t)~RTC_CR_DCE;\r
+ }\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+ \r
+ status = SUCCESS;\r
+ } \r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock to be output through the relative \r
+ * pin.\r
+ * @param NewState: new state of the digital calibration Output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_CalibOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC clock output */\r
+ RTC->CR |= (uint32_t)RTC_CR_COE;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the RTC clock output */\r
+ RTC->CR &= (uint32_t)~RTC_CR_COE;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RTC_Group8 TimeStamp configuration functions\r
+ * @brief TimeStamp configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ TimeStamp configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or Disables the RTC TimeStamp functionality with the \r
+ * specified time stamp pin stimulating edge.\r
+ * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following:\r
+ * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising \r
+ * edge of the related pin.\r
+ * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param NewState: new state of the TimeStamp.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+\r
+ /* Get the new configuration */\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);\r
+ }\r
+ else\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge);\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ RTC->CR = (uint32_t)tmpreg;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Get the RTC TimeStamp value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contains the TimeStamp time values. \r
+ * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contains the TimeStamp date values. \r
+ * @retval None\r
+ */\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
+ RTC_DateTypeDef* RTC_StampDateStruct)\r
+{\r
+ uint32_t tmptime = 0, tmpdate = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the TimeStamp time and date registers values */\r
+ tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);\r
+ tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Fill the Time structure fields with the read parameters */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Fill the Date structure fields with the read parameters */\r
+ RTC_StampDateStruct->RTC_Year = 0;\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the Time structure parameters to Binary format */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);\r
+\r
+ /* Convert the Date structure parameters to Binary format */\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group9 Tampers configuration functions\r
+ * @brief Tampers configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Tampers configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the select Tamper pin edge.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be RTC_Tamper_1.\r
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that \r
+ * stimulates tamper event. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. \r
+ * @retval None\r
+ */\r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));\r
+ \r
+ if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); \r
+ }\r
+ else\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Tamper detection.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be RTC_Tamper_1.\r
+ * @param NewState: new state of the tamper pin.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected Tamper pin */\r
+ RTC->TAFCR |= (uint32_t)RTC_Tamper;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected Tamper pin */\r
+ RTC->TAFCR &= (uint32_t)~RTC_Tamper; \r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions\r
+ * @brief Backup Data Registers configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Backup Data Registers configuration functions \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a data in a specified RTC Backup data register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register.\r
+ * @param Data: Data to be written in the specified RTC Backup data register. \r
+ * @retval None\r
+ */\r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+\r
+ /* Write the specified register */\r
+ *(__IO uint32_t *)tmp = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified RTC Backup data Register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register. \r
+ * @retval None\r
+ */\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+ \r
+ /* Read the specified register */\r
+ return (*(__IO uint32_t *)tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group11 Output Type Config configuration functions\r
+ * @brief Output Type Config configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Output Type Config configuration functions \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC Output Pin mode. \r
+ * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in \r
+ * Open Drain mode.\r
+ * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in \r
+ * Push Pull mode. \r
+ * @retval None\r
+ */\r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));\r
+ \r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);\r
+ RTC->TAFCR |= (uint32_t)(RTC_OutputType); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group12 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+ All RTC interrupts are connected to the EXTI controller.\r
+ \r
+ - To enable the RTC Alarm interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 17 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using\r
+ the RTC_SetAlarm() and RTC_AlarmCmd() functions.\r
+\r
+ - To enable the RTC Wakeup interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 20 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to generate the RTC wakeup timer event using the \r
+ RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
+\r
+ - To enable the RTC Tamper interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to detect the RTC tamper event using the \r
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.\r
+\r
+ - To enable the RTC TimeStamp interrupt, the following sequence is required:\r
+ - Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ - Configure the RTC to detect the RTC time-stamp event using the \r
+ RTC_TimeStampCmd() functions.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC interrupts.\r
+ * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt mask\r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt mask\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt mask\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt mask\r
+ * @arg RTC_IT_TAMP: Tamper event interrupt mask\r
+ * @param NewState: new state of the specified RTC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CONFIG_IT(RTC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ else\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC flag is set or not.\r
+ * @param RTC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r
+ * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag\r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag\r
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r
+ * @arg RTC_FLAG_ALRBF: Alarm B flag\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag\r
+ * @arg RTC_FLAG_INITF: Initialization mode flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @arg RTC_FLAG_INITS: Registers Configured flag\r
+ * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag\r
+ * @arg RTC_FLAG_ALRBWF: Alarm B Write flag\r
+ * @arg RTC_FLAG_ALRAWF: Alarm A write flag\r
+ * @retval The new state of RTC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));\r
+ \r
+ /* Get all the flags */\r
+ tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);\r
+ \r
+ /* Return the status of the flag */\r
+ if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's pending flags.\r
+ * @param RTC_FLAG: specifies the RTC flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r
+ * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag \r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag\r
+ * @arg RTC_FLAG_WUTF: WakeUp Timer flag\r
+ * @arg RTC_FLAG_ALRBF: Alarm B flag\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @retval None\r
+ */\r
+void RTC_ClearFlag(uint32_t RTC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));\r
+\r
+ /* Clear the Flags in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occurred or not.\r
+ * @param RTC_IT: specifies the RTC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt \r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt \r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt \r
+ * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r
+ * @retval The new state of RTC_IT (SET or RESET).\r
+ */\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0, enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_IT(RTC_IT));\r
+ \r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));\r
+ \r
+ /* Get the Interrupt enable Status */\r
+ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));\r
+ \r
+ /* Get the Interrupt pending bit */\r
+ tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));\r
+ \r
+ /* Get the status of the Interrupt */\r
+ if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's interrupt pending bits.\r
+ * @param RTC_IT: specifies the RTC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt \r
+ * @arg RTC_IT_WUT: WakeUp Timer interrupt \r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt \r
+ * @arg RTC_IT_TAMP1: Tamper 1 event interrupt \r
+ * @retval None\r
+ */\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_IT(RTC_IT));\r
+\r
+ /* Get the RTC_ISR Interrupt pending bits mask */\r
+ tmpreg = (uint32_t)(RTC_IT >> 4);\r
+\r
+ /* Clear the interrupt pending bits in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Converts a 2 digit decimal to BCD format.\r
+ * @param Value: Byte to be converted.\r
+ * @retval Converted byte\r
+ */\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value)\r
+{\r
+ uint8_t bcdhigh = 0;\r
+ \r
+ while (Value >= 10)\r
+ {\r
+ bcdhigh++;\r
+ Value -= 10;\r
+ }\r
+ \r
+ return ((uint8_t)(bcdhigh << 4) | Value);\r
+}\r
+\r
+/**\r
+ * @brief Convert from 2 digit BCD to Binary.\r
+ * @param Value: BCD value to be converted.\r
+ * @retval Converted word\r
+ */\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)\r
+{\r
+ uint8_t tmp = 0;\r
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r
+ return (tmp + (Value & (uint8_t)0x0F));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_spi.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Serial peripheral interface (SPI): \r
+ * - Initialization and Configuration\r
+ * - Data transfers functions\r
+ * - Hardware CRC Calculation\r
+ * - DMA transfers management\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * The I2S feature is not implemented in STM32L1xx Ultra Low Power\r
+ * Medium-density devices and will be supported in future products.\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)\r
+ * function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)\r
+ * function for SPI2.\r
+ *\r
+ * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()\r
+ * function. \r
+ *\r
+ * 3. Peripherals alternate function: \r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function by:\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave \r
+ * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
+ * function.\r
+ *\r
+ * 5. Enable the NVIC and the corresponding interrupt using the function \r
+ * SPI_ITConfig() if you need to use interrupt mode. \r
+ *\r
+ * 6. When using the DMA mode \r
+ * - Configure the DMA using DMA_Init() function\r
+ * - Active the needed channel Request using SPI_I2S_DMACmd() function\r
+ * \r
+ * 7. Enable the SPI using the SPI_Cmd() function.\r
+ * \r
+ * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. \r
+ *\r
+ * 9. Optionally you can enable/configure the following parameters without\r
+ * re-initialization (i.e there is no need to call again SPI_Init() function):\r
+ * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)\r
+ * is programmed as Data direction parameter using the SPI_Init() function\r
+ * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx\r
+ * using the SPI_BiDirectionalLineConfig() function.\r
+ * - When SPI_NSS_Soft is selected as Slave Select Management parameter \r
+ * using the SPI_Init() function it can be possible to manage the \r
+ * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.\r
+ * - Reconfigure the data size using the SPI_DataSizeConfig() function \r
+ * - Enable or disable the SS output using the SPI_SSOutputCmd() function \r
+ * \r
+ * 10. To use the CRC Hardware calculation feature refer to the Peripheral \r
+ * CRC hardware Calculation subsection.\r
+ *\r
+ * @endverbatim \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI \r
+ * @brief SPI driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_MASK ((uint16_t)0x3040)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to initialize the SPI Direction,\r
+ SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud\r
+ Rate Prescaler, SPI First Bit and SPI CRC Polynomial.\r
+ \r
+ The SPI_Init() function follows the SPI configuration procedures for Master mode\r
+ and Slave mode (details for these procedures are available in reference manual\r
+ (RM0038)).\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPIx peripheral registers to their default\r
+ * reset values.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ if (SPIx == SPI1)\r
+ {\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (SPIx == SPI2)\r
+ {\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the SPI_InitStruct.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+ \r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SPI_InitStruct member with its default value.\r
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= SPI_CR1_SPE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the data size for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_DataSize: specifies the SPI data size.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
+ * @retval None\r
+ */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+ /* Clear DFF bit */\r
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
+ /* Set new DFF bit value */\r
+ SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
+ * @arg SPI_Direction_Rx: Selects Rx receive direction\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SS output for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx SS output. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group2 Data transfers functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data transfers functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to manage the SPI data transfers\r
+ \r
+ In reception, data are received and then stored into an internal Rx buffer while \r
+ In transmission, data are first stored into an internal Tx buffer before being \r
+ transmitted.\r
+\r
+ The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()\r
+ function and returns the Rx buffered value. Whereas a write access to the SPI_DR \r
+ can be done using SPI_I2S_SendData() function and stores the written data into \r
+ Tx buffer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx peripheral. \r
+ * @param SPIx: where x can be 1 or 2 in SPI mode.\r
+ * @retval The value of the received data.\r
+ */\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx peripheral.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode. \r
+ * @param Data: Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions\r
+ * @brief Hardware CRC Calculation functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Hardware CRC Calculation functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to manage the SPI CRC hardware \r
+ calculation\r
+\r
+ SPI communication using CRC is possible through the following procedure:\r
+ 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, \r
+ Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
+ function.\r
+ 2. Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ 3. Enable the SPI using the SPI_Cmd() function\r
+ 4. Before writing the last data to the TX buffer, set the CRCNext bit using the \r
+ SPI_TransmitCRC() function to indicate that after transmission of the last \r
+ data, the CRC should be transmitted.\r
+ 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT\r
+ bit is reset. The CRC is also received and compared against the SPI_RXCRCR \r
+ value. \r
+ If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt\r
+ can be generated when the SPI_I2S_IT_ERR interrupt is enabled.\r
+\r
+Note: \r
+-----\r
+ - It is advised to don't read the calculate CRC values during the communication.\r
+\r
+ - When the SPI is in slave mode, be careful to enable CRC calculation only \r
+ when the clock is stable, that is, when the clock is in the steady state. \r
+ If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive \r
+ to the SCK slave input clock as soon as CRCEN is set, and this, whatever \r
+ the value of the SPE bit.\r
+\r
+ - With high bitrate frequencies, be careful when transmitting the CRC.\r
+ As the number of used CPU cycles has to be as low as possible in the CRC \r
+ transfer phase, it is forbidden to call software functions in the CRC \r
+ transmission sequence to avoid errors in the last data and CRC reception. \r
+ In fact, CRCNEXT bit has to be written before the end of the transmission/reception \r
+ of the last data.\r
+\r
+ - For high bit rate frequencies, it is advised to use the DMA mode to avoid the\r
+ degradation of the SPI speed performance due to CPU accesses impacting the \r
+ SPI bandwidth.\r
+\r
+ - When the STM32L15xxx are configured as slaves and the NSS hardware mode is \r
+ used, the NSS pin needs to be kept low between the data phase and the CRC \r
+ phase.\r
+\r
+ - When the SPI is configured in slave mode with the CRC feature enabled, CRC\r
+ calculation takes place even if a high level is applied on the NSS pin. \r
+ This may happen for example in case of a multislave environment where the \r
+ communication master addresses slaves alternately.\r
+\r
+ - Between a slave deselection (high level on NSS) and a new slave selection \r
+ (low level on NSS), the CRC value should be cleared on both master and slave\r
+ sides in order to resynchronize the master and slave for their respective \r
+ CRC calculation.\r
+\r
+ To clear the CRC, follow the procedure below:\r
+ 1. Disable SPI using the SPI_Cmd() function\r
+ 2. Disable the CRC calculation using the SPI_CalculateCRC() function.\r
+ 3. Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ 4. Enable SPI using the SPI_Cmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= SPI_CR1_CRCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit the SPIx CRC value.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= SPI_CR1_CRCNEXT;\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_CRC: specifies the CRC register to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRC_Tx: Selects Tx CRC register\r
+ * @arg SPI_CRC_Rx: Selects Rx CRC register\r
+ * @retval The selected CRC register value..\r
+ */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+ uint16_t crcreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA transfers management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the SPIx DMA interface.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
+ * @param NewState: new state of the selected SPI DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI DMA requests */\r
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This section provides a set of functions allowing to configure the SPI Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+ \r
+ Polling Mode\r
+ =============\r
+ In Polling Mode, the SPI communication can be managed by 6 flags:\r
+ 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register\r
+ 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register\r
+ 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.\r
+ 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur \r
+ 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur\r
+ 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur\r
+\r
+Note: Do not use the BSY flag to handle each data transmission or reception.\r
+----- It is better to use the TXE and RXNE flags instead.\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+\r
+ Interrupt Mode\r
+ ===============\r
+ In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources\r
+ and 5 pending bits: \r
+ Pending Bits:\r
+ ------------- \r
+ 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register\r
+ 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register\r
+ 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur \r
+ 4. SPI_IT_MODF : to indicate if a Mode Fault error occur\r
+ 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur\r
+\r
+ Interrupt Source:\r
+ -----------------\r
+ 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty \r
+ interrupt. \r
+ 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
+ empty interrupt.\r
+ 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+ - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+ - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+ DMA Mode\r
+ ========\r
+ In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:\r
+ 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r
+ 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r
+\r
+ In this Mode it is advised to use the following function:\r
+ - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI interrupts.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified SPI interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ uint16_t itpos = 0, itmask = 0 ;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI interrupt */\r
+ SPIx->CR2 &= (uint16_t)~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI flag is set or not.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
+ * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.\r
+ * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.\r
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Check the status of the specified SPI flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
+ * This function clears only CRCERR flag.\r
+ * @note\r
+ * - OVR (OverRun error) flag is cleared by software sequence: a read \r
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI interrupt has occurred or not.\r
+ * @param SPIx: where x can be\r
+ * - 1 or 2 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
+ * @arg SPI_I2S_IT_MODF: Mode Fault interrupt.\r
+ * @arg SPI_I2S_IT_CRCERR: CRC Error interrupt.\r
+ * @retval The new state of SPI_I2S_IT (SET or RESET).\r
+ */\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI_I2S_IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Get the SPI_I2S_IT IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = 0x01 << itmask;\r
+\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI interrupt */\r
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
+ * @param SPIx: where x can be\r
+ * - 1 or 2 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
+ * This function clears only CRCERR interrupt pending bit. \r
+ * @note\r
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
+ * the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ uint16_t itpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI_I2S IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
+ SPIx->SR = (uint16_t)~itpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_syscfg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the SYSCFG and RI peripherals: \r
+ * - SYSCFG Initialization and Configuration\r
+ * - RI Initialization and Configuration\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * \r
+ * This driver provides functions for:\r
+ * \r
+ * 1. Remapping the memory accessible in the code area using\r
+ * SYSCFG_MemoryRemapConfig() \r
+ * 2. Manage the EXTI lines connection to the GPIOs using\r
+ * SYSCFG_EXTILineConfig().\r
+ * 3. Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).\r
+ * 4. Input routing of COMP1 and COMP2\r
+ * 5. Routing of internal reference voltage VREFINT to PB0 and PB1.\r
+ *\r
+ * 6. The RI registers can be accessed only when the comparator \r
+ * APB interface clock is enabled.\r
+ * To enable comparator clock use:\r
+ * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE);\r
+ *\r
+ * Following functions uses RI registers:\r
+ * - SYSCFG_RIDeInit()\r
+ * - SYSCFG_RITIMSelect()\r
+ * - SYSCFG_RITIMInputCaptureConfig()\r
+ * - SYSCFG_RIResistorConfig()\r
+ * - SYSCFG_RIIOSwitchConfig()\r
+ * - SYSCFG_RISwitchControlModeCmd()\r
+ * - SYSCFG_RIHysteresisConfig()\r
+ *\r
+ * 7- The SYSCFG registers can be accessed only when the SYSCFG \r
+ * interface APB clock is enabled.\r
+ * To enable SYSCFG APB clock use:\r
+ * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ *\r
+ * Following functions uses SYSCFG registers:\r
+ * - SYSCFG_MemoryRemapConfig()\r
+ * - SYSCFG_USBPuCmd()\r
+ * - SYSCFG_EXTILineConfig()\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_syscfg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG \r
+ * @brief SYSCFG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */\r
+#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions\r
+ * @brief SYSCFG Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ SYSCFG Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SYSCFG registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ * @ Note: MEMRMP bits are not reset by APB2 reset.\r
+ */\r
+void SYSCFG_DeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the RI registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIDeInit(void)\r
+{\r
+ RI->ICR = ((uint32_t)0x00000000); /*!< Set RI->ICR to reset value */\r
+ RI->ASCR1 = ((uint32_t)0x00000000); /*!< Set RI->ASCR1 to reset value */ \r
+ RI->ASCR2 = ((uint32_t)0x00000000); /*!< Set RI->ASCR2 to reset value */ \r
+ RI->HYSCR1 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR1 to reset value */\r
+ RI->HYSCR2 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR2 to reset value */\r
+ RI->HYSCR3 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR3 to reset value */\r
+}\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified memory.\r
+ * @param SYSCFG_Memory: selects the memory remapping.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 \r
+ * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r
+ * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 \r
+ * @retval None\r
+ */\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r
+ SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r
+}\r
+\r
+/**\r
+ * @brief Control the internal pull-up on USB DP line.\r
+ * @param NewState: New state of the internal pull-up on USB DP line. \r
+ * This parameter can be ENABLE: Connect internal pull-up on USB DP line.\r
+ * or DISABLE: Disconnect internal pull-up on USB DP line.\r
+ * @retval None\r
+ */\r
+void SYSCFG_USBPuCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ { \r
+ /* Connect internal pull-up on USB DP line */\r
+ SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;\r
+ }\r
+ else\r
+ {\r
+ /* Disconnect internal pull-up on USB DP line */\r
+ SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source \r
+ * for EXTI lines where x can be (A, B, C, D, E or H).\r
+ * @param EXTI_PinSourcex: specifies the EXTI line to be configured.\r
+ * This parameter can be EXTI_PinSourcex where x can be (0..15)\r
+ * @retval None\r
+ */\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
+{\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
+ assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
+ \r
+ tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions\r
+ * @brief RI Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ RI Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the routing interface to select which Timer to be routed.\r
+ * @note Routing capability can be applied only on one of the three timers\r
+ * (TIM2, TIM3 or TIM4) at a time.\r
+ * @param TIM_Select: Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Select_None: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed.\r
+ * @retval None.\r
+ */\r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_TIM(TIM_Select));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = RI->ICR;\r
+\r
+ /* Clear the TIMx select bits */\r
+ tmpreg &= TIM_SELECT_MASK;\r
+\r
+ /* Select the Timer */\r
+ tmpreg |= (TIM_Select);\r
+\r
+ /* Write to RI->ICR register */\r
+ RI->ICR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 1, 2, 3 or 4\r
+ * to a selected I/O pin.\r
+ * @param RI_InputCapture selects which input capture to be routed.\r
+ * This parameter can be one (or combination) of the following parameters:\r
+ * @arg RI_InputCapture_IC1: Input capture 1 is selected.\r
+ * @arg RI_InputCapture_IC2: Input capture 2 is selected.\r
+ * @arg RI_InputCapture_IC3: Input capture 3 is selected.\r
+ * @arg RI_InputCapture_IC4: Input capture 4 is selected.\r
+ * @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15\r
+ * e.g.\r
+ * SYSCFG_RITIMSelect(TIM_Select_TIM2)\r
+ * SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1)\r
+ * allows routing of Input capture IC1 of TIM2 to PA4.\r
+ * For details about correspondence between RI_InputCaptureRouting_x \r
+ * and I/O pins refer to the parameters' description in the header file\r
+ * or refer to the product reference manual.\r
+ * @note Input capture selection bits are not reset by this function.\r
+ * To reset input capture selection bits, use SYSCFG_RIDeInit() function.\r
+ * @note The I/O should be configured in alternate function mode (AF14) using\r
+ * GPIO_PinAFConfig() function.\r
+ * @retval None.\r
+ */\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = RI->ICR;\r
+\r
+ /* Select input captures to be routed */\r
+ tmpreg |= (RI_InputCapture);\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~IC_ROUTING_MASK);\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( RI_InputCaptureRouting);\r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4)); \r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8)); \r
+ }\r
+\r
+ if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)\r
+ {\r
+ /* Clear the input capture select bits */\r
+ tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));\r
+\r
+ /* Set RI_InputCaptureRouting bits */\r
+ tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12)); \r
+ }\r
+\r
+ /* Write to RI->ICR register */\r
+ RI->ICR = tmpreg;\r
+}\r
+/**\r
+ * @brief Configures the Pull-up and Pull-down Resistors \r
+ * @param RI_Resistor selects the resistor to connect. \r
+ * This parameter can be one of the following values:\r
+ * @arg RI_Resistor_10KPU: 10K pull-up resistor\r
+ * @arg RI_Resistor_400KPU: 400K pull-up resistor \r
+ * @arg RI_Resistor_10KPD: 10K pull-down resistor \r
+ * @arg RI_Resistor_400KPD: 400K pull-down resistor\r
+ * @param NewState: New state of the analog switch associated to the selected \r
+ * resistor.\r
+ * This parameter can be:\r
+ * ENABLE so the selected resistor is connected\r
+ * or DISABLE so the selected resistor is disconnected\r
+ * @note To avoid extra power consumption, only one resistor should be enabled\r
+ * at a time. \r
+ * @retval None\r
+ */\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_RESISTOR(RI_Resistor));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the resistor */\r
+ COMP->CSR |= (uint32_t) RI_Resistor;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Resistor */\r
+ COMP->CSR &= (uint32_t) (~RI_Resistor);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Close or Open the routing interface Input Output switches.\r
+ * @param RI_IOSwitch: selects the I/O analog switch number.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15\r
+ * @arg RI_IOSwitch_CH18 --> RI_IOSwitch_CH25\r
+ * @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4\r
+ * @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2\r
+ * @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3\r
+ * @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3\r
+ * @arg RI_IOSwitch_VCOMP\r
+ * @param NewState: New state of the analog switch. \r
+ * This parameter can be \r
+ * ENABLE so the Input Output switch is closed\r
+ * or DISABLE so the Input Output switch is open\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)\r
+{\r
+ uint32_t ioswitchmask = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RI_IOSWITCH(RI_IOSwitch));\r
+ \r
+ /* Read Analog switch register index */\r
+ ioswitchmask = RI_IOSwitch >> 31;\r
+ \r
+ /* Get Bits[30:0] of the IO switch */\r
+ RI_IOSwitch &= 0x7FFFFFFF;\r
+ \r
+ \r
+ if (NewState != DISABLE)\r
+ { \r
+ if (ioswitchmask != 0)\r
+ {\r
+ /* Close the analog switches */\r
+ RI->ASCR1 |= RI_IOSwitch;\r
+ }\r
+ else\r
+ {\r
+ /* Open the analog switches */\r
+ RI->ASCR2 |= RI_IOSwitch;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (ioswitchmask != 0)\r
+ {\r
+ /* Close the analog switches */\r
+ RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);\r
+ }\r
+ else\r
+ {\r
+ /* Open the analog switches */\r
+ RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the switch control mode.\r
+ * @param NewState: New state of the switch control mode. This parameter can\r
+ * be ENABLE: ADC analog switches closed if the corresponding \r
+ * I/O switch is also closed.\r
+ * When using COMP1 switch control mode must be enabled.\r
+ * or DISABLE: ADC analog switches open or controlled by the ADC interface.\r
+ * When using the ADC for acquisition switch control mode \r
+ * must be disabled.\r
+ * @note COMP1 comparator and ADC cannot be used at the same time since \r
+ * they share the ADC switch matrix.\r
+ * @retval None\r
+ */\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ { \r
+ /* Enable the Switch control mode */ \r
+ RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Switch control mode */ \r
+ RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E\r
+ * When the I/Os are programmed in input mode by standard I/O port \r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default. \r
+ * When hysteresis is disabled, it is possible to read the \r
+ * corresponding port with a trigger level of VDDIO/2. \r
+ * @param RI_Port: selects the GPIO Port.\r
+ * This parameter can be one of the following values:\r
+ * @arg RI_PortA : Port A is selected\r
+ * @arg RI_PortB : Port B is selected\r
+ * @arg RI_PortC : Port C is selected\r
+ * @arg RI_PortD : Port D is selected\r
+ * @arg RI_PortE : Port E is selected\r
+ * @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.\r
+ * @param NewState new state of the Hysteresis.\r
+ * This parameter can be:\r
+ * ENABLE so the Hysteresis is on\r
+ * or DISABLE so the Hysteresis is off\r
+ * @retval None\r
+ */\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+ FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RI_PORT(RI_Port));\r
+ assert_param(IS_RI_PIN(RI_Pin));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(RI_Port == RI_PortA)\r
+ { \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR1 |= (uint32_t) RI_Pin;\r
+ }\r
+ }\r
+ \r
+ else if(RI_Port == RI_PortB)\r
+ {\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+ }\r
+ } \r
+ \r
+ else if(RI_Port == RI_PortC)\r
+ {\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR2 |= (uint32_t) (RI_Pin );\r
+ }\r
+ } \r
+ else if(RI_Port == RI_PortD)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+\r
+ }\r
+ } \r
+ else /* RI_Port == RI_PortE */\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Hysteresis on */\r
+ RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+ }\r
+ else\r
+ {\r
+ /* Hysteresis off */\r
+ RI->HYSCR3 |= (uint32_t) (RI_Pin );\r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ \r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_tim.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the TIM peripheral:\r
+ * - TimeBase management\r
+ * - Output Compare management\r
+ * - Input Capture management\r
+ * - Interrupts, DMA and flags management\r
+ * - Clocks management\r
+ * - Synchronization management\r
+ * - Specific interface management\r
+ * - Specific remapping management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * This driver provides functions to configure and program the TIM \r
+ * of all STM32L1xx devices\r
+ * These functions are split in 8 groups: \r
+ * \r
+ * 1. TIM TimeBase management: this group includes all needed functions \r
+ * to configure the TM Timebase unit:\r
+ * - Set/Get Prescaler\r
+ * - Set/Get Autoreload \r
+ * - Counter modes configuration\r
+ * - Set Clock division \r
+ * - Select the One Pulse mode\r
+ * - Update Request Configuration\r
+ * - Update Disable Configuration\r
+ * - Auto-Preload Configuration \r
+ * - Enable/Disable the counter \r
+ * \r
+ * 2. TIM Output Compare management: this group includes all needed \r
+ * functions to configure the Capture/Compare unit used in Output \r
+ * compare mode: \r
+ * - Configure each channel, independently, in Output Compare mode\r
+ * - Select the output compare modes\r
+ * - Select the Polarities of each channel\r
+ * - Set/Get the Capture/Compare register values\r
+ * - Select the Output Compare Fast mode \r
+ * - Select the Output Compare Forced mode \r
+ * - Output Compare-Preload Configuration \r
+ * - Clear Output Compare Reference\r
+ * - Select the OCREF Clear signal\r
+ * - Enable/Disable the Capture/Compare Channels \r
+ * \r
+ * 3. TIM Input Capture management: this group includes all needed \r
+ * functions to configure the Capture/Compare unit used in \r
+ * Input Capture mode:\r
+ * - Configure each channel in input capture mode\r
+ * - Configure Channel1/2 in PWM Input mode\r
+ * - Set the Input Capture Prescaler\r
+ * - Get the Capture/Compare values \r
+ * \r
+ * 4. TIM interrupts, DMA and flags management\r
+ * - Enable/Disable interrupt sources\r
+ * - Get flags status\r
+ * - Clear flags/ Pending bits\r
+ * - Enable/Disable DMA requests \r
+ * - Configure DMA burst mode\r
+ * - Select CaptureCompare DMA request \r
+ * \r
+ * 5. TIM clocks management: this group includes all needed functions \r
+ * to configure the clock controller unit:\r
+ * - Select internal/External clock\r
+ * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx\r
+ * \r
+ * 6. TIM synchronization management: this group includes all needed \r
+ * functions to configure the Synchronization unit:\r
+ * - Select Input Trigger \r
+ * - Select Output Trigger \r
+ * - Select Master Slave Mode \r
+ * - ETR Configuration when used as external trigger \r
+ * \r
+ * 7. TIM specific interface management, this group includes all \r
+ * needed functions to use the specific TIM interface:\r
+ * - Encoder Interface Configuration\r
+ * - Select Hall Sensor \r
+ * \r
+ * 8. TIM specific remapping management includes the Remapping \r
+ * configuration of specific timers \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_tim.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM \r
+ * @brief TIM driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define SMCR_ETR_MASK ((uint16_t)0x00FF) \r
+#define CCMR_OFFSET ((uint16_t)0x0018)\r
+#define CCER_CCE_SET ((uint16_t)0x0001) \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Group1 TimeBase management functions\r
+ * @brief TimeBase management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ TimeBase management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in Timing(Time base) Mode\r
+ =================================================================== \r
+ To use the Timer in Timing(Time base) mode, the following steps are mandatory:\r
+ \r
+ 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
+ \r
+ 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.\r
+ \r
+ 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit\r
+ with the corresponding configuration\r
+ \r
+ 4. Enable the NVIC if you need to generate the update interrupt. \r
+ \r
+ 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) \r
+ \r
+ 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ \r
+ Note1: All other functions can be used seperatly to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval None\r
+ * \r
+ */\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ \r
+ if (TIMx == TIM2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+ }\r
+ else if (TIMx == TIM3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+ }\r
+ else if (TIMx == TIM4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
+ } \r
+\r
+ else if (TIMx == TIM6)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
+ } \r
+ else if (TIMx == TIM7)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
+ } \r
+\r
+ else if (TIMx == TIM9)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);\r
+ } \r
+ else if (TIMx == TIM10)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (TIMx == TIM11)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
+ } \r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Time Base Unit peripheral according to \r
+ * the specified parameters in the TIM_TimeBaseInitStruct.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure that contains the configuration information for\r
+ * the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+\r
+ tmpcr1 = TIMx->CR1; \r
+\r
+ if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))\r
+ { \r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+ }\r
+ \r
+ if(((TIMx) != TIM6) && ((TIMx) != TIM7))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+ \r
+ /* Generate an update event to reload the Prescaler value immediatly */\r
+ TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Prescaler.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Prescaler: specifies the Prescaler Register value\r
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r
+ * @retval None\r
+ */\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Prescaler;\r
+ /* Set or reset the UG Bit */\r
+ TIMx->EGR = TIM_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Specifies the TIMx Counter Mode to be used.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_CounterMode: specifies the Counter Mode to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+ * @retval None\r
+ */\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+ \r
+ tmpcr1 = TIMx->CR1;\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM_CounterMode;\r
+ /* Write to TIMx CR1 register */\r
+ TIMx->CR1 = tmpcr1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Counter Register value\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Counter: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Counter Register value */\r
+ TIMx->CNT = Counter;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Autoreload Register value\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param Autoreload: specifies the Autoreload register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Autoreload Register value */\r
+ TIMx->ARR = Autoreload;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Counter value.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval Counter Register value.\r
+ */\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Counter Register value */\r
+ return TIMx->CNT;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Prescaler value.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @retval Prescaler Register value.\r
+ */\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Prescaler Register value */\r
+ return TIMx->PSC;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIMx Update event.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx UDIS bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the Update Disable Bit */\r
+ TIMx->CR1 |= TIM_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the Update Disable Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Update Request Interrupt source.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_UpdateSource: specifies the Update source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller.\r
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+ \r
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
+ {\r
+ /* Set the URS Bit */\r
+ TIMx->CR1 |= TIM_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the URS Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx peripheral Preload register\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ARR Preload Bit */\r
+ TIMx->CR1 |= TIM_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ARR Preload Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx\92s One Pulse Mode.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_OPMode: specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMode_Single\r
+ * @arg TIM_OPMode_Repetitive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
+ \r
+ /* Reset the OPM Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
+ /* Configure the OPM Mode */\r
+ TIMx->CR1 |= TIM_OPMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Clock Division value.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_CKD: specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
+ * @retval None\r
+ */\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
+ \r
+ /* Reset the CKD Bits */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
+ /* Set the CKD value */\r
+ TIMx->CR1 |= TIM_CKD;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM peripheral.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIMx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Counter */\r
+ TIMx->CR1 |= TIM_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Counter */\r
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group2 Output Compare management functions\r
+ * @brief Output Compare management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Output Compare management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in Output Compare Mode\r
+ =================================================================== \r
+ To use the Timer in Output Compare mode, the following steps are mandatory:\r
+ \r
+ 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
+ \r
+ 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
+ \r
+ 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
+ else the Timer will run with the default configuration:\r
+ - Autoreload value = 0xFFFF\r
+ - Prescaler value = 0x0000\r
+ - Counter mode = Up counting\r
+ - Clock Division = TIM_CKD_DIV1\r
+ \r
+ 3. Fill the TIM_OCInitStruct with the desired parameters including:\r
+ - The TIM Output Compare mode: TIM_OCMode\r
+ - TIM Output State: TIM_OutputState\r
+ - TIM Pulse value: TIM_Pulse\r
+ - TIM Output Compare Polarity : TIM_OCPolarity\r
+ \r
+ 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the \r
+ corresponding configuration\r
+ \r
+ 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ \r
+ Note1: All other functions can be used separately to modify, if needed,\r
+ a specific feature of the Timer. \r
+ \r
+ Note2: In case of PWM mode, this function is mandatory:\r
+ TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); \r
+ \r
+ Note3: If the corresponding interrupt or DMA request are needed, the user should:\r
+ 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). \r
+ 2. Enable the corresponding interrupt (or DMA request) using the function \r
+ TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel1 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel2 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel3 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel4 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+\r
+ /* Disable the Channel 2: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_OCInitStruct member with its default value.\r
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM Output Compare Mode.\r
+ * @note This function disables the selected channel before changing the Output\r
+ * Compare Mode.\r
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCMode_Timing\r
+ * @arg TIM_OCMode_Active\r
+ * @arg TIM_OCMode_Toggle\r
+ * @arg TIM_OCMode_PWM1\r
+ * @arg TIM_OCMode_PWM2\r
+ * @arg TIM_ForcedAction_Active\r
+ * @arg TIM_ForcedAction_InActive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint16_t tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OCM(TIM_OCMode));\r
+ \r
+ tmp = (uint32_t) TIMx;\r
+ tmp += CCMR_OFFSET;\r
+\r
+ tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r
+\r
+ /* Disable the Channel: Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp1;\r
+\r
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
+ {\r
+ tmp += (TIM_Channel>>1);\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= TIM_OCMode;\r
+ }\r
+ else\r
+ {\r
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare1 Register value\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param Compare1: specifies the Capture Compare1 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare1 Register value */\r
+ TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare2 Register value\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param Compare2: specifies the Capture Compare2 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare2 Register value */\r
+ TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare3 Register value\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param Compare3: specifies the Capture Compare3 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare3 Register value */\r
+ TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare4 Register value\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param Compare4: specifies the Capture Compare4 register new value.\r
+ * @retval None\r
+\r
+ */\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare4 Register value */\r
+ TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+ \r
+/**\r
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM \r
+ * peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 1 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 2 Fast feature.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 3 Fast feature.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 4 Fast feature.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF1 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF2 signal on an external event\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF3 signal on an external event\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF4 signal on an external event\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 1 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
+ tmpccer |= TIM_OCPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 2 polarity.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 3 polarity.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC3 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 4 polarity.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC4 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC4P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Selects the OCReference Clear source.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_OCReferenceClear: specifies the OCReference Clear source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.\r
+ * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. \r
+ * @retval None\r
+ */\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));\r
+\r
+ /* Set the TIM_OCReferenceClear source */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);\r
+ TIMx->SMCR |= TIM_OCReferenceClear;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_CCX(TIM_CCx));\r
+\r
+ tmp = CCER_CCE_SET << TIM_Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t)~ tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group3 Input Capture management functions\r
+ * @brief Input Capture management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Input Capture management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in Input Capture Mode\r
+ =================================================================== \r
+ To use the Timer in Input Capture mode, the following steps are mandatory:\r
+ \r
+ 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
+ \r
+ 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
+ \r
+ 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
+ else the Timer will run with the default configuration:\r
+ - Autoreload value = 0xFFFF\r
+ - Prescaler value = 0x0000\r
+ - Counter mode = Up counting\r
+ - Clock Division = TIM_CKD_DIV1\r
+ \r
+ 3. Fill the TIM_ICInitStruct with the desired parameters including:\r
+ - TIM Channel: TIM_Channel\r
+ - TIM Input Capture polarity: TIM_ICPolarity\r
+ - TIM Input Capture selection: TIM_ICSelection\r
+ - TIM Input Capture Prescaler: TIM_ICPrescaler\r
+ - TIM Input CApture filter value: TIM_ICFilter\r
+ \r
+ 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the \r
+ corresponding configuration and to measure only frequency or duty cycle of the input signal,\r
+ or,\r
+ Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the \r
+ corresponding configuration and to measure the frequency and the duty cycle of the input signal\r
+ \r
+ 5. Enable the NVIC or the DMA to read the measured frequency. \r
+ \r
+ 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,\r
+ using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
+ \r
+ 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ \r
+ 8. Use TIM_GetCapturex(TIMx); to read the captured value.\r
+ \r
+ Note1: All other functions can be used seperatly to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+ \r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_ICInitStruct member with its default value.\r
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Rising;\r
+ }\r
+ /* Select the Opposite Input */\r
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+ {\r
+ icoppositeselection = TIM_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ icoppositeselection = TIM_ICSelection_DirectTI;\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 1 value.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @retval Capture Compare 1 Register value.\r
+\r
+ */\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 1 Register value */\r
+ return TIMx->CCR1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 2 value.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @retval Capture Compare 2 Register value.\r
+\r
+ */\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 2 Register value */\r
+ return TIMx->CCR2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 3 value.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ \r
+ /* Get the Capture 3 Register value */\r
+ return TIMx->CCR3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 4 value.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @retval Capture Compare 4 Register value.\r
+ */\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 4 Register value */\r
+ return TIMx->CCR4;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 1 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
+ /* Set the IC1PSC value */\r
+ TIMx->CCMR1 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 2 prescaler.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
+ /* Set the IC2PSC value */\r
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 3 prescaler.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC3PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
+ /* Set the IC3PSC value */\r
+ TIMx->CCMR2 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 4 prescaler.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC4PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
+ /* Set the IC4PSC value */\r
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group4 Interrupts DMA and flags management functions\r
+ * @brief Interrupts, DMA and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts, DMA and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM interrupts.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update interrupt. \r
+ * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11\r
+ * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9. \r
+ * @param NewState: new state of the TIM interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIMx->DIER |= TIM_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx event to be generate by software.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_EventSource: specifies the event source.\r
+ * This parameter can be one or more of the following values: \r
+ * @arg TIM_EventSource_Update: Timer update Event source\r
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source \r
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update event. \r
+ * - TIM9 can only generate an update event, Capture Compare 1 event, \r
+ * Capture Compare 2 event and TIM_EventSource_Trigger. \r
+ * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event. \r
+ * @retval None\r
+ */\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); \r
+ /* Set the event sources */\r
+ TIMx->EGR = TIM_EventSource;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM flag is set or not.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag.\r
+ * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,\r
+ * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
+ * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags \r
+ * @retval The new state of TIM_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ ITStatus bitstatus = RESET; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
+ \r
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's pending flags.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag. \r
+ * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags\r
+ * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
+ * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1\r
+ * or TIM_FLAG_CC1OF flags \r
+ * @retval None\r
+ */\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ TIMx->SR = (uint16_t)~TIM_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM interrupt has occurred or not.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,\r
+ * interrupt and TIM_IT_Trigger interrupt.\r
+ * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1\r
+ * interrupt \r
+ * @retval The new state of the TIM_IT(SET or RESET).\r
+ */\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ ITStatus bitstatus = RESET; \r
+ uint16_t itstatus = 0x0, itenable = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_IT(TIM_IT));\r
+ \r
+ itstatus = TIMx->SR & TIM_IT;\r
+ \r
+ itenable = TIMx->DIER & TIM_IT;\r
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's interrupt pending bits.\r
+ * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,\r
+ * and TIM_IT_Trigger interrupt. \r
+ * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1\r
+ * interrupt \r
+ * @retval None\r
+ */\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ \r
+ /* Clear the IT pending Bit */\r
+ TIMx->SR = (uint16_t)~TIM_IT;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx\92s DMA interface.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_DMABase: DMA Base address.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
+ * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,\r
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
+ * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, \r
+ * TIM_DMABase_CCR4, TIM_DMABase_DCR.\r
+ * @param TIM_DMABurstLength: DMA Burst length.\r
+ * This parameter can be one value between:\r
+ * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
+ * @retval None\r
+ */\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s DMA Requests.\r
+ * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral. \r
+ * @param TIM_DMASource: specifies the DMA Request sources.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_DMA_Update: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ TIMx->DIER |= TIM_DMASource; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param NewState: new state of the Capture Compare DMA source\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCDS Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCDS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCDS Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group5 Clocks management functions\r
+ * @brief Clocks management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Clocks management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx internal Clock\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Internal Trigger as External Clock\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ITRSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @param TIM_TS_ITR0: Internal Trigger 0\r
+ * @param TIM_TS_ITR1: Internal Trigger 1\r
+ * @param TIM_TS_ITR2: Internal Trigger 2\r
+ * @param TIM_TS_ITR3: Internal Trigger 3\r
+ * @retval None\r
+ */\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Select the Internal Trigger */\r
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Trigger as External Clock\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_TIxExternalCLKSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
+ * @param TIM_ICPolarity: specifies the TIx Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param ICFilter : specifies the filter value.\r
+ * This parameter must be a value between 0x0 and 0xF.\r
+ * @retval None\r
+ */\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_FILTER(ICFilter));\r
+ \r
+ /* Configure the Timer Input Clock Source */\r
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ /* Select the Trigger source */\r
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode1\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ /* Select the External clock mode1 */\r
+ tmpsmcr |= TIM_SlaveMode_External1;\r
+ /* Select the Trigger selection : ETRF */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ tmpsmcr |= TIM_TS_ETRF;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode2\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ /* Enable the External clock mode2 */\r
+ TIMx->SMCR |= TIM_SMCR_ECE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group6 Synchronization management functions\r
+ * @brief Synchronization management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Synchronization management functions\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ TIM Driver: how to use it in synchronization Mode\r
+ =================================================================== \r
+ Case of two/several Timers\r
+ **************************\r
+ 1. Configure the Master Timers using the following functions:\r
+ - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); \r
+ - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); \r
+ 2. Configure the Slave Timers using the following functions: \r
+ - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
+ - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
+ \r
+ Case of Timers and external trigger(ETR pin)\r
+ ******************************************** \r
+ 1. Configure the Etrenal trigger using this function:\r
+ - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+ 2. Configure the Slave Timers using the following functions: \r
+ - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
+ - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_InputTriggerSource: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= TIM_InputTriggerSource;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Trigger Output Mode.\r
+ * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.\r
+ * @param TIM_TRGOSource: specifies the Trigger Output source.\r
+ * This paramter can be one of the following values:\r
+ *\r
+ * - For all TIMx\r
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
+ *\r
+ * - For all TIMx except TIM6 and TIM7\r
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
+ * is to be set, as soon as a capture or compare match occurs (TRGO).\r
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
+\r
+ * - For all TIMx except TIM6, TIM7, TIM10 and TIM11\r
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
+\r
+ * - For TIM2, TIM3 and TIM4\r
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
+ *\r
+ * @retval None\r
+ */\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+\r
+ /* Reset the MMS Bits */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
+ /* Select the TRGO source */\r
+ TIMx->CR2 |= TIM_TRGOSource;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Slave Mode.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
+ * the counter and triggers an update of the registers.\r
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
+ * @retval None\r
+ */\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+ \r
+ /* Reset the SMS Bits */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
+ /* Select the Slave Mode */\r
+ TIMx->SMCR |= TIM_SlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIMx Master/Slave Mode.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
+ * and its slaves (through TRGO).\r
+ * @arg TIM_MasterSlaveMode_Disable: No action\r
+ * @retval None\r
+ */\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+ \r
+ /* Reset the MSM Bit */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
+ \r
+ /* Set or Reset the MSM Bit */\r
+ TIMx->SMCR |= TIM_MasterSlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= SMCR_ETR_MASK;\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group7 Specific interface management functions\r
+ * @brief Specific interface management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Specific interface management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx Encoder Interface.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
+ * on the level of the other input.\r
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @retval None\r
+ */\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ uint16_t tmpccmr1 = 0;\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ tmpsmcr |= TIM_EncoderMode;\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx Hall sensor interface.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the TI1S Bit */\r
+ TIMx->CR2 |= TIM_CR2_TI1S;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the TI1S Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group8 Specific remapping management function\r
+ * @brief Specific remapping management function\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Specific remapping management function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.\r
+ * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_Remap: specifies the TIM input remapping source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)\r
+ * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.\r
+ * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default) \r
+ * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.\r
+ * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.\r
+ * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event. \r
+ * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default) \r
+ * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.\r
+ * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock. \r
+ * @retval None\r
+ */\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_REMAP(TIM_Remap));\r
+\r
+ /* Set the Timer remapping configuration */\r
+ TIMx->OR = TIM_Remap;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0;\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 4);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 8);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ \r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 12);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_usart.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Universal synchronous asynchronous receiver\r
+ * transmitter (USART): \r
+ * - Initialization and Configuration\r
+ * - Data transfers\r
+ * - Multi-Processor Communication\r
+ * - LIN mode\r
+ * - Half-duplex mode\r
+ * - Smartcard mode\r
+ * - IrDA mode\r
+ * - DMA transfers management\r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)\r
+ * function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)\r
+ * function for USART2 and USART3.\r
+ *\r
+ * 2. According to the USART mode, enable the GPIO clocks using \r
+ * RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, \r
+ * or and SCLK). \r
+ *\r
+ * 3. Peripheral\92s alternate function: \r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function by:\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware \r
+ * flow control and Mode(Receiver/Transmitter) using the SPI_Init()\r
+ * function.\r
+ *\r
+ * 5. For synchronous mode, enable the clock and program the polarity,\r
+ * phase and last bit using the USART_ClockInit() function.\r
+ *\r
+ * 5. Enable the NVIC and the corresponding interrupt using the function \r
+ * USART_ITConfig() if you need to use interrupt mode. \r
+ *\r
+ * 6. When using the DMA mode \r
+ * - Configure the DMA using DMA_Init() function\r
+ * - Active the needed channel Request using USART_DMACmd() function\r
+ * \r
+ * 7. Enable the USART using the USART_Cmd() function.\r
+ * \r
+ * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. \r
+ *\r
+ * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections\r
+ * for more details\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_usart.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART \r
+ * @brief USART driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */\r
+#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \\r
+ USART_CR1_PS | USART_CR1_TE | \\r
+ USART_CR1_RE))\r
+\r
+/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */\r
+#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\r
+ USART_CR2_CPHA | USART_CR2_LBCL))\r
+\r
+/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */\r
+#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+\r
+/*!< USART Interrupts mask */\r
+#define IT_MASK ((uint16_t)0x001F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to initialize the USART \r
+ in asynchronous and in synchronous modes.\r
+ - For the asynchronous mode only these parameters can be configured: \r
+ - Baud Rate\r
+ - Word Length \r
+ - Stop Bit\r
+ - Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ the possible USART frame formats are as listed in the following table:\r
+ +-------------------------------------------------------------+ \r
+ | M bit | PCE bit | USART frame |\r
+ |---------------------|---------------------------------------| \r
+ | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ +-------------------------------------------------------------+ \r
+ - Hardware flow control\r
+ - Receiver/transmitter modes\r
+\r
+ The USART_Init() function follows the USART asynchronous configuration procedure\r
+ (details for the procedure are available in reference manual (RM0038)).\r
+\r
+ - For the synchronous mode in addition to the asynchronous mode parameters these \r
+ parameters should be also configured:\r
+ - USART Clock Enabled\r
+ - USART polarity\r
+ - USART phase\r
+ - USART LastBit\r
+ \r
+ These parameters can be configured using the USART_ClockInit() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values: USART1, USART2 or USART3.\r
+ * @retval None\r
+ */\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ if (USARTx == USART1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ }\r
+ else if (USARTx == USART2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ }\r
+ else \r
+ {\r
+ if (USARTx == USART3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); \r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral according to the specified\r
+ * parameters in the USART_InitStruct .\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * that contains the configuration information for the specified USART peripheral.\r
+ * @retval None\r
+ */\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00, apbclock = 0x00;\r
+ uint32_t integerdivider = 0x00;\r
+ uint32_t fractionaldivider = 0x00;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12] bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r
+\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_StopBits value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
+ \r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r
+\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/ \r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r
+\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ if (USARTx == USART1) \r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+ }\r
+\r
+ /* Determine the integer part */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 8 Samples */\r
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 16 Samples */\r
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ tmpreg = (integerdivider / 100) << 4;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
+\r
+ /* Implement the fractional part in the register */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
+ }\r
+ \r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_InitStruct member with its default value.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 9600;\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral Clock according to the \r
+ * specified parameters in the USART_ClockInitStruct .\r
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure that contains the configuration information for the specified \r
+ * USART peripheral. \r
+ * @retval None\r
+ */\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set CLKEN bit according to USART_Clock value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_ClockInitStruct member with its default value.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ /* USART_ClockInitStruct members default value */\r
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USARTx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_UE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_Prescaler: specifies the prescaler clock. \r
+ * @retval None\r
+ */\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= USART_GTPR_GT;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's 8x oversampling mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3.\r
+ * @param NewState: new state of the USART 8x oversampling mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ *\r
+ * @note\r
+ * This function has to be called before calling USART_Init()\r
+ * function in order to have correct baudrate Divider value.\r
+ * @retval : None\r
+ */\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_OVER8;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the USART's one bit sampling method.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3.\r
+ * @param NewState: new state of the USART one bit sampling method.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_ONEBIT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group2 Data transfers functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Data transfers functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART data \r
+ transfers.\r
+ \r
+ During an USART reception, data shifts in least significant bit first through \r
+ the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) \r
+ between the internal bus and the received shift register.\r
+\r
+ When a transmission is taking place, a write instruction to the USART_DR register \r
+ stores the data in the TDR register and which is copied in the shift register \r
+ at the end of the current transmission.\r
+\r
+ The read access of the USART_DR register can be done using the USART_ReceiveData()\r
+ function and returns the RDR buffered value. Whereas a write access to the USART_DR \r
+ can be done using USART_SendData() function and stores the written data into \r
+ TDR buffer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits single data through the USARTx peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->DR = (Data & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the USARTx peripheral.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @retval The received data.\r
+ */\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Receive Data */\r
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group3 MultiProcessor Communication functions\r
+ * @brief Multi-Processor Communication functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Multi-Processor Communication functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ multiprocessor communication.\r
+ \r
+ For instance one of the USARTs can be the master, its TX output is connected to \r
+ the RX input of the other USART. The others are slaves, their respective TX outputs \r
+ are logically ANDed together and connected to the RX input of the master.\r
+\r
+ USART multiprocessor communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter \r
+ or Mode receiver and hardware flow control values using the USART_Init()\r
+ function.\r
+ 2. Configures the USART address using the USART_SetAddress() function.\r
+ 3. Configures the wake up methode (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)\r
+ using USART_WakeUpConfig() function only for the slaves.\r
+ 4. Enable the USART using the USART_Cmd() function.\r
+ 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.\r
+\r
+ The USART Slave exit from mute mode when receive the wake up condition.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the address of the USART node.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_Address: Indicates the address of the USART node.\r
+ * @retval None\r
+ */\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_ADDRESS(USART_Address)); \r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the USART is in mute mode or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USART mute mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_RWU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);\r
+ }\r
+}\r
+/**\r
+ * @brief Selects the USART WakeUp method.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_WakeUp: specifies the USART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
+ * @retval None\r
+ */\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
+ \r
+ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group4 LIN mode functions\r
+ * @brief LIN mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ LIN mode functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART LIN \r
+ Mode communication.\r
+ \r
+ In LIN mode, 8-bit data format with 1 stop bit is required in accordance with \r
+ the LIN standard.\r
+\r
+ Only this LIN Feature is supported by the USART IP:\r
+ - LIN Master Synchronous Break send capability and LIN slave break detection\r
+ capability : 13-bit break generation and 10/11 bit break detection\r
+\r
+\r
+ USART LIN Master transmitter communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values using \r
+ the USART_Init() function.\r
+ 2. Enable the USART using the USART_Cmd() function.\r
+ 3. Enable the LIN mode using the USART_LINCmd() function.\r
+ 4. Send the break character using USART_SendBreak() function.\r
+\r
+ USART LIN Master receiver communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values using \r
+ the USART_Init() function.\r
+ 2. Enable the USART using the USART_Cmd() function.\r
+ 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()\r
+ function.\r
+ 4. Enable the LIN mode using the USART_LINCmd() function.\r
+\r
+Note:\r
+----\r
+ 1. In LIN mode, the following bits must be kept cleared:\r
+ - CLKEN in the USART_CR2 register,\r
+ - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the USART LIN Break detection length.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
+ * @retval None\r
+ */\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+ \r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s LIN mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USART LIN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ USARTx->CR2 |= USART_CR2_LINEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @retval None\r
+ */\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Send break characters */\r
+ USARTx->CR1 |= USART_CR1_SBK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group5 Halfduplex mode function\r
+ * @brief Half-duplex mode function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Half-duplex mode function\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ Half-duplex communication.\r
+ \r
+ The USART can be configured to follow a single-wire half-duplex protocol where \r
+ the TX and RX lines are internally connected.\r
+\r
+ USART Half duplex communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter \r
+ or Mode receiver and hardware flow control values using the USART_Init()\r
+ function.\r
+ 2. Configures the USART address using the USART_SetAddress() function.\r
+ 3. Enable the USART using the USART_Cmd() function.\r
+ 4. Enable the half duplex mode using USART_HalfDuplexCmd() function.\r
+\r
+Note:\r
+----\r
+ 1. The RX pin is no longer used\r
+ 2. In Half-duplex mode the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register.\r
+ - SCEN and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Half Duplex communication.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the USART Communication.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_HDSEL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USART_Group6 Smartcard mode functions\r
+ * @brief Smartcard mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Smartcard mode functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ Smartcard communication.\r
+ \r
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as\r
+ defined in the ISO 7816-3 standard.\r
+\r
+ The USART can provide a clock to the smartcard through the SCLK output.\r
+ In smartcard mode, SCLK is not associated to the communication but is simply derived \r
+ from the internal peripheral input clock through a 5-bit prescaler.\r
+\r
+ Smartcard communication is possible through the following procedure:\r
+ 1. Configures the Smartcard Prsecaler using the USART_SetPrescaler() function.\r
+ 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.\r
+ 3. Program the USART clock using the USART_ClockInit() function as following:\r
+ - USART Clock enabled\r
+ - USART CPOL Low\r
+ - USART CPHA on first edge\r
+ - USART Last Bit Clock Enabled\r
+ 4. Program the Smartcard interface using the USART_Init() function as following:\r
+ - Word Length = 9 Bits\r
+ - 1.5 Stop Bit\r
+ - Even parity\r
+ - BaudRate = 12096 baud\r
+ - Hardware flow control disabled (RTS and CTS signals)\r
+ - Tx and Rx enabled\r
+ 5. Optionally you can enable the parity error interrupt using the USART_ITConfig()\r
+ function\r
+ 6. Enable the USART using the USART_Cmd() function.\r
+ 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.\r
+ 8. Enable the Smartcard interface using the USART_SmartCardCmd() function.\r
+\r
+ Please refer to the ISO 7816-3 specification for more details.\r
+\r
+Note: \r
+-----\r
+ 1. It is also possible to choose 0.5 stop bit for receiving but it is recommended \r
+ to use 1.5 stop bits for both transmitting and receiving to avoid switching \r
+ between the two configurations.\r
+ 2. In smartcard mode, the following bits must be kept cleared:\r
+ - LINEN bit in the USART_CR2 register.\r
+ - HDSEL and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the specified USART guard time.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_GuardTime: specifies the guard time. \r
+ * @retval None\r
+ */\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= USART_GTPR_PSC;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Smart Card mode.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_SCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the NACK transmission.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_NACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group7 IrDA mode functions\r
+ * @brief IrDA mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ IrDA mode functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to manage the USART \r
+ IrDA communication.\r
+ \r
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data\r
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver \r
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.\r
+ While receiving data, transmission should be avoided as the data to be transmitted\r
+ could be corrupted.\r
+\r
+ IrDA communication is possible through the following procedure:\r
+ 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver \r
+ modes and hardware flow control values using the USART_Init() function.\r
+ 2. Enable the USART using the USART_Cmd() function.\r
+ 3. Configures the IrDA pulse width by configuring the prescaler using \r
+ the USART_SetPrescaler() function.\r
+ 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode\r
+ using the USART_IrDAConfig() function.\r
+ 5. Enable the IrDA using the USART_IrDACmd() function.\r
+\r
+Note: \r
+-----\r
+ 1. A pulse of width less than two and greater than one PSC period(s) may or may\r
+ not be rejected.\r
+ 2. The receiver set up time should be managed by software. The IrDA physical layer\r
+ specification specifies a minimum of 10 ms delay between transmission and \r
+ reception (IrDA is a half duplex protocol).\r
+ 3. In IrDA mode, the following bits must be kept cleared:\r
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register.\r
+ - SCEN and HDSEL bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IrDAMode: specifies the IrDA mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IrDAMode_LowPower\r
+ * @arg USART_IrDAMode_Normal\r
+ * @retval None\r
+ */\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+ \r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param NewState: new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_IREN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group8 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ DMA transfers management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the USART\92s DMA interface.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_DMAReq: specifies the DMA request.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_DMAReq_Tx: USART DMA transmit request\r
+ * @arg USART_DMAReq_Rx: USART DMA receive request\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USART_Group9 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This subsection provides a set of functions allowing to configure the USART \r
+ Interrupts sources, DMA channels requests and check or clear the flags or \r
+ pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+ \r
+ Polling Mode\r
+ =============\r
+ In Polling Mode, the SPI communication can be managed by 10 flags:\r
+ 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register\r
+ 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register\r
+ 3. USART_FLAG_TC : to indicate the status of the transmit operation\r
+ 4. USART_FLAG_IDLE : to indicate the status of the Idle Line \r
+ 5. USART_FLAG_CTS : to indicate the status of the nCTS input\r
+ 6. USART_FLAG_LBD : to indicate the status of the LIN break detection\r
+ 7. USART_FLAG_NE : to indicate if a noise error occur\r
+ 8. USART_FLAG_FE : to indicate if a frame error occur\r
+ 9. USART_FLAG_PE : to indicate if a parity error occur\r
+ 10. USART_FLAG_ORE : to indicate if an Overrun error occur\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+\r
+ Interrupt Mode\r
+ ===============\r
+ In Interrupt Mode, the USART communication can be managed by 8 interrupt sources\r
+ and 10 pending bits: \r
+\r
+ Pending Bits:\r
+ ------------- \r
+ 1. USART_IT_TXE : to indicate the status of the transmit buffer register\r
+ 2. USART_IT_RXNE : to indicate the status of the receive buffer register\r
+ 3. USART_IT_TC : to indicate the status of the transmit operation\r
+ 4. USART_IT_IDLE : to indicate the status of the Idle Line \r
+ 5. USART_IT_CTS : to indicate the status of the nCTS input\r
+ 6. USART_IT_LBD : to indicate the status of the LIN break detection\r
+ 7. USART_IT_NE : to indicate if a noise error occur\r
+ 8. USART_IT_FE : to indicate if a frame error occur\r
+ 9. USART_IT_PE : to indicate if a parity error occur\r
+ 10. USART_IT_ORE : to indicate if an Overrun error occur\r
+\r
+ Interrupt Source:\r
+ -----------------\r
+ 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty \r
+ interrupt. \r
+ 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
+ empty interrupt.\r
+ 3. USART_IT_TC : specifies the interrupt source for the Transmit complete \r
+ interrupt. \r
+ 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. \r
+ 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. \r
+ 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection\r
+ interrupt. \r
+ 7. USART_IT_PE : specifies the interrupt source for theparity error interrupt. \r
+ 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt.\r
+\r
+ Note: Some parameters are coded in order to use them as interrupt source or \r
+ ---- as pending bits.\r
+\r
+ In this Mode it is advised to use the following functions:\r
+ - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+ - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+ - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+ DMA Mode\r
+ ========\r
+ In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:\r
+ 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request\r
+ 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request\r
+\r
+ In this Mode it is advised to use the following function:\r
+ - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART interrupts.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @param NewState: new state of the specified USARTx interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
+{\r
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+ uint32_t usartxbase = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ usartxbase = (uint32_t)USARTx;\r
+\r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & IT_MASK;\r
+ itmask = (((uint32_t)0x01) << itpos);\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ usartxbase += 0x0C;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ usartxbase += 0x10;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ usartxbase += 0x14; \r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(__IO uint32_t*)usartxbase |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint32_t*)usartxbase &= ~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART flag is set or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag\r
+ * @arg USART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg USART_FLAG_TC: Transmission Complete flag\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg USART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg USART_FLAG_ORE: OverRun Error flag\r
+ * @arg USART_FLAG_NE: Noise Error flag\r
+ * @arg USART_FLAG_FE: Framing Error flag\r
+ * @arg USART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of USART_FLAG (SET or RESET).\r
+ */\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_FLAG(USART_FLAG));\r
+ \r
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's pending flags.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag.\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) flags are cleared by software \r
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
+ * - RXNE flag can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC flag can be also cleared by software sequence: a read operation to \r
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
+ * to USART_DR register (USART_SendData()).\r
+ * - TXE flag is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+ \r
+ USARTx->SR = (uint16_t)~USART_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART interrupt has occurred or not.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IT: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_ORE: OverRun Error interrupt\r
+ * @arg USART_IT_NE: Noise Error interrupt\r
+ * @arg USART_IT_FE: Framing Error interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of USART_IT (SET or RESET).\r
+ */\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_GET_IT(USART_IT)); \r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & IT_MASK;\r
+ itmask = (uint32_t)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ bitpos = (uint32_t)0x01 << bitpos;\r
+ bitpos &= USARTx->SR;\r
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx\92s interrupt pending bits.\r
+ * @param USARTx: Select the USART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2 or USART3.\r
+ * @param USART_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt. \r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) pending bits are cleared by \r
+ * software sequence: a read operation to USART_SR register \r
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC pending bit can be also cleared by software sequence: a read \r
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
+ * operation to USART_DR register (USART_SendData()).\r
+ * - TXE pending bit is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint16_t bitpos = 0x00, itmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_IT(USART_IT)); \r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
+ USARTx->SR = (uint16_t)~itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Window watchdog (WWDG) peripheral: \r
+ * - Prescaler, Refresh window and Counter configuration\r
+ * - WWDG activation\r
+ * - Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * WWDG features\r
+ * ===================================================================\r
+ * \r
+ * Once enabled the WWDG generates a system reset on expiry of a programmed\r
+ * time period, unless the program refreshes the counter (downcounter) \r
+ * before to reach 0x3F value (i.e. a reset is generated when the counter\r
+ * value rolls over from 0x40 to 0x3F). \r
+ * An MCU reset is also generated if the counter value is refreshed\r
+ * before the counter has reached the refresh window value. This \r
+ * implies that the counter must be refreshed in a limited window.\r
+ * \r
+ * Once enabled the WWDG cannot be disabled except by a system reset. \r
+ * \r
+ * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r
+ * reset occurs.\r
+ * \r
+ * The WWDG counter input clock is derived from the APB clock divided \r
+ * by a programmable prescaler.\r
+ * \r
+ * WWDG counter clock = PCLK1 / Prescaler\r
+ * WWDG timeout = (WWDG counter clock) * (counter value)\r
+ * \r
+ * Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function\r
+ * \r
+ * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function\r
+ * \r
+ * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function\r
+ * \r
+ * 4. Set the WWDG counter value and start it using WWDG_Enable() function.\r
+ * When the WWDG is enabled the counter value should be configured to \r
+ * a value greater than 0x40 to prevent generating an immediate reset. \r
+ * \r
+ * 5. Optionally you can enable the Early wakeup interrupt which is \r
+ * generated when the counter reach 0x40.\r
+ * Once enabled this interrupt cannot be disabled except by a system reset.\r
+ * \r
+ * 6. Then the application program must refresh the WWDG counter at regular\r
+ * intervals during normal operation to prevent an MCU reset, using\r
+ * WWDG_SetCounter() function. This operation must occur only when\r
+ * the counter value is lower than the refresh window value, \r
+ * programmed using WWDG_SetWindowValue(). \r
+ *\r
+ * @endverbatim \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_wwdg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG \r
+ * @brief WWDG driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ----------- WWDG registers bit address in the alias region ----------- */\r
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
+\r
+/* Alias word address of EWI bit */\r
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
+#define EWI_BitNumber 0x09\r
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
+\r
+/* --------------------- WWDG registers bit mask ------------------------ */\r
+\r
+/* CFR register bit mask */\r
+#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)\r
+#define CFR_W_MASK ((uint32_t)0xFFFFFF80)\r
+#define BIT_MASK ((uint8_t)0x7F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions\r
+ * @brief Prescaler, Refresh window and Counter configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Prescaler, Refresh window and Counter configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG Prescaler.\r
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
+ * @retval None\r
+ */\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
+ /* Clear WDGTB[1:0] bits */\r
+ tmpreg = WWDG->CFR & CFR_WDGTB_MASK;\r
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
+ tmpreg |= WWDG_Prescaler;\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the downcounter.\r
+ * This parameter value must be lower than 0x80.\r
+ * @retval None\r
+ */\r
+void WWDG_SetWindowValue(uint8_t WindowValue)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
+ /* Clear W[6:0] bits */\r
+\r
+ tmpreg = WWDG->CFR & CFR_W_MASK;\r
+\r
+ /* Set W[6:0] bits according to WindowValue value */\r
+ tmpreg |= WindowValue & (uint32_t) BIT_MASK;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
+ * @note Once enabled this interrupt cannot be disabled except by a system reset. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_EnableIT(void)\r
+{\r
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG counter value.\r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset) \r
+ * @retval None\r
+ */\r
+void WWDG_SetCounter(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = Counter & BIT_MASK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group2 WWDG activation functions\r
+ * @brief WWDG activation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ WWDG activation functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables WWDG and load the counter value. \r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset)\r
+ * @retval None\r
+ */\r
+void WWDG_Enable(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ WWDG->CR = WWDG_CR_WDGA | Counter;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r
+ */\r
+FlagStatus WWDG_GetFlagStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((WWDG->SR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears Early Wakeup interrupt flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_ClearFlag(void)\r
+{\r
+ WWDG->SR = (uint32_t)RESET;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-typedef unsigned int uint32_t;
-
-#define GPIOC 0x40011000 // port C
-#define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
-#define GPIOC_ODR (GPIOC + 0x0c) // port output data register
-#define LED_BLUE (1<<8) // pin 8
-#define LED_GREEN (1<<9) // pin 9
-
-#define delay() \
-do { \
- register unsigned int i; \
- for (i = 0; i < 1000000; ++i) \
- __asm__ __volatile__ ("nop\n\t":::"memory"); \
-} while (0)
-
-static void __attribute__((naked)) __attribute__((used)) main(void)
-{
- *(volatile uint32_t*)GPIOC_CRH = 0x44444411;
-
- while (1)
- {
- *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN;
- delay();
- *(volatile uint32_t*)GPIOC_ODR = 0;
- delay();
- }
-}
--- /dev/null
+CFLAGS+=-g
+CFLAGS+=-DCONFIG_USE_LIBUSB
+CFLAGS+=-DCONFIG_USE_LIBSG
+CFLAGS+=-DDEBUG
+CFLAGS+=-std=gnu99
+CFLAGS+=-Wall -Wextra
+CFLAGS+=-I../src
+
+LDFLAGS=-L.. -lstlink -lusb-1.0 -lsgutils2
+
+SRCS=main.c
+OBJS=$(SRCS:.c=.o)
+
+NAME=flash
+
+all: $(NAME)
+
+$(NAME): $(OBJS)
+ $(CC) $(CFLAGS) -o $(NAME) $(OBJS) $(LDFLAGS)
+
+%.o: %.c
+ $(CC) $(CFLAGS) -c $^ -o $@
+
+clean:
+ rm -f $(OBJS)
+ rm -f $(NAME)
+
+.PHONY: clean all
--- /dev/null
+/* simple wrapper around the stlink_flash_write function */
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "stlink-common.h"
+
+
+int main(int ac, char** av)
+{
+ /* stlinkv1 command line: ./flash /dev/sgX path addr */
+ /* stlinkv2 command line: ./flash path addr */
+
+ stlink_t* sl = NULL;
+ stm32_addr_t addr;
+ const char* path;
+ int err;
+
+ if (ac == 4) /* stlinkv1 */
+ {
+ static const int scsi_verbose = 2;
+ sl = stlink_quirk_open(av[1], scsi_verbose);
+ path = av[2];
+ addr = strtoul(av[3], NULL, 16);
+ }
+ else if (ac == 3) /* stlinkv2 */
+ {
+ sl = stlink_open_usb(NULL, 10);
+ path = av[1];
+ addr = strtoul(av[2], NULL, 16);
+ }
+ else /* invalid */
+ {
+ printf("invalid command line\n");
+ goto on_error;
+ }
+
+ if (sl == NULL) goto on_error;
+
+ err = stlink_fwrite_flash(sl, path, addr);
+ if (err == -1)
+ {
+ printf("stlink_fwrite_flash() == -1\n");
+ goto on_error;
+ }
+
+ on_error:
+ if (sl != NULL) stlink_close(sl);
+
+ return err;
+}
}
}
- if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE)
- stlink_enter_swd_mode(sl);
+ if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) {
+ stlink_exit_dfu_mode(sl);
+ }
+
+ if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) {
+ stlink_enter_swd_mode(sl);
+ }
uint32_t chip_id = stlink_chip_id(sl);
printf("Chip ID is %08x.\n", chip_id);
// memory map is in 1k blocks.
current_memory_map = make_memory_map(params, flash_size * 0x400);
- int port;
-
- if(argc == 1) {
- // not on 64bit?
- //srand((unsigned int)&port);
- port = rand()/65535;
- }
- else {
- port = atoi(argv[1]);
- }
+ int port = 4242;
while(serve(sl, port) == 0);
if(!strcmp(queryName, "Supported")) {
reply = strdup("PacketSize=3fff;qXfer:memory-map:read+");
} else if(!strcmp(queryName, "Xfer")) {
- char *type, *op, *annex, *s_addr, *s_length;
+ char *type, *op, *s_addr, *s_length;
char *tok = params;
+ char *annex __attribute__((unused));
type = strsep(&tok, ":");
op = strsep(&tok, ":");
// Max data transfer size.
// 6kB = max mem32_read block, 8kB sram
//#define Q_BUF_LEN 96
-#define Q_BUF_LEN 1024 * 100
+#define Q_BUF_LEN (1024 * 100)
// st-link vendor cmd's
#define USB_ST_VID 0x0483
// unprocessed
int stlink_erase_flash_mass(stlink_t* sl);
int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
+ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
// PUBLIC
uint16_t stlink_chip_id(stlink_t *sl);
if (sl) {
struct stlink_libsg *slsg = sl->backend_data;
scsi_pt_close_device(slsg->sg_fd);
- // CAUTION!? s this right?
free(slsg);
- free(sl);
}
}
}
}
+
+static void parse_version(stlink_t *stl) {
+ struct stlink_libsg *sl = stl->backend_data;
+
+ sl->st_vid = 0;
+ sl->stlink_pid = 0;
+
+ if (stl->q_len <= 0) {
+ fprintf(stderr, "Error: could not parse the stlink version");
+ return;
+ }
+
+ uint32_t b0 = stl->q_buf[0]; //lsb
+ uint32_t b1 = stl->q_buf[1];
+ uint32_t b2 = stl->q_buf[2];
+ uint32_t b3 = stl->q_buf[3];
+ uint32_t b4 = stl->q_buf[4];
+ uint32_t b5 = stl->q_buf[5]; //msb
+
+ // b0 b1 || b2 b3 | b4 b5
+ // 4b | 6b | 6b || 2B | 2B
+ // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
+
+ sl->stlink_v = (b0 & 0xf0) >> 4;
+ sl->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
+ sl->swim_v = b1 & 0x3f;
+ sl->st_vid = (b3 << 8) | b2;
+ sl->stlink_pid = (b5 << 8) | b4;
+}
+
void _stlink_sg_version(stlink_t *stl) {
struct stlink_libsg *sl = stl->backend_data;
D(stl, "\n*** stlink_version ***\n");
stl->q_len = 6;
sl->q_addr = 0;
stlink_q(stl);
+ parse_version(stl);
}
// Get stlink mode:
void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) {
struct stlink_libsg *sg = sl->backend_data;
+
+ /* unused */
+ regp = regp;
+
clear_cdb(sg);
sg->cdb_cmd_blk[1] = STLINK_DEBUG_READALLREGS;
sl->q_len = 84;
stlink_version(sl);
struct stlink_libsg *sg = sl->backend_data;
- if (sg->st_vid != USB_ST_VID || sg->stlink_pid != USB_STLINK_PID) {
+ if ((sg->st_vid != USB_ST_VID) || (sg->stlink_pid != USB_STLINK_PID)) {
fprintf(stderr, "Error: the device %s is not a stlink\n",
dev_name);
fprintf(stderr, " VID: got %04x expect %04x \n",
unsigned char* const buf = sl->q_buf;
ssize_t size;
-#if Q_BUF_LEN < UINT16_MAX
- assert(len < sizeof(sl->q_buf));
-#endif
+ /* assume len < sizeof(sl->q_buf) */
memset(buf, 0, sizeof (sl->q_buf));
buf[0] = STLINK_DEBUG_COMMAND;
stlink_print_data(sl);
}
+
+#if 1 /* stlinkv1 */
+
void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const buf = sl->q_buf;
DD(sl, "rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80));
}
+#else /* stlinkv2 */
+
+static void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) {
+ struct stlink_libusb * const slu = sl->backend_data;
+ unsigned char* const buf = sl->q_buf;
+ unsigned char* const cmd_buf = sl->c_buf;
+ ssize_t size;
+ int i;
+
+#define STLINK_JTAG_COMMAND 0xf2
+#define STLINK_JTAG_READALLREGS2 0x3a
+ memset(cmd_buf, 0, STLINK_CMD_SIZE);
+ cmd_buf[0] = STLINK_JTAG_COMMAND;
+ cmd_buf[1] = STLINK_JTAG_READALLREGS2;
+ size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 84);
+
+ if (size == -1) {
+ printf("[!] send_recv\n");
+ return;
+ }
+
+ sl->q_len = (size_t) size;
+
+ for(i=0; i<16; i++)
+ regp->r[i]= read_uint32(sl->q_buf, i*4);
+
+ regp->xpsr = read_uint32(sl->q_buf, 64);
+ regp->main_sp = read_uint32(sl->q_buf, 68);
+ regp->process_sp = read_uint32(sl->q_buf, 72);
+ regp->rw = read_uint32(sl->q_buf, 76);
+ regp->rw2 = read_uint32(sl->q_buf, 80);
+}
+
+#endif /* stlinkv1 */
+
void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const buf = sl->q_buf;
}
}
+
+#if 1 /* stlinkv1 */
+
void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const buf = sl->q_buf;
stlink_print_data(sl);
}
+#else /* stlinkv2 */
+
+void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) {
+ struct stlink_libusb * const slu = sl->backend_data;
+ unsigned char* const buf = sl->q_buf;
+ unsigned char *cmd_buf = sl->c_buf;
+ ssize_t size;
+
+#define STLINK_JTAG_WRITEREG2 0x34
+ memset(cmd_buf, 0, STLINK_CMD_SIZE);
+ cmd_buf[0] = STLINK_JTAG_COMMAND;
+ cmd_buf[1] = STLINK_JTAG_WRITEREG2;
+ cmd_buf[2] = idx;
+ write_uint32(cmd_buf + 3, reg);
+ size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 2);
+ if (size == -1) {
+ printf("[!] send_recv\n");
+ return;
+ }
+ sl->q_len = (size_t) size;
+ stlink_print_data(sl);
+}
+
+#endif /* stlinkv1 */
+
+
stlink_backend_t _stlink_usb_backend = {
_stlink_usb_close,
_stlink_usb_exit_debug_mode,
stlink_t* sl = NULL;
struct stlink_libusb* slu = NULL;
+ /* unused */
+ dev_name = dev_name;
+
sl = malloc(sizeof (stlink_t));
slu = malloc(sizeof (struct stlink_libusb));
if (sl == NULL) goto on_error;
stlink_t* sl;
reg regs;
+ /* unused */
+ ac = ac;
+ av = av;
+
sl = stlink_open_usb(NULL, 10);
if (sl != NULL) {
printf("-- version\n");
+++ /dev/null
-#ifndef STLINK_HW_H_INCLUDED
-# define STLINK_HW_H_INCLUDED
-
-// STLINK_DEBUG_RESETSYS, etc:
-#define STLINK_OK 0x80
-#define STLINK_FALSE 0x81
-#define STLINK_CORE_RUNNING 0x80
-#define STLINK_CORE_HALTED 0x81
-#define STLINK_CORE_STAT_UNKNOWN -1
-
-#define STLINK_GET_VERSION 0xf1
-#define STLINK_GET_CURRENT_MODE 0xf5
-
-#define STLINK_DEBUG_COMMAND 0xF2
-#define STLINK_DFU_COMMAND 0xF3
-#define STLINK_DFU_EXIT 0x07
-
-// STLINK_GET_CURRENT_MODE
-#define STLINK_DEV_DFU_MODE 0x00
-#define STLINK_DEV_MASS_MODE 0x01
-#define STLINK_DEV_DEBUG_MODE 0x02
-#define STLINK_DEV_UNKNOWN_MODE -1
-
-// jtag mode cmds
-#define STLINK_DEBUG_ENTER 0x20
-#define STLINK_DEBUG_EXIT 0x21
-#define STLINK_DEBUG_READCOREID 0x22
-#define STLINK_DEBUG_GETSTATUS 0x01
-#define STLINK_DEBUG_FORCEDEBUG 0x02
-#define STLINK_DEBUG_RESETSYS 0x03
-#define STLINK_DEBUG_READALLREGS 0x04
-#define STLINK_DEBUG_READREG 0x05
-#define STLINK_DEBUG_WRITEREG 0x06
-#define STLINK_DEBUG_READMEM_32BIT 0x07
-#define STLINK_DEBUG_WRITEMEM_32BIT 0x08
-#define STLINK_DEBUG_RUNCORE 0x09
-#define STLINK_DEBUG_STEPCORE 0x0a
-#define STLINK_DEBUG_SETFP 0x0b
-#define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
-#define STLINK_DEBUG_CLEARFP 0x0e
-#define STLINK_DEBUG_WRITEDEBUGREG 0x0f
-#define STLINK_DEBUG_ENTER_SWD 0xa3
-#define STLINK_DEBUG_ENTER_JTAG 0x00
-
-#endif /* STLINK_HW_H_INCLUDED */
+++ /dev/null
-USBlyzer Report\r
-\r
-Capture List\r
-\r
-Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
-START,0001,17:45:39.429,,,,,,,,,,,,\r
-URB,0002,17:45:39.503,73.849 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0003-0002,17:45:39.505,75.843 ms,1.995 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0004,17:45:39.505,75.897 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0005-0004,17:45:39.507,77.812 ms,1.916 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0006,17:45:39.707,277.851 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0007-0006,17:45:39.709,279.821 ms,1.969 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0008,17:45:39.709,279.860 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0009-0008,17:45:39.711,281.806 ms,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0010,17:45:39.911,481.876 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0011-0010,17:45:39.913,483.827 ms,1.952 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0012,17:45:39.913,483.872 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0013-0012,17:45:39.915,485.806 ms,1.934 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0014,17:45:40.115,685.865 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0015-0014,17:45:40.116,687.797 ms,1.932 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0016,17:45:40.117,687.841 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0017-0016,17:45:40.118,689.796 ms,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0018,17:45:40.319,889.869 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0019-0018,17:45:40.320,891.792 ms,1.922 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0020,17:45:40.321,891.830 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0021-0020,17:45:40.321,892.814 ms,984 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0022,17:45:40.522,1.092884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0023-0022,17:45:40.523,1.094793 s,1.909 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0024,17:45:40.524,1.094839 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0025-0024,17:45:40.525,1.096788 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0026,17:45:40.725,1.295894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0027-0026,17:45:40.726,1.297784 s,1.891 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0028,17:45:40.726,1.297822 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0029-0028,17:45:40.728,1.299784 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0030,17:45:40.928,1.498899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0031-0030,17:45:40.929,1.500780 s,1.881 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0032,17:45:40.929,1.500814 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0033-0032,17:45:40.931,1.502781 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0034,17:45:41.131,1.701903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0035-0034,17:45:41.132,1.703782 s,1.879 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0036,17:45:41.132,1.703816 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0037-0036,17:45:41.134,1.705777 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0038,17:45:41.334,1.904910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0039-0038,17:45:41.335,1.906771 s,1.862 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0040,17:45:41.335,1.906805 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0041-0040,17:45:41.337,1.908771 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0042,17:45:41.537,2.107928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0043-0042,17:45:41.538,2.109777 s,1.849 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0044,17:45:41.538,2.109811 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0045-0044,17:45:41.540,2.111768 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0046,17:45:41.540,2.111800 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00\r
-URB,0047-0046,17:45:41.541,2.112767 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0048,17:45:41.541,2.112791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0049-0048,17:45:41.543,2.114766 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0050,17:45:41.543,2.114793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0051-0050,17:45:41.544,2.115767 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0052,17:45:41.544,2.115790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0053-0052,17:45:41.546,2.117768 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 01\r
-URB,0054,17:45:41.546,2.117799 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0055-0054,17:45:41.547,2.118768 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0056,17:45:41.547,2.118793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0057-0056,17:45:41.549,2.120767 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 00\r
-URB,0058,17:45:41.549,2.120798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 41 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0059-0058,17:45:41.550,2.121767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0060,17:45:41.550,2.121792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0061-0060,17:45:41.552,2.123768 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0062,17:45:41.552,2.123798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0063-0062,17:45:41.553,2.124767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0064,17:45:41.553,2.124791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0065-0064,17:45:41.555,2.126767 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
-URB,0066,17:45:41.555,2.126794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0067-0066,17:45:41.556,2.127767 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0068,17:45:41.556,2.127791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0069-0068,17:45:41.558,2.129767 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0070,17:45:41.558,2.129794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0071-0070,17:45:41.559,2.130767 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0072,17:45:41.559,2.130791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 01\r
-URB,0073-0072,17:45:41.561,2.132768 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0074,17:45:41.561,2.132793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0075-0074,17:45:41.563,2.134767 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0076,17:45:41.563,2.134790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0077-0076,17:45:41.565,2.136767 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0078,17:45:41.565,2.136798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0079-0078,17:45:41.566,2.137767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0080,17:45:41.566,2.137791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
-URB,0081-0080,17:45:41.568,2.139766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0082,17:45:41.568,2.139792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0083-0082,17:45:41.570,2.141767 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0084,17:45:41.570,2.141792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0085-0084,17:45:41.572,2.143769 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0086,17:45:41.572,2.143800 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0087-0086,17:45:41.573,2.144767 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0088,17:45:41.573,2.144791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
-URB,0089-0088,17:45:41.575,2.146766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0090,17:45:41.575,2.146791 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0091-0090,17:45:41.577,2.148766 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0092,17:45:41.577,2.148790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0093-0092,17:45:41.579,2.150766 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0094,17:45:41.579,2.150793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0095-0094,17:45:41.580,2.151767 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0096,17:45:41.580,2.151790 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
-URB,0097-0096,17:45:41.582,2.153766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0098,17:45:41.582,2.153790 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0099-0098,17:45:41.584,2.155769 s,1.979 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0100,17:45:41.584,2.155793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0101-0100,17:45:41.586,2.157767 s,1.974 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0102,17:45:41.586,2.157797 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0103-0102,17:45:41.587,2.158767 s,970 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0104,17:45:41.587,2.158791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
-URB,0105-0104,17:45:41.589,2.160766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0106,17:45:41.589,2.160792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0107-0106,17:45:41.591,2.162766 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0108,17:45:41.591,2.162791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0109-0108,17:45:41.593,2.164767 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0110,17:45:41.593,2.164801 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3A 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0111-0110,17:45:41.594,2.165766 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0112,17:45:41.594,2.165790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0113-0112,17:45:41.599,2.170766 s,4.976 ms,Bulk or Interrupt Transfer,64 bytes data,80 00 00 01 04 00 00 00...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 04 00 00 00 00 00 00 00 3F 00 00 00 06 00 00 00 C8 14 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 19 00 20 6B 01 00 20\r
-URB,0114,17:45:41.599,2.170777 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0115-0114,17:45:41.601,2.172761 s,1.984 ms,Bulk or Interrupt Transfer,24 bytes data,A8 0A 00 20 00 00 00 21...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),A8 0A 00 20 00 00 00 21 88 19 00 20 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0116,17:45:41.601,2.172796 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C A8 0A 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 0C A8 0A 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0117-0116,17:45:41.602,2.173763 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0118,17:45:41.602,2.173789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0119-0118,17:45:41.604,2.175766 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,01 D0,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),01 D0\r
-URB,0120,17:45:41.604,2.175792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0121-0120,17:45:41.605,2.176766 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0122,17:45:41.605,2.176794 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0123-0122,17:45:41.607,2.178767 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0124,17:45:41.608,2.178876 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 04 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 07 04 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0125-0124,17:45:41.608,2.179765 s,889 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0126,17:45:41.608,2.179791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0127-0126,17:45:41.610,2.181767 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 00\r
-URB,0128,17:45:41.610,2.181793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0129-0128,17:45:41.611,2.182766 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,0130,17:45:41.611,2.182789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0131-0130,17:45:41.613,2.184766 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0132,17:45:41.614,2.185390 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 94 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 94 19 00 20 04 00 00 00 00 00 00 00 00 00\r
-URB,0133-0132,17:45:41.614,2.185766 s,376 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,0134,17:45:41.614,2.185793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0135-0134,17:45:41.616,2.187766 s,1.972 ms,Bulk or Interrupt Transfer,4 bytes data,1D 0E 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),1D 0E 00 20\r
-URB,0136,17:45:41.616,2.187794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0137-0136,17:45:41.617,2.188767 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,0138,17:45:41.617,2.188791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0139-0138,17:45:41.619,2.190766 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0140,17:45:41.620,2.191087 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 9C 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 9C 19 00 20 04 00 00 00 00 00 00 00 00 00\r
-URB,0141-0140,17:45:41.620,2.191766 s,679 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,0142,17:45:41.620,2.191790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0143-0142,17:45:41.622,2.193765 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,83 0F 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),83 0F 00 20\r
-URB,0144,17:45:41.622,2.193791 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0145-0144,17:45:41.623,2.194768 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,0146,17:45:41.623,2.194792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0147-0146,17:45:41.625,2.196767 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0148,17:45:41.626,2.197059 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 E4 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 E4 19 00 20 04 00 00 00 00 00 00 00 00 00\r
-URB,0149-0148,17:45:41.626,2.197765 s,706 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,0150,17:45:41.626,2.197789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0151-0150,17:45:41.628,2.199766 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes data,67 14 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),67 14 00 20\r
-URB,0152,17:45:41.628,2.199792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0153-0152,17:45:41.629,2.200766 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,0154,17:45:41.629,2.200790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0155-0154,17:45:41.631,2.202765 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-\r
-This report was generated by USBlyzer http://www.usblyzer.com/\r
+++ /dev/null
-USBlyzer Report\r
-\r
-Capture List\r
-\r
-Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
-START,0001,16:01:27.054,,,,,,,,,,,,\r
-Create,0002,16:05:07.963,220.908617 s,,Create,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA8002864690h,\r
-Create,0003-0002,16:05:07.963,220.908641 s,24 us,Create,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA8002864690h,Success\r
-URB,0004,16:05:07.963,220.908764 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0005-0004,16:05:07.965,220.910795 s,2.032 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
-URB,0006,16:05:07.965,220.910876 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
-URB,0007-0006,16:05:07.968,220.912779 s,1.903 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),23 80 83 04 48 37\r
-URB,0008,16:05:07.968,220.912813 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0009-0008,16:05:07.968,220.913777 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
-URB,0010,16:05:07.968,220.913800 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
-URB,0011-0010,16:05:07.970,220.914777 s,978 us,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),00 01\r
-URB,0012,16:05:07.970,220.914803 s,,Bulk or Interrupt Transfer,16 bytes data,F3 08 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F3 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0013-0012,16:05:07.970,220.915778 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
-URB,0014,16:05:07.970,220.915799 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
-URB,0015-0014,16:05:07.973,220.917778 s,1.979 ms,Bulk or Interrupt Transfer,20 bytes data,40 00 FF FF 4A 82 34 06...,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),40 00 FF FF 4A 82 34 06 53 FF 68 06 48 82 57 51 07 38 12 87\r
-URB,0016,16:05:07.973,220.917815 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0017-0016,16:05:07.973,220.918777 s,963 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
-URB,0018,16:05:07.973,220.918799 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
-URB,0019-0018,16:05:07.975,220.920778 s,1.978 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),23 80 83 04 48 37\r
-Cleanup,0020,16:07:29.920,362.863914 s,,Cleanup,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,\r
-Cleanup,0021-0020,16:07:29.920,362.863990 s,76 us,Cleanup,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,Success\r
-Close,0022,16:07:29.920,362.863994 s,,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,\r
-Close,0023-0022,16:07:29.920,362.863998 s,4 us,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,Success\r
-Create,0024,16:07:43.292,376.235500 s,,Create,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80067CE0D0h,\r
-Create,0025-0024,16:07:43.292,376.235525 s,24 us,Create,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80067CE0D0h,Success\r
-URB,0026,16:07:43.292,376.235653 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0027-0026,16:07:43.294,376.237673 s,2.020 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success)\r
-URB,0028,16:07:43.294,376.237720 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
-URB,0029-0028,16:07:43.296,376.239653 s,1.933 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),23 80 83 04 48 37\r
-URB,0030,16:07:43.296,376.239690 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0031-0030,16:07:43.297,376.240648 s,959 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success)\r
-URB,0032,16:07:43.297,376.240676 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
-URB,0033-0032,16:07:43.299,376.242648 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),00 01\r
-URB,0034,16:07:43.299,376.242680 s,,Bulk or Interrupt Transfer,16 bytes data,F3 07 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F3 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0035-0034,16:07:43.300,376.243647 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success)\r
-URB,0036,16:07:43.301,376.244139 s,,Bulk or Interrupt Transfer,16 bytes data,F2 30 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0037-0036,16:07:43.302,376.245654 s,1.515 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
-URB,0038,16:07:43.302,376.245686 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
-URB,0039-0038,16:07:43.304,376.247651 s,1.965 ms,Bulk or Interrupt Transfer,2 bytes data,04 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),04 00\r
-URB,0040,16:07:43.305,376.247993 s,,Bulk or Interrupt Transfer,16 bytes data,F2 32 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0041-0040,16:07:43.305,376.248654 s,661 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
-URB,0042,16:07:43.305,376.248685 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
-URB,0043-0042,16:07:43.307,376.250665 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,04 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),04 00\r
-URB,0044,16:07:43.307,376.250708 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0045-0044,16:07:43.309,376.251656 s,948 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
-URB,0046,16:07:43.309,376.251689 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
-URB,0047-0046,16:07:43.310,376.253650 s,1.961 ms,Bulk or Interrupt Transfer,2 bytes data,02 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),02 00\r
-URB,0048,16:07:43.310,376.253680 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 35 F0 ED 00 E0 00 00 5F A0 00 00 00 00 00 00\r
-URB,0049-0048,16:07:43.311,376.254647 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
-URB,0050,16:07:43.311,376.254672 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
-URB,0051-0050,16:07:43.314,376.256648 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,08 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),08 00\r
-URB,0052,16:07:43.314,376.256675 s,,Bulk or Interrupt Transfer,16 bytes data,F2 21 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 21 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0053-0052,16:07:43.314,376.257649 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
-Cleanup,0054,16:07:43.314,376.257674 s,,Cleanup,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,\r
-Cleanup,0055-0054,16:07:43.314,376.257719 s,45 us,Cleanup,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,Success\r
-Close,0056,16:07:43.314,376.257722 s,,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,\r
-Close,0057-0056,16:07:43.314,376.257726 s,3 us,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,Success\r
-\r
-This report was generated by USBlyzer http://www.usblyzer.com/\r
+++ /dev/null
-USBlyzer Report\r
-\r
-Capture List\r
-\r
-Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
-START,0001,17:43:38.035,,,,,,,,,,,,\r
-URB,0002,17:44:01.236,23.201589 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0003-0002,17:44:01.238,23.203514 s,1.924 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,0004,17:44:01.238,23.203558 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0005-0004,17:44:01.240,23.205498 s,1.940 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
-URB,0006,17:44:01.240,23.205532 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0007-0006,17:44:01.241,23.206491 s,960 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0008,17:44:01.241,23.206517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0009-0008,17:44:01.243,23.208494 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0010,17:44:01.243,23.208535 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0011-0010,17:44:01.244,23.209491 s,956 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0012,17:44:01.244,23.209515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0013-0012,17:44:01.246,23.211490 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
-URB,0014,17:44:01.246,23.211517 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0015-0014,17:44:01.247,23.212490 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0016,17:44:01.247,23.212515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0017-0016,17:44:01.249,23.214501 s,1.986 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0018,17:44:01.249,23.214544 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0019-0018,17:44:01.250,23.215493 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0020,17:44:01.250,23.215522 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 01\r
-URB,0021-0020,17:44:01.252,23.217580 s,2.058 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0022,17:44:01.252,23.217648 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0023-0022,17:44:01.254,23.219490 s,1.843 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0024,17:44:01.254,23.219518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0025-0024,17:44:01.256,23.221489 s,1.971 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0026,17:44:01.256,23.221519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0027-0026,17:44:01.257,23.222489 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0028,17:44:01.257,23.222512 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
-URB,0029-0028,17:44:01.259,23.224489 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0030,17:44:01.259,23.224513 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0031-0030,17:44:01.261,23.226489 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0032,17:44:01.261,23.226512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0033-0032,17:44:01.263,23.228488 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0034,17:44:01.263,23.228515 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0035-0034,17:44:01.264,23.229489 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0036,17:44:01.264,23.229513 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
-URB,0037-0036,17:44:01.266,23.231489 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0038,17:44:01.266,23.231523 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0039-0038,17:44:01.268,23.233488 s,1.965 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0040,17:44:01.268,23.233512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0041-0040,17:44:01.270,23.235488 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0042,17:44:01.270,23.235514 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0043-0042,17:44:01.271,23.236487 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0044,17:44:01.271,23.236510 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
-URB,0045-0044,17:44:01.272,23.237487 s,977 us,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0046,17:44:01.272,23.237512 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0047-0046,17:44:01.273,23.238488 s,976 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0048,17:44:01.273,23.238512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0049-0048,17:44:01.275,23.240489 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0050,17:44:01.275,23.240516 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0051-0050,17:44:01.276,23.241489 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0052,17:44:01.276,23.241511 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
-URB,0053-0052,17:44:01.278,23.243487 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0054,17:44:01.278,23.243511 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0055-0054,17:44:01.279,23.244488 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0056,17:44:01.279,23.244513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0057-0056,17:44:01.281,23.246491 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0058,17:44:01.281,23.246535 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 01 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 35 F0 ED 00 E0 01 00 5F A0 00 00 00 00 00 00\r
-URB,0059-0058,17:44:01.282,23.247488 s,953 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0060,17:44:01.282,23.247512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0061-0060,17:44:01.284,23.249527 s,2.015 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0062,17:44:01.285,23.249896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0063-0062,17:44:01.285,23.250503 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0064,17:44:01.285,23.250533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0065-0064,17:44:01.287,23.252495 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0066,17:44:01.288,23.252884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0067-0066,17:44:01.288,23.253503 s,619 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0068,17:44:01.288,23.253528 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0069-0068,17:44:01.290,23.255495 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0070,17:44:01.291,23.255892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0071-0070,17:44:01.291,23.256498 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0072,17:44:01.291,23.256526 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0073-0072,17:44:01.293,23.258496 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0074,17:44:01.294,23.258894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0075-0074,17:44:01.294,23.259494 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0076,17:44:01.294,23.259523 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0077-0076,17:44:01.296,23.261494 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0078,17:44:01.297,23.261891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0079-0078,17:44:01.297,23.262495 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0080,17:44:01.297,23.262521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0081-0080,17:44:01.299,23.264495 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0082,17:44:01.300,23.264888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0083-0082,17:44:01.300,23.265494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0084,17:44:01.300,23.265520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0085-0084,17:44:01.302,23.267581 s,2.061 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0086,17:44:01.303,23.267906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0087-0086,17:44:01.303,23.268497 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0088,17:44:01.303,23.268527 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0089-0088,17:44:01.305,23.270494 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0090,17:44:01.306,23.270899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0091-0090,17:44:01.306,23.271494 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0092,17:44:01.306,23.271522 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0093-0092,17:44:01.308,23.273498 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0094,17:44:01.309,23.273886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0095-0094,17:44:01.309,23.274495 s,609 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0096,17:44:01.309,23.274520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0097-0096,17:44:01.311,23.276494 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0098,17:44:01.312,23.276884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0099-0098,17:44:01.312,23.277494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0100,17:44:01.312,23.277518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0101-0100,17:44:01.314,23.279495 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0102,17:44:01.315,23.279888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0103-0102,17:44:01.315,23.280494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0104,17:44:01.315,23.280517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0105-0104,17:44:01.317,23.282495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0106,17:44:01.318,23.282883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0107-0106,17:44:01.318,23.283494 s,611 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0108,17:44:01.318,23.283517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0109-0108,17:44:01.320,23.285493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0110,17:44:01.321,23.285893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0111-0110,17:44:01.321,23.286494 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0112,17:44:01.321,23.286520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0113-0112,17:44:01.323,23.288494 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0114,17:44:01.324,23.288887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0115-0114,17:44:01.324,23.289495 s,608 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0116,17:44:01.324,23.289519 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0117-0116,17:44:01.326,23.291494 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0118,17:44:01.327,23.291891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0119-0118,17:44:01.327,23.292493 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0120,17:44:01.327,23.292517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0121-0120,17:44:01.329,23.294494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0122,17:44:01.330,23.294883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0123-0122,17:44:01.330,23.295494 s,611 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0124,17:44:01.330,23.295517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0125-0124,17:44:01.332,23.297495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0126,17:44:01.333,23.297883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0127-0126,17:44:01.333,23.298494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0128,17:44:01.333,23.298517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0129-0128,17:44:01.335,23.300494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0130,17:44:01.336,23.300889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0131-0130,17:44:01.336,23.301494 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0132,17:44:01.336,23.301518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0133-0132,17:44:01.338,23.303494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0134,17:44:01.339,23.303884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0135-0134,17:44:01.339,23.304494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0136,17:44:01.339,23.304517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0137-0136,17:44:01.341,23.306493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0138,17:44:01.342,23.306884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0139-0138,17:44:01.342,23.307496 s,612 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0140,17:44:01.342,23.307520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0141-0140,17:44:01.344,23.309501 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0142,17:44:01.345,23.309893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0143-0142,17:44:01.345,23.310495 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0144,17:44:01.345,23.310521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0145-0144,17:44:01.347,23.312495 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0146,17:44:01.348,23.312884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0147-0146,17:44:01.348,23.313493 s,609 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0148,17:44:01.348,23.313517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0149-0148,17:44:01.350,23.315494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0150,17:44:01.351,23.315884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0151-0150,17:44:01.351,23.316494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0152,17:44:01.351,23.316517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0153-0152,17:44:01.353,23.318494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0154,17:44:01.354,23.318886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0155-0154,17:44:01.354,23.319494 s,608 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0156,17:44:01.354,23.319518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0157-0156,17:44:01.356,23.321494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0158,17:44:01.357,23.321890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0159-0158,17:44:01.357,23.322494 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0160,17:44:01.357,23.322517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0161-0160,17:44:01.359,23.324493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0162,17:44:01.360,23.324886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0163-0162,17:44:01.360,23.325493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0164,17:44:01.360,23.325517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0165-0164,17:44:01.362,23.327495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0166,17:44:01.363,23.327887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0167-0166,17:44:01.363,23.328494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0168,17:44:01.363,23.328517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0169-0168,17:44:01.365,23.330494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0170,17:44:01.366,23.330888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0171-0170,17:44:01.366,23.331493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0172,17:44:01.366,23.331518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0173-0172,17:44:01.368,23.333493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0174,17:44:01.369,23.333885 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0175-0174,17:44:01.369,23.334497 s,612 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0176,17:44:01.369,23.334520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0177-0176,17:44:01.371,23.336494 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0178,17:44:01.372,23.336887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0179-0178,17:44:01.372,23.337493 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0180,17:44:01.372,23.337516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0181-0180,17:44:01.374,23.339494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0182,17:44:01.375,23.339889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0183-0182,17:44:01.375,23.340492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0184,17:44:01.375,23.340517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0185-0184,17:44:01.377,23.342494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0186,17:44:01.378,23.342886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0187-0186,17:44:01.378,23.343493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0188,17:44:01.378,23.343516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0189-0188,17:44:01.380,23.345494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0190,17:44:01.381,23.345888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0191-0190,17:44:01.381,23.346493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0192,17:44:01.381,23.346516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0193-0192,17:44:01.383,23.348495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0194,17:44:01.384,23.348887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0195-0194,17:44:01.384,23.349493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0196,17:44:01.384,23.349516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0197-0196,17:44:01.386,23.351494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0198,17:44:01.387,23.351891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0199-0198,17:44:01.387,23.352493 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0200,17:44:01.387,23.352516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0201-0200,17:44:01.389,23.354493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0202,17:44:01.390,23.354887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0203-0202,17:44:01.390,23.355492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0204,17:44:01.390,23.355516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0205-0204,17:44:01.392,23.357492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0206,17:44:01.393,23.357886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0207-0206,17:44:01.393,23.358493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0208,17:44:01.393,23.358516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0209-0208,17:44:01.395,23.360494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0210,17:44:01.396,23.360885 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0211-0210,17:44:01.396,23.361493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0212,17:44:01.396,23.361516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0213-0212,17:44:01.398,23.363492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0214,17:44:01.399,23.363886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0215-0214,17:44:01.399,23.364493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0216,17:44:01.399,23.364516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0217-0216,17:44:01.401,23.366493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0218,17:44:01.402,23.366886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0219-0218,17:44:01.402,23.367492 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0220,17:44:01.402,23.367516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0221-0220,17:44:01.404,23.369494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0222,17:44:01.405,23.369888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0223-0222,17:44:01.405,23.370492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0224,17:44:01.405,23.370516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0225-0224,17:44:01.407,23.372492 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0226,17:44:01.408,23.372890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0227-0226,17:44:01.408,23.373492 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0228,17:44:01.408,23.373515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0229-0228,17:44:01.410,23.375494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0230,17:44:01.411,23.375887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0231-0230,17:44:01.411,23.376492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0232,17:44:01.411,23.376516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0233-0232,17:44:01.413,23.378492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0234,17:44:01.414,23.378886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0235-0234,17:44:01.414,23.379492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0236,17:44:01.414,23.379515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0237-0236,17:44:01.416,23.381492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0238,17:44:01.417,23.381895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0239-0238,17:44:01.417,23.382503 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0240,17:44:01.417,23.382534 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0241-0240,17:44:01.419,23.384495 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0242,17:44:01.420,23.384887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0243-0242,17:44:01.420,23.385492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0244,17:44:01.420,23.385516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0245-0244,17:44:01.422,23.387493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0246,17:44:01.423,23.387888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0247-0246,17:44:01.423,23.388492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0248,17:44:01.423,23.388516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0249-0248,17:44:01.425,23.390493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0250,17:44:01.426,23.390889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0251-0250,17:44:01.426,23.391492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0252,17:44:01.426,23.391516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0253-0252,17:44:01.428,23.393492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0254,17:44:01.429,23.393887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0255-0254,17:44:01.429,23.394492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0256,17:44:01.429,23.394516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0257-0256,17:44:01.431,23.396491 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0258,17:44:01.432,23.396887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0259-0258,17:44:01.432,23.397492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0260,17:44:01.432,23.397515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0261-0260,17:44:01.434,23.399492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0262,17:44:01.435,23.399888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0263-0262,17:44:01.435,23.400492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0264,17:44:01.435,23.400515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0265-0264,17:44:01.437,23.402492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0266,17:44:01.438,23.402893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0267-0266,17:44:01.438,23.403492 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0268,17:44:01.438,23.403517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0269-0268,17:44:01.440,23.405492 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0270,17:44:01.441,23.405888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0271-0270,17:44:01.441,23.406492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0272,17:44:01.441,23.406515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0273-0272,17:44:01.443,23.408491 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0274,17:44:01.444,23.408912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0275-0274,17:44:01.444,23.409490 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0276,17:44:01.444,23.409520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0277-0276,17:44:01.446,23.411489 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0278,17:44:01.447,23.411894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0279-0278,17:44:01.447,23.412492 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0280,17:44:01.447,23.412516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0281-0280,17:44:01.449,23.414492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0282,17:44:01.450,23.414888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0283-0282,17:44:01.450,23.415491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0284,17:44:01.450,23.415515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0285-0284,17:44:01.452,23.417492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0286,17:44:01.453,23.417888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0287-0286,17:44:01.453,23.418491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0288,17:44:01.453,23.418514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0289-0288,17:44:01.455,23.420492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0290,17:44:01.456,23.420890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0291-0290,17:44:01.456,23.421491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0292,17:44:01.456,23.421515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0293-0292,17:44:01.458,23.423496 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0294,17:44:01.459,23.423889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0295-0294,17:44:01.459,23.424492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0296,17:44:01.459,23.424515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0297-0296,17:44:01.461,23.426492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0298,17:44:01.462,23.426888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0299-0298,17:44:01.462,23.427491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0300,17:44:01.462,23.427515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0301-0300,17:44:01.464,23.429492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0302,17:44:01.465,23.429892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0303-0302,17:44:01.465,23.430491 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0304,17:44:01.465,23.430516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0305-0304,17:44:01.467,23.432491 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0306,17:44:01.468,23.432889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0307-0306,17:44:01.468,23.433491 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0308,17:44:01.468,23.433514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0309-0308,17:44:01.470,23.435492 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0310,17:44:01.471,23.435891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0311-0310,17:44:01.471,23.436491 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0312,17:44:01.471,23.436516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0313-0312,17:44:01.473,23.438493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0314,17:44:01.474,23.438890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0315-0314,17:44:01.474,23.439491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0316,17:44:01.474,23.439516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0317-0316,17:44:01.476,23.441492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0318,17:44:01.477,23.441894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0319-0318,17:44:01.477,23.442492 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0320,17:44:01.477,23.442516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0321-0320,17:44:01.479,23.444490 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0322,17:44:01.480,23.444892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0323-0322,17:44:01.480,23.445491 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0324,17:44:01.480,23.445514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0325-0324,17:44:01.482,23.447492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0326,17:44:01.483,23.447889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0327-0326,17:44:01.483,23.448490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0328,17:44:01.483,23.448514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0329-0328,17:44:01.485,23.450491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0330,17:44:01.486,23.450892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0331-0330,17:44:01.486,23.451490 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0332,17:44:01.486,23.451514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0333-0332,17:44:01.488,23.453491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0334,17:44:01.489,23.453892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0335-0334,17:44:01.489,23.454492 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0336,17:44:01.489,23.454516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0337-0336,17:44:01.491,23.456490 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0338,17:44:01.492,23.456889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0339-0338,17:44:01.492,23.457494 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0340,17:44:01.492,23.457517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0341-0340,17:44:01.494,23.459491 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0342,17:44:01.495,23.459889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0343-0342,17:44:01.495,23.460490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0344,17:44:01.495,23.460513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0345-0344,17:44:01.497,23.462490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0346,17:44:01.498,23.462889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0347-0346,17:44:01.498,23.463490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0348,17:44:01.498,23.463514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0349-0348,17:44:01.500,23.465491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0350,17:44:01.501,23.465890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0351-0350,17:44:01.501,23.466491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0352,17:44:01.501,23.466514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0353-0352,17:44:01.503,23.468491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0354,17:44:01.504,23.468891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0355-0354,17:44:01.504,23.469490 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0356,17:44:01.504,23.469513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0357-0356,17:44:01.506,23.471493 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0358,17:44:01.507,23.471897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0359-0358,17:44:01.507,23.472491 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0360,17:44:01.507,23.472516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0361-0360,17:44:01.509,23.474490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0362,17:44:01.510,23.474890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0363-0362,17:44:01.510,23.475490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0364,17:44:01.510,23.475514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0365-0364,17:44:01.512,23.477491 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0366,17:44:01.513,23.477891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0367-0366,17:44:01.513,23.478490 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0368,17:44:01.513,23.478514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0369-0368,17:44:01.515,23.480491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0370,17:44:01.516,23.480890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0371-0370,17:44:01.516,23.481490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0372,17:44:01.516,23.481514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0373-0372,17:44:01.518,23.483491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0374,17:44:01.519,23.483891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0375-0374,17:44:01.519,23.484490 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0376,17:44:01.519,23.484515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0377-0376,17:44:01.521,23.486490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0378,17:44:01.522,23.486890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0379-0378,17:44:01.522,23.487490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0380,17:44:01.522,23.487514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0381-0380,17:44:01.524,23.489490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0382,17:44:01.525,23.489894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0383-0382,17:44:01.525,23.490491 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0384,17:44:01.525,23.490515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0385-0384,17:44:01.527,23.492490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0386,17:44:01.528,23.492891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0387-0386,17:44:01.528,23.493489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0388,17:44:01.528,23.493513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0389-0388,17:44:01.530,23.495490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0390,17:44:01.531,23.495891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0391-0390,17:44:01.531,23.496489 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0392,17:44:01.531,23.496513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0393-0392,17:44:01.533,23.498490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0394,17:44:01.534,23.498891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0395-0394,17:44:01.534,23.499489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0396,17:44:01.534,23.499513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0397-0396,17:44:01.536,23.501506 s,1.992 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0398,17:44:01.537,23.501906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0399-0398,17:44:01.537,23.502503 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0400,17:44:01.537,23.502536 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0401-0400,17:44:01.539,23.504496 s,1.960 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0402,17:44:01.540,23.504897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0403-0402,17:44:01.540,23.505490 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0404,17:44:01.540,23.505514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0405-0404,17:44:01.542,23.507490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0406,17:44:01.543,23.507891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0407-0406,17:44:01.543,23.508489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0408,17:44:01.543,23.508513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0409-0408,17:44:01.545,23.510491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0410,17:44:01.546,23.510917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0411-0410,17:44:01.546,23.511487 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0412,17:44:01.546,23.511515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0413-0412,17:44:01.548,23.513484 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0414,17:44:01.549,23.513914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0415-0414,17:44:01.549,23.514487 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0416,17:44:01.549,23.514515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0417-0416,17:44:01.551,23.516490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0418,17:44:01.552,23.516893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0419-0418,17:44:01.552,23.517489 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0420,17:44:01.552,23.517513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0421-0420,17:44:01.554,23.519493 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0422,17:44:01.555,23.519892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0423-0422,17:44:01.555,23.520491 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0424,17:44:01.555,23.520514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0425-0424,17:44:01.557,23.522490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0426,17:44:01.558,23.522894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0427-0426,17:44:01.558,23.523489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0428,17:44:01.558,23.523513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0429-0428,17:44:01.560,23.525489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0430,17:44:01.561,23.525892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0431-0430,17:44:01.561,23.526489 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0432,17:44:01.561,23.526513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0433-0432,17:44:01.563,23.528490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0434,17:44:01.564,23.528894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0435-0434,17:44:01.564,23.529489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0436,17:44:01.564,23.529514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0437-0436,17:44:01.566,23.531489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0438,17:44:01.567,23.531899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0439-0438,17:44:01.567,23.532489 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0440,17:44:01.567,23.532514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0441-0440,17:44:01.569,23.534489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0442,17:44:01.570,23.534893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0443-0442,17:44:01.570,23.535490 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0444,17:44:01.570,23.535513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0445-0444,17:44:01.572,23.537489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0446,17:44:01.573,23.537899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0447-0446,17:44:01.573,23.538489 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0448,17:44:01.573,23.538513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0449-0448,17:44:01.575,23.540489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0450,17:44:01.576,23.540893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0451-0450,17:44:01.576,23.541488 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0452,17:44:01.576,23.541511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0453-0452,17:44:01.578,23.543489 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0454,17:44:01.579,23.543893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0455-0454,17:44:01.579,23.544489 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0456,17:44:01.579,23.544513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0457-0456,17:44:01.581,23.546491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0458,17:44:01.582,23.546895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0459-0458,17:44:01.582,23.547488 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0460,17:44:01.582,23.547512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0461-0460,17:44:01.584,23.549489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0462,17:44:01.585,23.549896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0463-0462,17:44:01.585,23.550490 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0464,17:44:01.585,23.550514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0465-0464,17:44:01.587,23.552489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0466,17:44:01.588,23.552894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0467-0466,17:44:01.588,23.553491 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0468,17:44:01.588,23.553515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0469-0468,17:44:01.590,23.555488 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0470,17:44:01.591,23.555918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8007DE2010h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0471-0470,17:44:01.591,23.556484 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8007DE2010h,Success (Success)\r
-URB,0472,17:44:01.591,23.556512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0473-0472,17:44:01.593,23.558529 s,2.017 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0474,17:44:01.594,23.558897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0475-0474,17:44:01.594,23.559500 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0476,17:44:01.594,23.559530 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0477-0476,17:44:01.596,23.561491 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0478,17:44:01.597,23.561907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0479-0478,17:44:01.597,23.562488 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0480,17:44:01.597,23.562513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0481-0480,17:44:01.599,23.564489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0482,17:44:01.600,23.564895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0483-0482,17:44:01.600,23.565492 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0484,17:44:01.600,23.565517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0485-0484,17:44:01.602,23.567488 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0486,17:44:01.603,23.567894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0487-0486,17:44:01.603,23.568488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0488,17:44:01.603,23.568512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0489-0488,17:44:01.605,23.570493 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0490,17:44:01.606,23.570895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0491-0490,17:44:01.606,23.571489 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0492,17:44:01.606,23.571514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0493-0492,17:44:01.608,23.573489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0494,17:44:01.609,23.573900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0495-0494,17:44:01.609,23.574489 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0496,17:44:01.609,23.574513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0497-0496,17:44:01.611,23.576489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0498,17:44:01.612,23.576894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0499-0498,17:44:01.612,23.577488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0500,17:44:01.612,23.577511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0501-0500,17:44:01.614,23.579490 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0502,17:44:01.615,23.579894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0503-0502,17:44:01.615,23.580489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0504,17:44:01.615,23.580512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0505-0504,17:44:01.617,23.582489 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0506,17:44:01.618,23.582894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0507-0506,17:44:01.618,23.583489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0508,17:44:01.618,23.583512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0509-0508,17:44:01.620,23.585489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0510,17:44:01.621,23.585894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0511-0510,17:44:01.621,23.586488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0512,17:44:01.621,23.586511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0513-0512,17:44:01.623,23.588488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0514,17:44:01.624,23.588898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0515-0514,17:44:01.624,23.589488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0516,17:44:01.624,23.589512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0517-0516,17:44:01.626,23.591487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0518,17:44:01.627,23.591900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0519-0518,17:44:01.627,23.592489 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0520,17:44:01.627,23.592513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0521-0520,17:44:01.629,23.594488 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0522,17:44:01.630,23.594894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0523-0522,17:44:01.630,23.595488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0524,17:44:01.630,23.595511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0525-0524,17:44:01.632,23.597487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0526,17:44:01.633,23.597894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0527-0526,17:44:01.633,23.598488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0528,17:44:01.633,23.598512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0529-0528,17:44:01.635,23.600490 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0530,17:44:01.636,23.600905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0531-0530,17:44:01.636,23.601502 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0532,17:44:01.636,23.601530 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0533-0532,17:44:01.638,23.603487 s,1.957 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0534,17:44:01.639,23.603897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0535-0534,17:44:01.639,23.604488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0536,17:44:01.639,23.604512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0537-0536,17:44:01.641,23.606489 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0538,17:44:01.642,23.606897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0539-0538,17:44:01.642,23.607488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0540,17:44:01.642,23.607512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0541-0540,17:44:01.644,23.609487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0542,17:44:01.645,23.609899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0543-0542,17:44:01.645,23.610488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0544,17:44:01.645,23.610513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0545-0544,17:44:01.647,23.612487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0546,17:44:01.648,23.612896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0547-0546,17:44:01.648,23.613490 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0548,17:44:01.648,23.613514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0549-0548,17:44:01.650,23.615488 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0550,17:44:01.651,23.615895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0551-0550,17:44:01.651,23.616488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0552,17:44:01.651,23.616511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0553-0552,17:44:01.653,23.618488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0554,17:44:01.654,23.618896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0555-0554,17:44:01.654,23.619487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0556,17:44:01.654,23.619511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0557-0556,17:44:01.656,23.621487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0558,17:44:01.657,23.621901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0559-0558,17:44:01.657,23.622487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0560,17:44:01.657,23.622511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0561-0560,17:44:01.659,23.624488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0562,17:44:01.660,23.624895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0563-0562,17:44:01.660,23.625488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0564,17:44:01.660,23.625511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0565-0564,17:44:01.662,23.627489 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0566,17:44:01.663,23.627896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0567-0566,17:44:01.663,23.628487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0568,17:44:01.663,23.628510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0569-0568,17:44:01.665,23.630488 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0570,17:44:01.666,23.630898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0571-0570,17:44:01.666,23.631488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0572,17:44:01.666,23.631512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0573-0572,17:44:01.668,23.633487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0574,17:44:01.669,23.633896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0575-0574,17:44:01.669,23.634487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0576,17:44:01.669,23.634511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0577-0576,17:44:01.671,23.636487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0578,17:44:01.672,23.636896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0579-0578,17:44:01.672,23.637489 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0580,17:44:01.672,23.637512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0581-0580,17:44:01.674,23.639488 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0582,17:44:01.675,23.639897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0583-0582,17:44:01.675,23.640488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0584,17:44:01.675,23.640511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0585-0584,17:44:01.677,23.642487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0586,17:44:01.678,23.642896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0587-0586,17:44:01.678,23.643487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0588,17:44:01.678,23.643510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0589-0588,17:44:01.680,23.645487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0590,17:44:01.681,23.645896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0591-0590,17:44:01.681,23.646487 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0592,17:44:01.681,23.646510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0593-0592,17:44:01.683,23.648487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0594,17:44:01.684,23.648899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0595-0594,17:44:01.684,23.649487 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0596,17:44:01.684,23.649511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0597-0596,17:44:01.686,23.651487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0598,17:44:01.687,23.651901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0599-0598,17:44:01.687,23.652487 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0600,17:44:01.687,23.652510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0601-0600,17:44:01.689,23.654489 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0602,17:44:01.690,23.654899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0603-0602,17:44:01.690,23.655490 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0604,17:44:01.690,23.655514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0605-0604,17:44:01.692,23.657487 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0606,17:44:01.693,23.657898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0607-0606,17:44:01.693,23.658488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0608,17:44:01.693,23.658511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0609-0608,17:44:01.695,23.660486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0610,17:44:01.696,23.660897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0611-0610,17:44:01.696,23.661486 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0612,17:44:01.696,23.661510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0613-0612,17:44:01.698,23.663487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0614,17:44:01.699,23.663899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0615-0614,17:44:01.699,23.664486 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0616,17:44:01.699,23.664511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0617-0616,17:44:01.701,23.666486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0618,17:44:01.702,23.666898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0619-0618,17:44:01.702,23.667486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0620,17:44:01.702,23.667510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0621-0620,17:44:01.704,23.669490 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0622,17:44:01.705,23.669901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0623-0622,17:44:01.705,23.670487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0624,17:44:01.705,23.670512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0625-0624,17:44:01.707,23.672487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0626,17:44:01.708,23.672898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0627-0626,17:44:01.708,23.673487 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0628,17:44:01.708,23.673510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0629-0628,17:44:01.710,23.675486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0630,17:44:01.711,23.675898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0631-0630,17:44:01.711,23.676487 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0632,17:44:01.711,23.676510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0633-0632,17:44:01.713,23.678487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0634,17:44:01.714,23.678898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0635-0634,17:44:01.714,23.679486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0636,17:44:01.714,23.679510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0637-0636,17:44:01.716,23.681486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0638,17:44:01.717,23.681904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0639-0638,17:44:01.717,23.682486 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0640,17:44:01.717,23.682510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0641-0640,17:44:01.719,23.684485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0642,17:44:01.720,23.684898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0643-0642,17:44:01.720,23.685486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0644,17:44:01.720,23.685510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0645-0644,17:44:01.722,23.687486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0646,17:44:01.723,23.687898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0647-0646,17:44:01.723,23.688486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0648,17:44:01.723,23.688510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0649-0648,17:44:01.725,23.690486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0650,17:44:01.726,23.690901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0651-0650,17:44:01.726,23.691486 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0652,17:44:01.726,23.691509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0653-0652,17:44:01.728,23.693486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0654,17:44:01.729,23.693898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0655-0654,17:44:01.729,23.694486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0656,17:44:01.729,23.694510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0657-0656,17:44:01.731,23.696486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0658,17:44:01.732,23.696899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0659-0658,17:44:01.732,23.697486 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0660,17:44:01.732,23.697509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0661-0660,17:44:01.734,23.699487 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0662,17:44:01.735,23.699900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0663-0662,17:44:01.735,23.700486 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0664,17:44:01.735,23.700512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0665-0664,17:44:01.737,23.702486 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0666,17:44:01.738,23.702899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0667-0666,17:44:01.738,23.703490 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0668,17:44:01.738,23.703514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0669-0668,17:44:01.740,23.705486 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0670,17:44:01.741,23.705899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0671-0670,17:44:01.741,23.706487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0672,17:44:01.741,23.706511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0673-0672,17:44:01.743,23.708486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0674,17:44:01.744,23.708904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0675-0674,17:44:01.744,23.709488 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0676,17:44:01.744,23.709515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0677-0676,17:44:01.746,23.711487 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0678,17:44:01.747,23.711906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0679-0678,17:44:01.747,23.712491 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0680,17:44:01.747,23.712520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0681-0680,17:44:01.749,23.714489 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0682,17:44:01.750,23.714913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0683-0682,17:44:01.750,23.715487 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0684,17:44:01.750,23.715516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0685-0684,17:44:01.752,23.717495 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0686,17:44:01.753,23.717908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0687-0686,17:44:01.753,23.718488 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0688,17:44:01.753,23.718516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0689-0688,17:44:01.755,23.720485 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0690,17:44:01.756,23.720912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0691-0690,17:44:01.756,23.721490 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0692,17:44:01.756,23.721516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0693-0692,17:44:01.758,23.723484 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0694,17:44:01.759,23.723901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0695-0694,17:44:01.759,23.724485 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0696,17:44:01.759,23.724508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0697-0696,17:44:01.761,23.726486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0698,17:44:01.762,23.726899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0699-0698,17:44:01.762,23.727485 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0700,17:44:01.762,23.727508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0701-0700,17:44:01.764,23.729487 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0702,17:44:01.765,23.729910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0703-0702,17:44:01.765,23.730486 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0704,17:44:01.765,23.730512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0705-0704,17:44:01.767,23.732485 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0706,17:44:01.768,23.732900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0707-0706,17:44:01.768,23.733485 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0708,17:44:01.768,23.733509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0709-0708,17:44:01.770,23.735486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0710,17:44:01.771,23.735900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0711-0710,17:44:01.771,23.736489 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0712,17:44:01.771,23.736512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0713-0712,17:44:01.773,23.738485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0714,17:44:01.774,23.738900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0715-0714,17:44:01.774,23.739485 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0716,17:44:01.774,23.739508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0717-0716,17:44:01.776,23.741485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0718,17:44:01.777,23.741907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0719-0718,17:44:01.777,23.742485 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0720,17:44:01.777,23.742509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0721-0720,17:44:01.779,23.744486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0722,17:44:01.780,23.744906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0723-0722,17:44:01.780,23.745486 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0724,17:44:01.780,23.745512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0725-0724,17:44:01.782,23.747486 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0726,17:44:01.783,23.747908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0727-0726,17:44:01.783,23.748485 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0728,17:44:01.783,23.748511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0729-0728,17:44:01.785,23.750485 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0730,17:44:01.786,23.750906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0731-0730,17:44:01.786,23.751486 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0732,17:44:01.786,23.751510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0733-0732,17:44:01.788,23.753485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0734,17:44:01.789,23.753901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0735-0734,17:44:01.789,23.754484 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0736,17:44:01.789,23.754507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0737-0736,17:44:01.791,23.756487 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0738,17:44:01.792,23.756901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0739-0738,17:44:01.792,23.757484 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0740,17:44:01.792,23.757508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0741-0740,17:44:01.794,23.759485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0742,17:44:01.795,23.759904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0743-0742,17:44:01.795,23.760485 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0744,17:44:01.795,23.760509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0745-0744,17:44:01.797,23.762486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0746,17:44:01.798,23.762904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0747-0746,17:44:01.798,23.763484 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0748,17:44:01.798,23.763508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0749-0748,17:44:01.800,23.765484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0750,17:44:01.801,23.765902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0751-0750,17:44:01.801,23.766529 s,627 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0752,17:44:01.801,23.766553 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0753-0752,17:44:01.803,23.768492 s,1.939 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0754,17:44:01.804,23.768914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0755-0754,17:44:01.804,23.769490 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0756,17:44:01.804,23.769519 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0757-0756,17:44:01.806,23.771485 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0758,17:44:01.807,23.771909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0759-0758,17:44:01.807,23.772484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0760,17:44:01.807,23.772508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0761-0760,17:44:01.809,23.774486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0762,17:44:01.810,23.774901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0763-0762,17:44:01.810,23.775487 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0764,17:44:01.810,23.775511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0765-0764,17:44:01.812,23.777486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0766,17:44:01.813,23.777906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0767-0766,17:44:01.813,23.778486 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0768,17:44:01.813,23.778511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0769-0768,17:44:01.815,23.780484 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0770,17:44:01.816,23.780907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0771-0770,17:44:01.816,23.781485 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0772,17:44:01.816,23.781508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0773-0772,17:44:01.818,23.783486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0774,17:44:01.819,23.783904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0775-0774,17:44:01.819,23.784486 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0776,17:44:01.819,23.784509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0777-0776,17:44:01.821,23.786485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0778,17:44:01.822,23.786902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0779-0778,17:44:01.822,23.787483 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0780,17:44:01.822,23.787507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0781-0780,17:44:01.824,23.789485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0782,17:44:01.825,23.789906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0783-0782,17:44:01.825,23.790484 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0784,17:44:01.825,23.790509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0785-0784,17:44:01.827,23.792485 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0786,17:44:01.828,23.792902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0787-0786,17:44:01.828,23.793484 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0788,17:44:01.828,23.793508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0789-0788,17:44:01.830,23.795484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0790,17:44:01.831,23.795902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0791-0790,17:44:01.831,23.796484 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0792,17:44:01.831,23.796508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0793-0792,17:44:01.833,23.798484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0794,17:44:01.834,23.798902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0795-0794,17:44:01.834,23.799485 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0796,17:44:01.834,23.799509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0797-0796,17:44:01.836,23.801485 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0798,17:44:01.837,23.801908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0799-0798,17:44:01.837,23.802484 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0800,17:44:01.837,23.802508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0801-0800,17:44:01.839,23.804483 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0802,17:44:01.840,23.804903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0803-0802,17:44:01.840,23.805484 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0804,17:44:01.840,23.805507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0805-0804,17:44:01.842,23.807488 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0806,17:44:01.843,23.807910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0807-0806,17:44:01.843,23.808486 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0808,17:44:01.843,23.808511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0809-0808,17:44:01.845,23.810485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0810,17:44:01.846,23.810909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0811-0810,17:44:01.846,23.811484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0812,17:44:01.846,23.811508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0813-0812,17:44:01.848,23.813484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0814,17:44:01.849,23.813904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0815-0814,17:44:01.849,23.814485 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0816,17:44:01.849,23.814508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0817-0816,17:44:01.851,23.816484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0818,17:44:01.852,23.816905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0819-0818,17:44:01.852,23.817483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0820,17:44:01.852,23.817508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0821-0820,17:44:01.854,23.819484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0822,17:44:01.855,23.819903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0823-0822,17:44:01.855,23.820483 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0824,17:44:01.855,23.820507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0825-0824,17:44:01.857,23.822484 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0826,17:44:01.858,23.822903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0827-0826,17:44:01.858,23.823483 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0828,17:44:01.858,23.823506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0829-0828,17:44:01.860,23.825487 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0830,17:44:01.861,23.825922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0831-0830,17:44:01.861,23.826480 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0832,17:44:01.861,23.826509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0833-0832,17:44:01.863,23.828476 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0834,17:44:01.864,23.828919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0835-0834,17:44:01.864,23.829481 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0836,17:44:01.864,23.829508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0837-0836,17:44:01.866,23.831484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0838,17:44:01.867,23.831911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0839-0838,17:44:01.867,23.832483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0840,17:44:01.867,23.832507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0841-0840,17:44:01.869,23.834484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0842,17:44:01.870,23.834905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0843-0842,17:44:01.870,23.835483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0844,17:44:01.870,23.835506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0845-0844,17:44:01.872,23.837484 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0846,17:44:01.873,23.837910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0847-0846,17:44:01.873,23.838484 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0848,17:44:01.873,23.838508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0849-0848,17:44:01.875,23.840485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0850,17:44:01.876,23.840907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0851-0850,17:44:01.876,23.841479 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0852,17:44:01.876,23.841506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0853-0852,17:44:01.878,23.843476 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0854,17:44:01.879,23.843916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0855-0854,17:44:01.879,23.844485 s,568 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0856,17:44:01.879,23.844511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0857-0856,17:44:01.881,23.846483 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0858,17:44:01.882,23.846906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0859-0858,17:44:01.882,23.847482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0860,17:44:01.882,23.847507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0861-0860,17:44:01.884,23.849485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0862,17:44:01.885,23.849911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0863-0862,17:44:01.885,23.850482 s,571 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0864,17:44:01.885,23.850508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0865-0864,17:44:01.887,23.852483 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0866,17:44:01.888,23.852905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0867-0866,17:44:01.888,23.853482 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0868,17:44:01.888,23.853507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0869-0868,17:44:01.890,23.855484 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0870,17:44:01.891,23.855908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0871-0870,17:44:01.891,23.856483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0872,17:44:01.891,23.856507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0873-0872,17:44:01.893,23.858485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0874,17:44:01.894,23.858905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0875-0874,17:44:01.894,23.859483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0876,17:44:01.894,23.859506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0877-0876,17:44:01.896,23.861483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0878,17:44:01.897,23.861910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0879-0878,17:44:01.897,23.862483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0880,17:44:01.897,23.862506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0881-0880,17:44:01.899,23.864482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0882,17:44:01.900,23.864904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0883-0882,17:44:01.900,23.865483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0884,17:44:01.900,23.865506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0885-0884,17:44:01.902,23.867483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0886,17:44:01.903,23.867905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0887-0886,17:44:01.903,23.868482 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0888,17:44:01.903,23.868506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0889-0888,17:44:01.905,23.870518 s,2.013 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0890,17:44:01.906,23.870911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0891-0890,17:44:01.906,23.871488 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0892,17:44:01.906,23.871517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0893-0892,17:44:01.908,23.873487 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0894,17:44:01.909,23.873914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0895-0894,17:44:01.909,23.874486 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0896,17:44:01.909,23.874513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0897-0896,17:44:01.911,23.876488 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0898,17:44:01.912,23.876909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0899-0898,17:44:01.912,23.877482 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0900,17:44:01.912,23.877506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0901-0900,17:44:01.914,23.879483 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0902,17:44:01.915,23.879906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0903-0902,17:44:01.915,23.880482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0904,17:44:01.915,23.880505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0905-0904,17:44:01.917,23.882483 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0906,17:44:01.918,23.882910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0907-0906,17:44:01.918,23.883483 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0908,17:44:01.918,23.883506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0909-0908,17:44:01.920,23.885483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0910,17:44:01.921,23.885906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0911-0910,17:44:01.921,23.886482 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0912,17:44:01.921,23.886505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0913-0912,17:44:01.923,23.888483 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0914,17:44:01.924,23.888907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0915-0914,17:44:01.924,23.889483 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0916,17:44:01.924,23.889508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0917-0916,17:44:01.926,23.891482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0918,17:44:01.927,23.891913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0919-0918,17:44:01.927,23.892482 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0920,17:44:01.927,23.892506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0921-0920,17:44:01.929,23.894483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0922,17:44:01.930,23.894906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0923-0922,17:44:01.930,23.895483 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0924,17:44:01.930,23.895507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0925-0924,17:44:01.932,23.897482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0926,17:44:01.933,23.897906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0927-0926,17:44:01.933,23.898482 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0928,17:44:01.933,23.898506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0929-0928,17:44:01.935,23.900482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0930,17:44:01.936,23.900906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0931-0930,17:44:01.936,23.901482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0932,17:44:01.936,23.901506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0933-0932,17:44:01.938,23.903482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0934,17:44:01.939,23.903906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0935-0934,17:44:01.939,23.904482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0936,17:44:01.939,23.904506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0937-0936,17:44:01.941,23.906483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0938,17:44:01.942,23.906906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0939-0938,17:44:01.942,23.907482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0940,17:44:01.942,23.907506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0941-0940,17:44:01.944,23.909481 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0942,17:44:01.945,23.909909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0943-0942,17:44:01.945,23.910513 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0944,17:44:01.945,23.910539 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0945-0944,17:44:01.947,23.912487 s,1.948 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0946,17:44:01.948,23.912912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0947-0946,17:44:01.948,23.913485 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0948,17:44:01.948,23.913512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0949-0948,17:44:01.950,23.915486 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0950,17:44:01.951,23.915911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0951-0950,17:44:01.951,23.916481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0952,17:44:01.951,23.916506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0953-0952,17:44:01.953,23.918507 s,2.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0954,17:44:01.954,23.918910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0955-0954,17:44:01.954,23.919487 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0956,17:44:01.954,23.919513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0957-0956,17:44:01.956,23.921482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0958,17:44:01.957,23.921915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0959-0958,17:44:01.957,23.922481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0960,17:44:01.957,23.922506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0961-0960,17:44:01.959,23.924482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0962,17:44:01.960,23.924910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0963-0962,17:44:01.960,23.925483 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0964,17:44:01.960,23.925509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0965-0964,17:44:01.961,23.926505 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0966,17:44:01.962,23.926908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0967-0966,17:44:01.962,23.927483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0968,17:44:01.962,23.927509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0969-0968,17:44:01.964,23.929482 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0970,17:44:01.965,23.929915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0971-0970,17:44:01.965,23.930482 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0972,17:44:01.965,23.930508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0973-0972,17:44:01.967,23.932481 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0974,17:44:01.968,23.932908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0975-0974,17:44:01.968,23.933481 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0976,17:44:01.968,23.933504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0977-0976,17:44:01.969,23.934505 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0978,17:44:01.970,23.934910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0979-0978,17:44:01.970,23.935488 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0980,17:44:01.970,23.935515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0981-0980,17:44:01.972,23.937484 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0982,17:44:01.973,23.937918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0983-0982,17:44:01.973,23.938482 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0984,17:44:01.973,23.938507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0985-0984,17:44:01.975,23.940482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0986,17:44:01.976,23.940910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0987-0986,17:44:01.976,23.941484 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0988,17:44:01.976,23.941508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0989-0988,17:44:01.977,23.942504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0990,17:44:01.978,23.942909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0991-0990,17:44:01.978,23.943484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0992,17:44:01.978,23.943509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0993-0992,17:44:01.980,23.945482 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0994,17:44:01.981,23.945910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0995-0994,17:44:01.981,23.946481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,0996,17:44:01.981,23.946505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0997-0996,17:44:01.983,23.948481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,0998,17:44:01.984,23.948909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0999-0998,17:44:01.984,23.949481 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1000,17:44:01.984,23.949505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1001-1000,17:44:01.985,23.950503 s,998 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1002,17:44:01.986,23.950914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1003-1002,17:44:01.986,23.951485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1004,17:44:01.986,23.951513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1005-1004,17:44:01.988,23.953482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1006,17:44:01.989,23.953911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1007-1006,17:44:01.989,23.954481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1008,17:44:01.989,23.954505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1009-1008,17:44:01.991,23.956480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1010,17:44:01.992,23.956908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1011-1010,17:44:01.992,23.957484 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1012,17:44:01.992,23.957508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1013-1012,17:44:01.993,23.958504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1014,17:44:01.994,23.958909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1015-1014,17:44:01.994,23.959485 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1016,17:44:01.994,23.959510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1017-1016,17:44:01.996,23.961481 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1018,17:44:01.997,23.961911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1019-1018,17:44:01.997,23.962481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1020,17:44:01.997,23.962505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1021-1020,17:44:01.999,23.964481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1022,17:44:02.000,23.964908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1023-1022,17:44:02.000,23.965481 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1024,17:44:02.000,23.965504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1025-1024,17:44:02.001,23.966505 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1026,17:44:02.002,23.966909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1027-1026,17:44:02.002,23.967484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1028,17:44:02.002,23.967509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1029-1028,17:44:02.004,23.969482 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1030,17:44:02.005,23.969919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1031-1030,17:44:02.005,23.970480 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1032,17:44:02.005,23.970505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1033-1032,17:44:02.007,23.972481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1034,17:44:02.008,23.972909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1035-1034,17:44:02.008,23.973483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1036,17:44:02.008,23.973507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1037-1036,17:44:02.009,23.974504 s,997 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1038,17:44:02.010,23.974911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1039-1038,17:44:02.010,23.975484 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1040,17:44:02.010,23.975511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1041-1040,17:44:02.012,23.977482 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1042,17:44:02.013,23.977912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1043-1042,17:44:02.013,23.978480 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1044,17:44:02.013,23.978504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1045-1044,17:44:02.015,23.980481 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1046,17:44:02.016,23.980914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1047-1046,17:44:02.016,23.981481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1048,17:44:02.016,23.981506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1049-1048,17:44:02.017,23.982505 s,1000 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1050,17:44:02.018,23.982911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1051-1050,17:44:02.018,23.983486 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1052,17:44:02.018,23.983513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1053-1052,17:44:02.020,23.985482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1054,17:44:02.021,23.985915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1055-1054,17:44:02.021,23.986480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1056,17:44:02.021,23.986505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1057-1056,17:44:02.023,23.988480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1058,17:44:02.024,23.988911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1059-1058,17:44:02.024,23.989483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1060,17:44:02.024,23.989508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1061-1060,17:44:02.025,23.990504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1062,17:44:02.026,23.990912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1063-1062,17:44:02.026,23.991487 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1064,17:44:02.026,23.991515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1065-1064,17:44:02.028,23.993482 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1066,17:44:02.029,23.993913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1067-1066,17:44:02.029,23.994480 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1068,17:44:02.029,23.994504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1069-1068,17:44:02.031,23.996480 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1070,17:44:02.032,23.996910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1071-1070,17:44:02.032,23.997480 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1072,17:44:02.032,23.997503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1073-1072,17:44:02.033,23.998504 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1074,17:44:02.034,23.998910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1075-1074,17:44:02.034,23.999484 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1076,17:44:02.034,23.999510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1077-1076,17:44:02.036,24.001489 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1078,17:44:02.037,24.001970 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1079-1078,17:44:02.037,24.002479 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
-URB,1080,17:44:02.037,24.002521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1081-1080,17:44:02.039,24.004477 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1082,17:44:02.040,24.004914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1083-1082,17:44:02.040,24.005485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1084,17:44:02.040,24.005510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1085-1084,17:44:02.041,24.006513 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1086,17:44:02.042,24.006912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1087-1086,17:44:02.042,24.007486 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1088,17:44:02.042,24.007513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1089-1088,17:44:02.044,24.009483 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1090,17:44:02.045,24.009923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1091-1090,17:44:02.045,24.010480 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1092,17:44:02.045,24.010506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1093-1092,17:44:02.047,24.012481 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1094,17:44:02.048,24.012915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1095-1094,17:44:02.048,24.013481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1096,17:44:02.048,24.013506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1097-1096,17:44:02.049,24.014511 s,1.005 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1098,17:44:02.050,24.014915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1099-1098,17:44:02.050,24.015483 s,568 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1100,17:44:02.050,24.015508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1101-1100,17:44:02.052,24.017482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1102,17:44:02.053,24.017913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1103-1102,17:44:02.053,24.018478 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1104,17:44:02.053,24.018502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1105-1104,17:44:02.055,24.020484 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1106,17:44:02.056,24.020913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1107-1106,17:44:02.056,24.021480 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1108,17:44:02.056,24.021504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1109-1108,17:44:02.057,24.022503 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1110,17:44:02.058,24.022912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1111-1110,17:44:02.058,24.023485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1112,17:44:02.058,24.023513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1113-1112,17:44:02.060,24.025485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1114,17:44:02.061,24.025922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1115-1114,17:44:02.061,24.026479 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1116,17:44:02.061,24.026505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1117-1116,17:44:02.063,24.028479 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1118,17:44:02.064,24.028913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1119-1118,17:44:02.064,24.029479 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1120,17:44:02.064,24.029503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1121-1120,17:44:02.065,24.030507 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1122,17:44:02.066,24.030913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1123-1122,17:44:02.066,24.031483 s,571 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1124,17:44:02.066,24.031508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1125-1124,17:44:02.068,24.033482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1126,17:44:02.069,24.033916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1127-1126,17:44:02.069,24.034480 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1128,17:44:02.069,24.034504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1129-1128,17:44:02.071,24.036483 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1130,17:44:02.072,24.036914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1131-1130,17:44:02.072,24.037479 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1132,17:44:02.072,24.037503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1133-1132,17:44:02.073,24.038504 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1134,17:44:02.074,24.038912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1135-1134,17:44:02.074,24.039481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1136,17:44:02.074,24.039508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1137-1136,17:44:02.076,24.041483 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1138,17:44:02.077,24.041921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1139-1138,17:44:02.077,24.042479 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1140,17:44:02.077,24.042505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1141-1140,17:44:02.079,24.044478 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1142,17:44:02.080,24.044913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1143-1142,17:44:02.080,24.045479 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1144,17:44:02.080,24.045504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1145-1144,17:44:02.081,24.046502 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1146,17:44:02.082,24.046913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1147-1146,17:44:02.082,24.047481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1148,17:44:02.082,24.047507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1149-1148,17:44:02.084,24.049479 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1150,17:44:02.085,24.049921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1151-1150,17:44:02.085,24.050478 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1152,17:44:02.085,24.050505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1153-1152,17:44:02.087,24.052479 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1154,17:44:02.088,24.052916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1155-1154,17:44:02.088,24.053479 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1156,17:44:02.088,24.053503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1157-1156,17:44:02.089,24.054503 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1158,17:44:02.090,24.054914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1159-1158,17:44:02.090,24.055484 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1160,17:44:02.090,24.055510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1161-1160,17:44:02.092,24.057479 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1162,17:44:02.093,24.057917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1163-1162,17:44:02.093,24.058478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1164,17:44:02.093,24.058502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1165-1164,17:44:02.095,24.060479 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1166,17:44:02.096,24.060915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1167-1166,17:44:02.096,24.061479 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1168,17:44:02.096,24.061504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1169-1168,17:44:02.097,24.062502 s,998 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1170,17:44:02.098,24.062913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1171-1170,17:44:02.098,24.063482 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1172,17:44:02.098,24.063508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1173-1172,17:44:02.100,24.065480 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1174,17:44:02.101,24.065915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1175-1174,17:44:02.101,24.066478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1176,17:44:02.101,24.066502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1177-1176,17:44:02.103,24.068479 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1178,17:44:02.104,24.068918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1179-1178,17:44:02.104,24.069479 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1180,17:44:02.104,24.069506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1181-1180,17:44:02.105,24.070506 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1182,17:44:02.106,24.070916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1183-1182,17:44:02.106,24.071486 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1184,17:44:02.106,24.071513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1185-1184,17:44:02.108,24.073479 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1186,17:44:02.109,24.073920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1187-1186,17:44:02.109,24.074478 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1188,17:44:02.109,24.074502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1189-1188,17:44:02.111,24.076478 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1190,17:44:02.112,24.076912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1191-1190,17:44:02.112,24.077478 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1192,17:44:02.112,24.077502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1193-1192,17:44:02.113,24.078502 s,1.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1194,17:44:02.114,24.078917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1195-1194,17:44:02.114,24.079482 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1196,17:44:02.114,24.079507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1197-1196,17:44:02.116,24.081480 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1198,17:44:02.117,24.081916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1199-1198,17:44:02.117,24.082479 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1200,17:44:02.117,24.082504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1201-1200,17:44:02.119,24.084478 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1202,17:44:02.120,24.084913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1203-1202,17:44:02.120,24.085478 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1204,17:44:02.120,24.085501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1205-1204,17:44:02.121,24.086502 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1206,17:44:02.122,24.086925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1207-1206,17:44:02.122,24.087482 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1208,17:44:02.122,24.087515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1209-1208,17:44:02.124,24.089479 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1210,17:44:02.125,24.089939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1211-1210,17:44:02.125,24.090481 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1212,17:44:02.125,24.090511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1213-1212,17:44:02.127,24.092478 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1214,17:44:02.128,24.092915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1215-1214,17:44:02.128,24.093479 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1216,17:44:02.128,24.093503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1217-1216,17:44:02.129,24.094510 s,1.007 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1218,17:44:02.130,24.094914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1219-1218,17:44:02.130,24.095481 s,567 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1220,17:44:02.130,24.095508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1221-1220,17:44:02.132,24.097479 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1222,17:44:02.133,24.097918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1223-1222,17:44:02.133,24.098478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1224,17:44:02.133,24.098503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1225-1224,17:44:02.135,24.100478 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1226,17:44:02.136,24.100914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1227-1226,17:44:02.136,24.101478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1228,17:44:02.136,24.101501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1229-1228,17:44:02.137,24.102512 s,1.011 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1230,17:44:02.138,24.102924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1231-1230,17:44:02.138,24.103484 s,559 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1232,17:44:02.138,24.103510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1233-1232,17:44:02.140,24.105481 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1234,17:44:02.141,24.105924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1235-1234,17:44:02.141,24.106478 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1236,17:44:02.141,24.106504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1237-1236,17:44:02.143,24.108478 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1238,17:44:02.144,24.108924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1239-1238,17:44:02.144,24.109482 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1240,17:44:02.144,24.109507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1241-1240,17:44:02.145,24.110507 s,1.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1242,17:44:02.146,24.110915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1243-1242,17:44:02.146,24.111480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1244,17:44:02.146,24.111505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1245-1244,17:44:02.148,24.113480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1246,17:44:02.149,24.113917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1247-1246,17:44:02.149,24.114477 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1248,17:44:02.149,24.114501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1249-1248,17:44:02.151,24.116478 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1250,17:44:02.152,24.116914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1251-1250,17:44:02.152,24.117478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1252,17:44:02.152,24.117501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1253-1252,17:44:02.153,24.118501 s,1000 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1254,17:44:02.154,24.118915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1255-1254,17:44:02.154,24.119481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1256,17:44:02.154,24.119506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1257-1256,17:44:02.156,24.121479 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1258,17:44:02.157,24.121923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1259-1258,17:44:02.157,24.122478 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1260,17:44:02.157,24.122506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1261-1260,17:44:02.159,24.124482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1262,17:44:02.160,24.124918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1263-1262,17:44:02.160,24.125476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1264,17:44:02.160,24.125500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1265-1264,17:44:02.161,24.126501 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1266,17:44:02.162,24.126916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1267-1266,17:44:02.162,24.127480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1268,17:44:02.162,24.127506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1269-1268,17:44:02.164,24.129478 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1270,17:44:02.165,24.129925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1271-1270,17:44:02.165,24.130477 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1272,17:44:02.165,24.130502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1273-1272,17:44:02.167,24.132478 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1274,17:44:02.168,24.132915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1275-1274,17:44:02.168,24.133477 s,562 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1276,17:44:02.168,24.133501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1277-1276,17:44:02.169,24.134503 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1278,17:44:02.170,24.134916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1279-1278,17:44:02.170,24.135482 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1280,17:44:02.170,24.135508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1281-1280,17:44:02.172,24.137480 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1282,17:44:02.173,24.137939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1283-1282,17:44:02.173,24.138479 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1284,17:44:02.173,24.138508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1285-1284,17:44:02.175,24.140477 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1286,17:44:02.176,24.140918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1287-1286,17:44:02.176,24.141476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1288,17:44:02.176,24.141500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1289-1288,17:44:02.177,24.142502 s,1.002 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1290,17:44:02.178,24.142916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1291-1290,17:44:02.178,24.143480 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1292,17:44:02.178,24.143505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1293-1292,17:44:02.180,24.145477 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1294,17:44:02.181,24.145917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1295-1294,17:44:02.181,24.146478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1296,17:44:02.181,24.146502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1297-1296,17:44:02.183,24.148477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1298,17:44:02.184,24.148917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1299-1298,17:44:02.184,24.149477 s,560 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1300,17:44:02.184,24.149502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1301-1300,17:44:02.185,24.150501 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1302,17:44:02.186,24.150917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1303-1302,17:44:02.186,24.151481 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1304,17:44:02.186,24.151506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1305-1304,17:44:02.188,24.153478 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1306,17:44:02.189,24.153919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1307-1306,17:44:02.189,24.154477 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1308,17:44:02.189,24.154502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1309-1308,17:44:02.191,24.156477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1310,17:44:02.192,24.156918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1311-1310,17:44:02.192,24.157477 s,559 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1312,17:44:02.192,24.157502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1313-1312,17:44:02.193,24.158501 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1314,17:44:02.194,24.158917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1315-1314,17:44:02.194,24.159489 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1316,17:44:02.194,24.159523 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1317-1316,17:44:02.196,24.161480 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1318,17:44:02.197,24.161929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1319-1318,17:44:02.197,24.162471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1320,17:44:02.197,24.162494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1321-1320,17:44:02.199,24.164470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1322,17:44:02.200,24.164914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1323-1322,17:44:02.200,24.165470 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1324,17:44:02.200,24.165492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1325-1324,17:44:02.201,24.166510 s,1.018 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1326,17:44:02.202,24.166918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1327-1326,17:44:02.202,24.167473 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1328,17:44:02.202,24.167500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1329-1328,17:44:02.204,24.169485 s,1.986 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1330,17:44:02.205,24.169923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1331-1330,17:44:02.205,24.170474 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1332,17:44:02.205,24.170502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1333-1332,17:44:02.207,24.172477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1334,17:44:02.208,24.172921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1335-1334,17:44:02.208,24.173470 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1336,17:44:02.208,24.173494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1337-1336,17:44:02.209,24.174504 s,1.009 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1338,17:44:02.210,24.174916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1339-1338,17:44:02.210,24.175474 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1340,17:44:02.210,24.175500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1341-1340,17:44:02.212,24.177474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1342,17:44:02.213,24.177917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1343-1342,17:44:02.213,24.178470 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1344,17:44:02.213,24.178493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1345-1344,17:44:02.215,24.180469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1346,17:44:02.216,24.180928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80085419A0h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1347-1346,17:44:02.216,24.181471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80085419A0h,Success (Success)\r
-URB,1348,17:44:02.216,24.181503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1349-1348,17:44:02.217,24.182498 s,994 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1350,17:44:02.218,24.182915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1351-1350,17:44:02.218,24.183472 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1352,17:44:02.218,24.183498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1353-1352,17:44:02.220,24.185472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1354,17:44:02.221,24.185917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1355-1354,17:44:02.221,24.186471 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1356,17:44:02.221,24.186493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1357-1356,17:44:02.223,24.188469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1358,17:44:02.224,24.188916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1359-1358,17:44:02.224,24.189470 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1360,17:44:02.224,24.189494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1361-1360,17:44:02.225,24.190497 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1362,17:44:02.226,24.190916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1363-1362,17:44:02.226,24.191472 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1364,17:44:02.226,24.191497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1365-1364,17:44:02.228,24.193472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1366,17:44:02.229,24.193917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1367-1366,17:44:02.229,24.194470 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1368,17:44:02.229,24.194493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1369-1368,17:44:02.231,24.196469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1370,17:44:02.232,24.196914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1371-1370,17:44:02.232,24.197469 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1372,17:44:02.232,24.197491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1373-1372,17:44:02.233,24.198469 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1374,17:44:02.234,24.198915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1375-1374,17:44:02.234,24.199469 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1376,17:44:02.234,24.199492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1377-1376,17:44:02.236,24.201470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1378,17:44:02.237,24.201917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1379-1378,17:44:02.237,24.202478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1380,17:44:02.237,24.202509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1381-1380,17:44:02.239,24.204473 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1382,17:44:02.240,24.204920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1383-1382,17:44:02.240,24.205471 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1384,17:44:02.240,24.205495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1385-1384,17:44:02.241,24.206505 s,1.010 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1386,17:44:02.242,24.206918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1387-1386,17:44:02.242,24.207493 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1388,17:44:02.242,24.207524 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1389-1388,17:44:02.244,24.209481 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1390,17:44:02.245,24.209930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1391-1390,17:44:02.245,24.210476 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1392,17:44:02.245,24.210503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1393-1392,17:44:02.247,24.212475 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1394,17:44:02.248,24.212919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1395-1394,17:44:02.248,24.213476 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1396,17:44:02.248,24.213499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1397-1396,17:44:02.249,24.214511 s,1.012 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1398,17:44:02.250,24.214919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1399-1398,17:44:02.250,24.215479 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1400,17:44:02.250,24.215505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1401-1400,17:44:02.252,24.217477 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1402,17:44:02.253,24.217922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1403-1402,17:44:02.253,24.218475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1404,17:44:02.253,24.218499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1405-1404,17:44:02.255,24.220476 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1406,17:44:02.256,24.220918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1407-1406,17:44:02.256,24.221476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1408,17:44:02.256,24.221499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1409-1408,17:44:02.257,24.222504 s,1.005 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1410,17:44:02.258,24.222924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1411-1410,17:44:02.258,24.223479 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1412,17:44:02.258,24.223505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1413-1412,17:44:02.260,24.225476 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1414,17:44:02.261,24.225921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1415-1414,17:44:02.261,24.226476 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1416,17:44:02.261,24.226500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1417-1416,17:44:02.263,24.228476 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1418,17:44:02.264,24.228922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1419-1418,17:44:02.264,24.229479 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1420,17:44:02.264,24.229506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1421-1420,17:44:02.266,24.231784 s,2.278 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1422,17:44:02.267,24.231919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1423-1422,17:44:02.267,24.232477 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1424,17:44:02.267,24.232503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1425-1424,17:44:02.269,24.234476 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1426,17:44:02.270,24.234918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1427-1426,17:44:02.270,24.235475 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1428,17:44:02.270,24.235498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1429-1428,17:44:02.272,24.237476 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1430,17:44:02.273,24.237925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1431-1430,17:44:02.273,24.238476 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1432,17:44:02.273,24.238499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1433-1432,17:44:02.275,24.240480 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1434,17:44:02.276,24.240921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1435-1434,17:44:02.276,24.241475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1436,17:44:02.276,24.241500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1437-1436,17:44:02.278,24.243475 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1438,17:44:02.279,24.243919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1439-1438,17:44:02.279,24.244475 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1440,17:44:02.279,24.244499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1441-1440,17:44:02.281,24.246475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1442,17:44:02.282,24.246919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1443-1442,17:44:02.282,24.247476 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1444,17:44:02.282,24.247499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1445-1444,17:44:02.284,24.249475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1446,17:44:02.285,24.249924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1447-1446,17:44:02.285,24.250475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1448,17:44:02.285,24.250500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1449-1448,17:44:02.287,24.252474 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1450,17:44:02.288,24.252919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1451-1450,17:44:02.288,24.253475 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1452,17:44:02.288,24.253499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1453-1452,17:44:02.290,24.255475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1454,17:44:02.291,24.255959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1455-1454,17:44:02.291,24.256471 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success)\r
-URB,1456,17:44:02.291,24.256501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1457-1456,17:44:02.293,24.258473 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1458,17:44:02.294,24.258921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1459-1458,17:44:02.294,24.259474 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1460,17:44:02.294,24.259499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1461-1460,17:44:02.295,24.260521 s,1.022 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1462,17:44:02.296,24.260928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1463-1462,17:44:02.296,24.261476 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1464,17:44:02.296,24.261505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1465-1464,17:44:02.298,24.263476 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1466,17:44:02.299,24.263930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1467-1466,17:44:02.299,24.264476 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1468,17:44:02.299,24.264502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1469-1468,17:44:02.301,24.266475 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1470,17:44:02.302,24.266922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1471-1470,17:44:02.302,24.267474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1472,17:44:02.302,24.267498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1473-1472,17:44:02.304,24.269475 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1474,17:44:02.305,24.269923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1475-1474,17:44:02.305,24.270475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1476,17:44:02.305,24.270500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1477-1476,17:44:02.307,24.272476 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1478,17:44:02.308,24.272920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1479-1478,17:44:02.308,24.273475 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1480,17:44:02.308,24.273498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1481-1480,17:44:02.310,24.275475 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1482,17:44:02.311,24.275922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1483-1482,17:44:02.311,24.276474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1484,17:44:02.311,24.276498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1485-1484,17:44:02.313,24.278475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1486,17:44:02.314,24.278921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1487-1486,17:44:02.314,24.279475 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1488,17:44:02.314,24.279499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1489-1488,17:44:02.316,24.281475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1490,17:44:02.317,24.281930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1491-1490,17:44:02.317,24.282475 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1492,17:44:02.317,24.282499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1493-1492,17:44:02.319,24.284474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1494,17:44:02.320,24.284921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1495-1494,17:44:02.320,24.285477 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1496,17:44:02.320,24.285501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1497-1496,17:44:02.322,24.287475 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1498,17:44:02.323,24.287920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1499-1498,17:44:02.323,24.288475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1500,17:44:02.323,24.288498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1501-1500,17:44:02.325,24.290474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1502,17:44:02.326,24.290924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1503-1502,17:44:02.326,24.291474 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1504,17:44:02.326,24.291499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1505-1504,17:44:02.328,24.293474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1506,17:44:02.329,24.293923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1507-1506,17:44:02.329,24.294475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1508,17:44:02.329,24.294500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1509-1508,17:44:02.331,24.296477 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1510,17:44:02.332,24.296928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1511-1510,17:44:02.332,24.297474 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1512,17:44:02.332,24.297498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1513-1512,17:44:02.334,24.299474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1514,17:44:02.335,24.299921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1515-1514,17:44:02.335,24.300474 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1516,17:44:02.335,24.300497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1517-1516,17:44:02.337,24.302474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1518,17:44:02.338,24.302921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1519-1518,17:44:02.338,24.303474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1520,17:44:02.338,24.303497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1521-1520,17:44:02.340,24.305475 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1522,17:44:02.341,24.305925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1523-1522,17:44:02.341,24.306476 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1524,17:44:02.341,24.306503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1525-1524,17:44:02.343,24.308474 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1526,17:44:02.344,24.308940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1527-1526,17:44:02.344,24.309470 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1528,17:44:02.344,24.309501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1529-1528,17:44:02.346,24.311472 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1530,17:44:02.347,24.311930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1531-1530,17:44:02.347,24.312474 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1532,17:44:02.347,24.312498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1533-1532,17:44:02.349,24.314474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1534,17:44:02.350,24.314922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1535-1534,17:44:02.350,24.315473 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1536,17:44:02.350,24.315497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1537-1536,17:44:02.352,24.317474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1538,17:44:02.353,24.317922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1539-1538,17:44:02.353,24.318476 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1540,17:44:02.353,24.318500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1541-1540,17:44:02.355,24.320475 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1542,17:44:02.356,24.320922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1543-1542,17:44:02.356,24.321474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1544,17:44:02.356,24.321497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1545-1544,17:44:02.358,24.323482 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1546,17:44:02.359,24.323937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1547-1546,17:44:02.359,24.324475 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1548,17:44:02.359,24.324504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1549-1548,17:44:02.361,24.326477 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1550,17:44:02.362,24.326932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1551-1550,17:44:02.362,24.327473 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1552,17:44:02.362,24.327498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1553-1552,17:44:02.364,24.329474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1554,17:44:02.365,24.329925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1555-1554,17:44:02.365,24.330473 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1556,17:44:02.365,24.330498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1557-1556,17:44:02.367,24.332473 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1558,17:44:02.368,24.332922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1559-1558,17:44:02.368,24.333473 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1560,17:44:02.368,24.333497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1561-1560,17:44:02.370,24.335474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1562,17:44:02.371,24.335922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1563-1562,17:44:02.371,24.336474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1564,17:44:02.371,24.336498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1565-1564,17:44:02.373,24.338474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1566,17:44:02.374,24.338922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1567-1566,17:44:02.374,24.339474 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1568,17:44:02.374,24.339497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1569-1568,17:44:02.376,24.341473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1570,17:44:02.377,24.341929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1571-1570,17:44:02.377,24.342474 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1572,17:44:02.377,24.342497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1573-1572,17:44:02.379,24.344473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1574,17:44:02.380,24.344923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1575-1574,17:44:02.380,24.345473 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1576,17:44:02.380,24.345496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1577-1576,17:44:02.382,24.347473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1578,17:44:02.383,24.347923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1579-1578,17:44:02.383,24.348473 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1580,17:44:02.383,24.348496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1581-1580,17:44:02.385,24.350474 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1582,17:44:02.386,24.350927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1583-1582,17:44:02.386,24.351477 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1584,17:44:02.386,24.351502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1585-1584,17:44:02.388,24.353473 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1586,17:44:02.389,24.353924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1587-1586,17:44:02.389,24.354473 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1588,17:44:02.389,24.354497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1589-1588,17:44:02.391,24.356472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1590,17:44:02.392,24.356925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1591-1590,17:44:02.392,24.357472 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1592,17:44:02.392,24.357497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1593-1592,17:44:02.394,24.359474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1594,17:44:02.395,24.359927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1595-1594,17:44:02.395,24.360473 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1596,17:44:02.395,24.360496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1597-1596,17:44:02.397,24.362473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1598,17:44:02.398,24.362923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1599-1598,17:44:02.398,24.363472 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1600,17:44:02.398,24.363495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1601-1600,17:44:02.400,24.365476 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1602,17:44:02.401,24.365924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1603-1602,17:44:02.401,24.366473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1604,17:44:02.401,24.366496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1605-1604,17:44:02.403,24.368472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1606,17:44:02.404,24.368924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1607-1606,17:44:02.404,24.369473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1608,17:44:02.404,24.369497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1609-1608,17:44:02.406,24.371473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1610,17:44:02.407,24.371929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1611-1610,17:44:02.407,24.372472 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1612,17:44:02.407,24.372496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1613-1612,17:44:02.409,24.374473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1614,17:44:02.410,24.374924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1615-1614,17:44:02.410,24.375472 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1616,17:44:02.410,24.375496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1617-1616,17:44:02.412,24.377473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1618,17:44:02.413,24.377924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1619-1618,17:44:02.413,24.378473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1620,17:44:02.413,24.378497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1621-1620,17:44:02.415,24.380514 s,2.018 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1622,17:44:02.416,24.380926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1623-1622,17:44:02.416,24.381478 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1624,17:44:02.416,24.381506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1625-1624,17:44:02.418,24.383488 s,1.982 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1626,17:44:02.419,24.383932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1627-1626,17:44:02.419,24.384475 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1628,17:44:02.419,24.384503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1629-1628,17:44:02.421,24.386473 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1630,17:44:02.422,24.386924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1631-1630,17:44:02.422,24.387473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1632,17:44:02.422,24.387497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1633-1632,17:44:02.424,24.389473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1634,17:44:02.425,24.389930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1635-1634,17:44:02.425,24.390472 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1636,17:44:02.425,24.390498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1637-1636,17:44:02.427,24.392473 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1638,17:44:02.428,24.392929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1639-1638,17:44:02.428,24.393473 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1640,17:44:02.428,24.393497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1641-1640,17:44:02.430,24.395472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1642,17:44:02.431,24.395924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1643-1642,17:44:02.431,24.396472 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1644,17:44:02.431,24.396496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1645-1644,17:44:02.433,24.398473 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1646,17:44:02.434,24.398925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1647-1646,17:44:02.434,24.399473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1648,17:44:02.434,24.399497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1649-1648,17:44:02.436,24.401473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1650,17:44:02.437,24.401931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1651-1650,17:44:02.437,24.402473 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1652,17:44:02.437,24.402496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1653-1652,17:44:02.439,24.404472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1654,17:44:02.440,24.404924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1655-1654,17:44:02.440,24.405474 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1656,17:44:02.440,24.405498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1657-1656,17:44:02.442,24.407473 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1658,17:44:02.443,24.407924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1659-1658,17:44:02.443,24.408472 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1660,17:44:02.443,24.408495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1661-1660,17:44:02.445,24.410473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1662,17:44:02.446,24.410929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1663-1662,17:44:02.446,24.411471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1664,17:44:02.446,24.411496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1665-1664,17:44:02.448,24.413471 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1666,17:44:02.449,24.413926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1667-1666,17:44:02.449,24.414472 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1668,17:44:02.449,24.414496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1669-1668,17:44:02.451,24.416472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1670,17:44:02.452,24.416925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1671-1670,17:44:02.452,24.417473 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1672,17:44:02.452,24.417496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1673-1672,17:44:02.454,24.419475 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1674,17:44:02.455,24.419927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1675-1674,17:44:02.455,24.420471 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1676,17:44:02.455,24.420495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1677-1676,17:44:02.457,24.422472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1678,17:44:02.458,24.422930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1679-1678,17:44:02.458,24.423471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1680,17:44:02.458,24.423495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1681-1680,17:44:02.460,24.425473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1682,17:44:02.461,24.425926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1683-1682,17:44:02.461,24.426472 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1684,17:44:02.461,24.426496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1685-1684,17:44:02.463,24.428472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1686,17:44:02.464,24.428927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1687-1686,17:44:02.464,24.429471 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1688,17:44:02.464,24.429495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1689-1688,17:44:02.466,24.431472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1690,17:44:02.467,24.431932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1691-1690,17:44:02.467,24.432472 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1692,17:44:02.467,24.432496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1693-1692,17:44:02.469,24.434472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1694,17:44:02.470,24.434926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1695-1694,17:44:02.470,24.435471 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1696,17:44:02.470,24.435495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1697-1696,17:44:02.472,24.437471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1698,17:44:02.473,24.437932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1699-1698,17:44:02.473,24.438471 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1700,17:44:02.473,24.438495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1701-1700,17:44:02.475,24.440473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1702,17:44:02.476,24.440926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1703-1702,17:44:02.476,24.441471 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1704,17:44:02.476,24.441494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1705-1704,17:44:02.478,24.443471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1706,17:44:02.479,24.443927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1707-1706,17:44:02.479,24.444472 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1708,17:44:02.479,24.444495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1709-1708,17:44:02.481,24.446472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1710,17:44:02.482,24.446927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1711-1710,17:44:02.482,24.447472 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1712,17:44:02.482,24.447495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1713-1712,17:44:02.484,24.449471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1714,17:44:02.485,24.449929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1715-1714,17:44:02.485,24.450471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1716,17:44:02.485,24.450496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1717-1716,17:44:02.487,24.452471 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1718,17:44:02.488,24.452927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1719-1718,17:44:02.488,24.453474 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1720,17:44:02.488,24.453498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1721-1720,17:44:02.490,24.455472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1722,17:44:02.491,24.455972 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1723-1722,17:44:02.491,24.456466 s,495 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success)\r
-URB,1724,17:44:02.491,24.456494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1725-1724,17:44:02.493,24.458469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1726,17:44:02.494,24.458928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1727-1726,17:44:02.494,24.459471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1728,17:44:02.494,24.459494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1729-1728,17:44:02.496,24.461471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1730,17:44:02.497,24.461931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1731-1730,17:44:02.497,24.462471 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1732,17:44:02.497,24.462495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1733-1732,17:44:02.499,24.464471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1734,17:44:02.500,24.464927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1735-1734,17:44:02.500,24.465470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1736,17:44:02.500,24.465494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1737-1736,17:44:02.502,24.467473 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1738,17:44:02.503,24.467927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1739-1738,17:44:02.503,24.468470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1740,17:44:02.503,24.468494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1741-1740,17:44:02.505,24.470472 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1742,17:44:02.506,24.470930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1743-1742,17:44:02.506,24.471471 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1744,17:44:02.506,24.471495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1745-1744,17:44:02.508,24.473471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1746,17:44:02.509,24.473928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1747-1746,17:44:02.509,24.474470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1748,17:44:02.509,24.474494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1749-1748,17:44:02.511,24.476470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1750,17:44:02.512,24.476929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1751-1750,17:44:02.512,24.477471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1752,17:44:02.512,24.477494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1753-1752,17:44:02.514,24.479471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1754,17:44:02.515,24.479928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1755-1754,17:44:02.515,24.480470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1756,17:44:02.515,24.480494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1757-1756,17:44:02.517,24.482471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1758,17:44:02.518,24.482928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1759-1758,17:44:02.518,24.483470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1760,17:44:02.518,24.483493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1761-1760,17:44:02.520,24.485470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1762,17:44:02.521,24.485928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1763-1762,17:44:02.521,24.486470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1764,17:44:02.521,24.486494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1765-1764,17:44:02.523,24.488471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1766,17:44:02.524,24.488929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1767-1766,17:44:02.524,24.489471 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1768,17:44:02.524,24.489494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1769-1768,17:44:02.526,24.491470 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1770,17:44:02.527,24.491932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1771-1770,17:44:02.527,24.492470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1772,17:44:02.527,24.492494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1773-1772,17:44:02.529,24.494470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1774,17:44:02.530,24.494928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1775-1774,17:44:02.530,24.495471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1776,17:44:02.530,24.495494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1777-1776,17:44:02.532,24.497470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1778,17:44:02.533,24.497928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1779-1778,17:44:02.533,24.498470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1780,17:44:02.533,24.498494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1781-1780,17:44:02.535,24.500470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1782,17:44:02.536,24.500929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1783-1782,17:44:02.536,24.501485 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1784,17:44:02.536,24.501514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1785-1784,17:44:02.538,24.503473 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1786,17:44:02.539,24.503932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1787-1786,17:44:02.539,24.504470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1788,17:44:02.539,24.504494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1789-1788,17:44:02.541,24.506469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1790,17:44:02.542,24.506928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1791-1790,17:44:02.542,24.507470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1792,17:44:02.542,24.507493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1793-1792,17:44:02.544,24.509470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1794,17:44:02.545,24.509933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1795-1794,17:44:02.545,24.510470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1796,17:44:02.545,24.510495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1797-1796,17:44:02.547,24.512470 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1798,17:44:02.548,24.512929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1799-1798,17:44:02.548,24.513470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1800,17:44:02.548,24.513493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1801-1800,17:44:02.550,24.515470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1802,17:44:02.551,24.515929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1803-1802,17:44:02.551,24.516470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1804,17:44:02.551,24.516493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1805-1804,17:44:02.553,24.518471 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1806,17:44:02.554,24.518929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1807-1806,17:44:02.554,24.519470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1808,17:44:02.554,24.519493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1809-1808,17:44:02.556,24.521471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1810,17:44:02.557,24.521934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1811-1810,17:44:02.557,24.522473 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1812,17:44:02.557,24.522497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1813-1812,17:44:02.559,24.524484 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1814,17:44:02.560,24.524933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1815-1814,17:44:02.560,24.525474 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1816,17:44:02.560,24.525502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1817-1816,17:44:02.562,24.527474 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1818,17:44:02.563,24.527930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1819-1818,17:44:02.563,24.528470 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1820,17:44:02.563,24.528494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1821-1820,17:44:02.565,24.530470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1822,17:44:02.566,24.530932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1823-1822,17:44:02.566,24.531469 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1824,17:44:02.566,24.531494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1825-1824,17:44:02.567,24.532523 s,1.029 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1826,17:44:02.568,24.532932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1827-1826,17:44:02.568,24.533476 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1828,17:44:02.568,24.533504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1829-1828,17:44:02.570,24.535471 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1830,17:44:02.571,24.535939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1831-1830,17:44:02.571,24.536470 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1832,17:44:02.571,24.536495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1833-1832,17:44:02.573,24.538471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1834,17:44:02.574,24.538930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1835-1834,17:44:02.574,24.539472 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1836,17:44:02.574,24.539497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1837-1836,17:44:02.576,24.541470 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1838,17:44:02.577,24.541932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1839-1838,17:44:02.577,24.542469 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1840,17:44:02.577,24.542493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1841-1840,17:44:02.579,24.544470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1842,17:44:02.580,24.544930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1843-1842,17:44:02.580,24.545470 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1844,17:44:02.580,24.545493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1845-1844,17:44:02.582,24.547469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1846,17:44:02.583,24.547930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1847-1846,17:44:02.583,24.548493 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1848,17:44:02.583,24.548518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1849-1848,17:44:02.585,24.550471 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1850,17:44:02.586,24.550933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1851-1850,17:44:02.586,24.551470 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1852,17:44:02.586,24.551495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1853-1852,17:44:02.588,24.553473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1854,17:44:02.589,24.553931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1855-1854,17:44:02.589,24.554469 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1856,17:44:02.589,24.554493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1857-1856,17:44:02.591,24.556469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1858,17:44:02.592,24.556933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1859-1858,17:44:02.592,24.557468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1860,17:44:02.592,24.557492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1861-1860,17:44:02.594,24.559470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1862,17:44:02.595,24.559931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1863-1862,17:44:02.595,24.560469 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1864,17:44:02.595,24.560492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1865-1864,17:44:02.597,24.562470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1866,17:44:02.598,24.562931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1867-1866,17:44:02.598,24.563468 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1868,17:44:02.598,24.563492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1869-1868,17:44:02.600,24.565469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1870,17:44:02.601,24.565930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1871-1870,17:44:02.601,24.566470 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1872,17:44:02.601,24.566494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1873-1872,17:44:02.603,24.568469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1874,17:44:02.604,24.568933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1875-1874,17:44:02.604,24.569468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1876,17:44:02.604,24.569492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1877-1876,17:44:02.606,24.571469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1878,17:44:02.607,24.571932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1879-1878,17:44:02.607,24.572468 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1880,17:44:02.607,24.572492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1881-1880,17:44:02.609,24.574469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1882,17:44:02.610,24.574934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1883-1882,17:44:02.610,24.575469 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1884,17:44:02.610,24.575493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1885-1884,17:44:02.612,24.577470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1886,17:44:02.613,24.577932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1887-1886,17:44:02.613,24.578470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1888,17:44:02.613,24.578493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1889-1888,17:44:02.615,24.580469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1890,17:44:02.616,24.580934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1891-1890,17:44:02.616,24.581469 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1892,17:44:02.616,24.581492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1893-1892,17:44:02.618,24.583469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1894,17:44:02.619,24.583932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1895-1894,17:44:02.619,24.584468 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1896,17:44:02.619,24.584492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1897-1896,17:44:02.621,24.586470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1898,17:44:02.622,24.586938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1899-1898,17:44:02.622,24.587467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1900,17:44:02.622,24.587493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1901-1900,17:44:02.624,24.589468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1902,17:44:02.625,24.589943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1903-1902,17:44:02.625,24.590468 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1904,17:44:02.625,24.590494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1905-1904,17:44:02.627,24.592469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1906,17:44:02.628,24.592935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1907-1906,17:44:02.628,24.593471 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1908,17:44:02.628,24.593496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1909-1908,17:44:02.630,24.595468 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1910,17:44:02.631,24.595933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1911-1910,17:44:02.631,24.596468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1912,17:44:02.631,24.596492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1913-1912,17:44:02.633,24.598468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1914,17:44:02.634,24.598933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1915-1914,17:44:02.634,24.599468 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1916,17:44:02.634,24.599492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1917-1916,17:44:02.636,24.601469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1918,17:44:02.637,24.601933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1919-1918,17:44:02.637,24.602468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1920,17:44:02.637,24.602492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1921-1920,17:44:02.639,24.604468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1922,17:44:02.640,24.604932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1923-1922,17:44:02.640,24.605468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1924,17:44:02.640,24.605491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1925-1924,17:44:02.642,24.607471 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1926,17:44:02.643,24.607934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1927-1926,17:44:02.643,24.608468 s,534 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1928,17:44:02.643,24.608491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1929-1928,17:44:02.645,24.610468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1930,17:44:02.646,24.610935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1931-1930,17:44:02.646,24.611468 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1932,17:44:02.646,24.611492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1933-1932,17:44:02.648,24.613469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1934,17:44:02.649,24.613937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1935-1934,17:44:02.649,24.614467 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1936,17:44:02.649,24.614493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1937-1936,17:44:02.651,24.616468 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1938,17:44:02.652,24.616933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1939-1938,17:44:02.652,24.617468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1940,17:44:02.652,24.617491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1941-1940,17:44:02.654,24.619468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1942,17:44:02.655,24.619933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1943-1942,17:44:02.655,24.620467 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1944,17:44:02.655,24.620491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1945-1944,17:44:02.657,24.622468 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1946,17:44:02.658,24.622937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1947-1946,17:44:02.658,24.623468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1948,17:44:02.658,24.623491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1949-1948,17:44:02.660,24.625467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1950,17:44:02.661,24.625933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1951-1950,17:44:02.661,24.626468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1952,17:44:02.661,24.626492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1953-1952,17:44:02.663,24.628467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1954,17:44:02.664,24.628935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1955-1954,17:44:02.664,24.629468 s,533 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1956,17:44:02.664,24.629492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1957-1956,17:44:02.666,24.631468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1958,17:44:02.667,24.631934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1959-1958,17:44:02.667,24.632468 s,534 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1960,17:44:02.667,24.632491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1961-1960,17:44:02.669,24.634469 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1962,17:44:02.670,24.634936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1963-1962,17:44:02.670,24.635467 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1964,17:44:02.670,24.635491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1965-1964,17:44:02.672,24.637468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1966,17:44:02.673,24.637940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1967-1966,17:44:02.673,24.638468 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1968,17:44:02.673,24.638492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1969-1968,17:44:02.675,24.640468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1970,17:44:02.676,24.640934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1971-1970,17:44:02.676,24.641470 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1972,17:44:02.676,24.641493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1973-1972,17:44:02.678,24.643467 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1974,17:44:02.679,24.643934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1975-1974,17:44:02.679,24.644467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1976,17:44:02.679,24.644490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1977-1976,17:44:02.681,24.646467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1978,17:44:02.682,24.646934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1979-1978,17:44:02.682,24.647467 s,533 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1980,17:44:02.682,24.647491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1981-1980,17:44:02.684,24.649468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1982,17:44:02.685,24.649937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1983-1982,17:44:02.685,24.650468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1984,17:44:02.685,24.650492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1985-1984,17:44:02.687,24.652467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1986,17:44:02.688,24.652934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1987-1986,17:44:02.688,24.653467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1988,17:44:02.688,24.653491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1989-1988,17:44:02.690,24.655470 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1990,17:44:02.691,24.655938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1991-1990,17:44:02.691,24.656468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1992,17:44:02.691,24.656491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1993-1992,17:44:02.693,24.658467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1994,17:44:02.694,24.658936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1995-1994,17:44:02.694,24.659468 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,1996,17:44:02.694,24.659491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,1997-1996,17:44:02.696,24.661467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,1998,17:44:02.697,24.661935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,1999-1998,17:44:02.697,24.662467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2000,17:44:02.697,24.662490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2001-2000,17:44:02.699,24.664467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2002,17:44:02.700,24.664934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2003-2002,17:44:02.700,24.665467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2004,17:44:02.700,24.665490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2005-2004,17:44:02.702,24.667469 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2006,17:44:02.703,24.667936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2007-2006,17:44:02.703,24.668467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2008,17:44:02.703,24.668492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2009-2008,17:44:02.705,24.670468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2010,17:44:02.706,24.670938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2011-2010,17:44:02.706,24.671467 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2012,17:44:02.706,24.671492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2013-2012,17:44:02.708,24.673467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2014,17:44:02.709,24.673937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2015-2014,17:44:02.709,24.674467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2016,17:44:02.709,24.674492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2017-2016,17:44:02.711,24.676467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2018,17:44:02.712,24.676936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2019-2018,17:44:02.712,24.677466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2020,17:44:02.712,24.677490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2021-2020,17:44:02.714,24.679468 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2022,17:44:02.715,24.679936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2023-2022,17:44:02.715,24.680466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2024,17:44:02.715,24.680490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2025-2024,17:44:02.717,24.682467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2026,17:44:02.718,24.682935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2027-2026,17:44:02.718,24.683467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2028,17:44:02.718,24.683490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2029-2028,17:44:02.720,24.685467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2030,17:44:02.721,24.685935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2031-2030,17:44:02.721,24.686467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2032,17:44:02.721,24.686490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2033-2032,17:44:02.723,24.688470 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2034,17:44:02.724,24.688938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2035-2034,17:44:02.724,24.689481 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2036,17:44:02.724,24.689511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2037-2036,17:44:02.726,24.691474 s,1.963 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2038,17:44:02.727,24.691937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2039-2038,17:44:02.727,24.692473 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2040,17:44:02.727,24.692498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2041-2040,17:44:02.729,24.694467 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2042,17:44:02.730,24.694936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2043-2042,17:44:02.730,24.695466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2044,17:44:02.730,24.695491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2045-2044,17:44:02.732,24.697467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2046,17:44:02.733,24.697936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2047-2046,17:44:02.733,24.698466 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2048,17:44:02.733,24.698490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2049-2048,17:44:02.735,24.700473 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2050,17:44:02.736,24.700936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2051-2050,17:44:02.736,24.701466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2052,17:44:02.736,24.701490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2053-2052,17:44:02.738,24.703469 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2054,17:44:02.739,24.703937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2055-2054,17:44:02.739,24.704475 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2056,17:44:02.739,24.704498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2057-2056,17:44:02.741,24.706474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2058,17:44:02.742,24.706937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2059-2058,17:44:02.742,24.707474 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2060,17:44:02.742,24.707497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2061-2060,17:44:02.744,24.709467 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2062,17:44:02.745,24.709945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2063-2062,17:44:02.745,24.710474 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2064,17:44:02.745,24.710500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2065-2064,17:44:02.747,24.712468 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2066,17:44:02.748,24.712944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2067-2066,17:44:02.748,24.713475 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2068,17:44:02.748,24.713500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2069-2068,17:44:02.750,24.715466 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2070,17:44:02.751,24.715937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2071-2070,17:44:02.751,24.716466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2072,17:44:02.751,24.716490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2073-2072,17:44:02.753,24.718466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2074,17:44:02.754,24.718937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2075-2074,17:44:02.754,24.719466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2076,17:44:02.754,24.719491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2077-2076,17:44:02.756,24.721466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2078,17:44:02.757,24.721937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2079-2078,17:44:02.757,24.722467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2080,17:44:02.757,24.722491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2081-2080,17:44:02.759,24.724466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2082,17:44:02.760,24.724937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2083-2082,17:44:02.760,24.725465 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2084,17:44:02.760,24.725489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2085-2084,17:44:02.762,24.727467 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2086,17:44:02.763,24.727937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2087-2086,17:44:02.763,24.728465 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2088,17:44:02.763,24.728489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2089-2088,17:44:02.765,24.730466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2090,17:44:02.766,24.730941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2091-2090,17:44:02.766,24.731465 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2092,17:44:02.766,24.731490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2093-2092,17:44:02.768,24.733466 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2094,17:44:02.769,24.733937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2095-2094,17:44:02.769,24.734466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2096,17:44:02.769,24.734490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2097-2096,17:44:02.771,24.736465 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2098,17:44:02.772,24.736937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2099-2098,17:44:02.772,24.737468 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2100,17:44:02.772,24.737492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2101-2100,17:44:02.774,24.739466 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2102,17:44:02.775,24.739937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2103-2102,17:44:02.775,24.740465 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2104,17:44:02.775,24.740489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2105-2104,17:44:02.777,24.742467 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2106,17:44:02.778,24.742938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2107-2106,17:44:02.778,24.743465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2108,17:44:02.778,24.743489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2109-2108,17:44:02.780,24.745466 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2110,17:44:02.781,24.745938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2111-2110,17:44:02.781,24.746465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2112,17:44:02.781,24.746489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2113-2112,17:44:02.783,24.748465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2114,17:44:02.784,24.748939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2115-2114,17:44:02.784,24.749465 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2116,17:44:02.784,24.749489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2117-2116,17:44:02.786,24.751468 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2118,17:44:02.787,24.751938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2119-2118,17:44:02.787,24.752465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2120,17:44:02.787,24.752488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2121-2120,17:44:02.789,24.754465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2122,17:44:02.790,24.754939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2123-2122,17:44:02.790,24.755464 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2124,17:44:02.790,24.755488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2125-2124,17:44:02.792,24.757465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2126,17:44:02.793,24.757938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2127-2126,17:44:02.793,24.758465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2128,17:44:02.793,24.758488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2129-2128,17:44:02.795,24.760466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2130,17:44:02.796,24.760940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2131-2130,17:44:02.796,24.761466 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2132,17:44:02.796,24.761489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2133-2132,17:44:02.798,24.763466 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2134,17:44:02.799,24.763938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2135-2134,17:44:02.799,24.764465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2136,17:44:02.799,24.764489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2137-2136,17:44:02.801,24.766465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2138,17:44:02.802,24.766938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2139-2138,17:44:02.802,24.767466 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2140,17:44:02.802,24.767489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2141-2140,17:44:02.804,24.769465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2142,17:44:02.805,24.769941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2143-2142,17:44:02.805,24.770464 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2144,17:44:02.805,24.770489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2145-2144,17:44:02.807,24.772465 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2146,17:44:02.808,24.772940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2147-2146,17:44:02.808,24.773464 s,524 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2148,17:44:02.808,24.773487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2149-2148,17:44:02.810,24.775466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2150,17:44:02.811,24.775939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2151-2150,17:44:02.811,24.776465 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2152,17:44:02.811,24.776488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2153-2152,17:44:02.813,24.778466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2154,17:44:02.814,24.778939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2155-2154,17:44:02.814,24.779464 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2156,17:44:02.814,24.779488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2157-2156,17:44:02.816,24.781465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2158,17:44:02.817,24.781952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2159-2158,17:44:02.817,24.782476 s,524 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2160,17:44:02.817,24.782505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2161-2160,17:44:02.819,24.784463 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2162,17:44:02.820,24.784938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2163-2162,17:44:02.820,24.785458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2164,17:44:02.820,24.785480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2165-2164,17:44:02.822,24.787457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2166,17:44:02.823,24.787937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2167-2166,17:44:02.823,24.788458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2168,17:44:02.823,24.788480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2169-2168,17:44:02.824,24.789461 s,980 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2170,17:44:02.825,24.789939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2171-2170,17:44:02.825,24.790459 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2172,17:44:02.825,24.790482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2173-2172,17:44:02.827,24.792457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2174,17:44:02.828,24.792937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2175-2174,17:44:02.828,24.793458 s,521 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2176,17:44:02.828,24.793481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2177-2176,17:44:02.830,24.795457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2178,17:44:02.831,24.795938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2179-2178,17:44:02.831,24.796457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2180,17:44:02.831,24.796479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2181-2180,17:44:02.832,24.797458 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2182,17:44:02.833,24.797937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2183-2182,17:44:02.833,24.798458 s,521 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2184,17:44:02.833,24.798487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2185-2184,17:44:02.835,24.800457 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2186,17:44:02.836,24.800937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2187-2186,17:44:02.836,24.801458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2188,17:44:02.836,24.801480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2189-2188,17:44:02.838,24.803457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2190,17:44:02.839,24.803937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2191-2190,17:44:02.839,24.804458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2192,17:44:02.839,24.804480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2193-2192,17:44:02.840,24.805457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2194,17:44:02.841,24.805937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2195-2194,17:44:02.841,24.806458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2196,17:44:02.841,24.806480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2197-2196,17:44:02.843,24.808458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2198,17:44:02.844,24.808938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2199-2198,17:44:02.844,24.809457 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2200,17:44:02.844,24.809480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2201-2200,17:44:02.846,24.811456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2202,17:44:02.847,24.811937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2203-2202,17:44:02.847,24.812457 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2204,17:44:02.847,24.812479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2205-2204,17:44:02.848,24.813457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2206,17:44:02.849,24.813938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2207-2206,17:44:02.849,24.814457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2208,17:44:02.849,24.814479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2209-2208,17:44:02.851,24.816457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2210,17:44:02.852,24.816938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2211-2210,17:44:02.852,24.817457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2212,17:44:02.852,24.817479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2213-2212,17:44:02.854,24.819457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2214,17:44:02.855,24.819938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2215-2214,17:44:02.855,24.820457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2216,17:44:02.855,24.820479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2217-2216,17:44:02.856,24.821457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2218,17:44:02.857,24.821945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2219-2218,17:44:02.857,24.822457 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2220,17:44:02.857,24.822479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2221-2220,17:44:02.859,24.824457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2222,17:44:02.860,24.824939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2223-2222,17:44:02.860,24.825457 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2224,17:44:02.860,24.825480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2225-2224,17:44:02.862,24.827457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2226,17:44:02.863,24.827939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2227-2226,17:44:02.863,24.828457 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2228,17:44:02.863,24.828479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2229-2228,17:44:02.864,24.829471 s,992 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2230,17:44:02.865,24.829943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2231-2230,17:44:02.865,24.830468 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2232,17:44:02.865,24.830494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2233-2232,17:44:02.867,24.832464 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2234,17:44:02.868,24.832941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2235-2234,17:44:02.868,24.833463 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2236,17:44:02.868,24.833487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2237-2236,17:44:02.870,24.835464 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2238,17:44:02.871,24.835940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2239-2238,17:44:02.871,24.836463 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2240,17:44:02.871,24.836487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2241-2240,17:44:02.873,24.838467 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2242,17:44:02.874,24.838942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2243-2242,17:44:02.874,24.839464 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2244,17:44:02.874,24.839488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2245-2244,17:44:02.876,24.841464 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2246,17:44:02.877,24.841941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2247-2246,17:44:02.877,24.842464 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2248,17:44:02.877,24.842487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2249-2248,17:44:02.879,24.844463 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2250,17:44:02.880,24.844942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2251-2250,17:44:02.880,24.845464 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2252,17:44:02.880,24.845487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2253-2252,17:44:02.882,24.847464 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2254,17:44:02.883,24.847941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2255-2254,17:44:02.883,24.848463 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2256,17:44:02.883,24.848487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2257-2256,17:44:02.885,24.850463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2258,17:44:02.886,24.850944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2259-2258,17:44:02.886,24.851463 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2260,17:44:02.886,24.851487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2261-2260,17:44:02.888,24.853464 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2262,17:44:02.889,24.853946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2263-2262,17:44:02.889,24.854464 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2264,17:44:02.889,24.854489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2265-2264,17:44:02.891,24.856463 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2266,17:44:02.892,24.856943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2267-2266,17:44:02.892,24.857463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2268,17:44:02.892,24.857488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2269-2268,17:44:02.894,24.859463 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2270,17:44:02.895,24.859945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2271-2270,17:44:02.895,24.860463 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2272,17:44:02.895,24.860487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2273-2272,17:44:02.897,24.862463 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2274,17:44:02.898,24.862942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2275-2274,17:44:02.898,24.863463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2276,17:44:02.898,24.863486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2277-2276,17:44:02.900,24.865463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2278,17:44:02.901,24.865942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2279-2278,17:44:02.901,24.866463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2280,17:44:02.901,24.866486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2281-2280,17:44:02.903,24.868463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2282,17:44:02.904,24.868945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2283-2282,17:44:02.904,24.869466 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2284,17:44:02.904,24.869491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2285-2284,17:44:02.906,24.871465 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2286,17:44:02.907,24.871943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2287-2286,17:44:02.907,24.872466 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2288,17:44:02.907,24.872489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2289-2288,17:44:02.909,24.874463 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2290,17:44:02.910,24.874943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2291-2290,17:44:02.910,24.875463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2292,17:44:02.910,24.875486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2293-2292,17:44:02.912,24.877463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2294,17:44:02.913,24.877943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2295-2294,17:44:02.913,24.878463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2296,17:44:02.913,24.878486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2297-2296,17:44:02.915,24.880463 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2298,17:44:02.916,24.880943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2299-2298,17:44:02.916,24.881462 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2300,17:44:02.916,24.881486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2301-2300,17:44:02.918,24.883463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2302,17:44:02.919,24.883942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2303-2302,17:44:02.919,24.884508 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2304,17:44:02.919,24.884533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2305-2304,17:44:02.921,24.886508 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2306,17:44:02.922,24.886959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2307-2306,17:44:02.922,24.887468 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2308,17:44:02.922,24.887499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2309-2308,17:44:02.924,24.889493 s,1.994 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2310,17:44:02.925,24.889959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2311-2310,17:44:02.925,24.890469 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2312,17:44:02.925,24.890498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2313-2312,17:44:02.927,24.892498 s,2.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2314,17:44:02.928,24.892966 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2315-2314,17:44:02.928,24.893481 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2316,17:44:02.928,24.893517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2317-2316,17:44:02.930,24.895471 s,1.953 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2318,17:44:02.931,24.895955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2319-2318,17:44:02.931,24.896468 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2320,17:44:02.931,24.896498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2321-2320,17:44:02.933,24.898463 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2322,17:44:02.934,24.899023 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2323-2322,17:44:02.934,24.899463 s,440 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2324,17:44:02.934,24.899495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2325-2324,17:44:02.936,24.901462 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2326,17:44:02.937,24.901953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2327-2326,17:44:02.937,24.902499 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2328,17:44:02.937,24.902545 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2329-2328,17:44:02.939,24.904556 s,2.011 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2330,17:44:02.940,24.904949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2331-2330,17:44:02.940,24.905466 s,517 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2332,17:44:02.940,24.905494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2333-2332,17:44:02.942,24.907461 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2334,17:44:02.943,24.907946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2335-2334,17:44:02.943,24.908461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2336,17:44:02.943,24.908486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2337-2336,17:44:02.945,24.910463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2338,17:44:02.946,24.910959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2339-2338,17:44:02.946,24.911462 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2340,17:44:02.946,24.911491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2341-2340,17:44:02.948,24.913462 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2342,17:44:02.949,24.913948 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2343-2342,17:44:02.949,24.914462 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2344,17:44:02.949,24.914486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2345-2344,17:44:02.951,24.916462 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2346,17:44:02.952,24.916946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2347-2346,17:44:02.952,24.917464 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2348,17:44:02.952,24.917489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2349-2348,17:44:02.954,24.919462 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2350,17:44:02.955,24.919946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2351-2350,17:44:02.955,24.920463 s,517 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2352,17:44:02.955,24.920487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2353-2352,17:44:02.957,24.922462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2354,17:44:02.958,24.922951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2355-2354,17:44:02.958,24.923464 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2356,17:44:02.958,24.923488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2357-2356,17:44:02.960,24.925461 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2358,17:44:02.961,24.925946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2359-2358,17:44:02.961,24.926465 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2360,17:44:02.961,24.926489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2361-2360,17:44:02.963,24.928461 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2362,17:44:02.964,24.928949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2363-2362,17:44:02.964,24.929469 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2364,17:44:02.964,24.929496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2365-2364,17:44:02.966,24.931462 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2366,17:44:02.967,24.931947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2367-2366,17:44:02.967,24.932461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2368,17:44:02.967,24.932487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2369-2368,17:44:02.969,24.934462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2370,17:44:02.970,24.934947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2371-2370,17:44:02.970,24.935462 s,516 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2372,17:44:02.970,24.935487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2373-2372,17:44:02.972,24.937473 s,1.986 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2374,17:44:02.973,24.938041 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2375-2374,17:44:02.973,24.938475 s,434 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2376,17:44:02.973,24.938541 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2377-2376,17:44:02.975,24.940483 s,1.942 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2378,17:44:02.976,24.941008 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2379-2378,17:44:02.976,24.941483 s,475 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2380,17:44:02.976,24.941540 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2381-2380,17:44:02.978,24.943485 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2382,17:44:02.979,24.943980 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2383-2382,17:44:02.979,24.944464 s,484 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2384,17:44:02.979,24.944496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2385-2384,17:44:02.981,24.946472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2386,17:44:02.982,24.946974 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2387-2386,17:44:02.982,24.947470 s,496 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2388,17:44:02.982,24.947518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2389-2388,17:44:02.984,24.949461 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2390,17:44:02.985,24.949987 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2391-2390,17:44:02.985,24.950462 s,475 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2392,17:44:02.985,24.950491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2393-2392,17:44:02.987,24.952462 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2394,17:44:02.988,24.952952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2395-2394,17:44:02.988,24.953461 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2396,17:44:02.988,24.953488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2397-2396,17:44:02.990,24.955468 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2398,17:44:02.991,24.956003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2399-2398,17:44:02.991,24.956462 s,459 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2400,17:44:02.991,24.956494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2401-2400,17:44:02.993,24.958459 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2402,17:44:02.994,24.958944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2403-2402,17:44:02.994,24.959458 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2404,17:44:02.994,24.959481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2405-2404,17:44:02.996,24.961477 s,1.996 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2406,17:44:02.997,24.962161 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2407-2406,17:44:02.997,24.962468 s,308 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success)\r
-URB,2408,17:44:02.997,24.962638 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2409-2408,17:44:02.999,24.964468 s,1.830 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2410,17:44:03.000,24.964956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2411-2410,17:44:03.000,24.965487 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2412,17:44:03.000,24.965525 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2413-2412,17:44:03.002,24.967484 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2414,17:44:03.003,24.967949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2415-2414,17:44:03.003,24.968469 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2416,17:44:03.003,24.968497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2417-2416,17:44:03.005,24.970464 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2418,17:44:03.006,24.970950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2419-2418,17:44:03.006,24.971462 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2420,17:44:03.006,24.971488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2421-2420,17:44:03.008,24.973462 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2422,17:44:03.009,24.973947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2423-2422,17:44:03.009,24.974461 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2424,17:44:03.009,24.974486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2425-2424,17:44:03.011,24.976462 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2426,17:44:03.012,24.976947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2427-2426,17:44:03.012,24.977461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2428,17:44:03.012,24.977485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2429-2428,17:44:03.014,24.979475 s,1.990 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2430,17:44:03.015,24.979996 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2431-2430,17:44:03.015,24.980474 s,478 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2432,17:44:03.015,24.980708 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2433-2432,17:44:03.017,24.982459 s,1.751 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2434,17:44:03.018,24.982953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2435-2434,17:44:03.018,24.983462 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2436,17:44:03.018,24.983486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2437-2436,17:44:03.020,24.985461 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2438,17:44:03.021,24.985947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2439-2438,17:44:03.021,24.986460 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2440,17:44:03.021,24.986484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2441-2440,17:44:03.023,24.988461 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2442,17:44:03.024,24.988950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2443-2442,17:44:03.024,24.989460 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2444,17:44:03.024,24.989485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2445-2444,17:44:03.026,24.991461 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2446,17:44:03.027,24.991947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2447-2446,17:44:03.027,24.992461 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2448,17:44:03.027,24.992484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2449-2448,17:44:03.029,24.994467 s,1.983 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2450,17:44:03.030,24.994956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2451-2450,17:44:03.030,24.995461 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2452,17:44:03.030,24.995488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2453-2452,17:44:03.032,24.997459 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2454,17:44:03.033,24.997953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2455-2454,17:44:03.033,24.998461 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2456,17:44:03.033,24.998485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2457-2456,17:44:03.035,25.000461 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2458,17:44:03.036,25.000949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2459-2458,17:44:03.036,25.001472 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2460,17:44:03.036,25.001502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2461-2460,17:44:03.038,25.003463 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2462,17:44:03.039,25.003954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2463-2462,17:44:03.039,25.004465 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2464,17:44:03.039,25.004495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2465-2464,17:44:03.041,25.006472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2466,17:44:03.042,25.007032 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2467-2466,17:44:03.042,25.007461 s,428 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2468,17:44:03.042,25.007495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2469-2468,17:44:03.044,25.009462 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2470,17:44:03.045,25.009969 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2471-2470,17:44:03.045,25.010462 s,492 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2472,17:44:03.045,25.010491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2473-2472,17:44:03.047,25.012459 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2474,17:44:03.048,25.012950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2475-2474,17:44:03.048,25.013460 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2476,17:44:03.048,25.013485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2477-2476,17:44:03.050,25.015464 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2478,17:44:03.051,25.015967 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2479-2478,17:44:03.051,25.016460 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2480,17:44:03.051,25.016487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2481-2480,17:44:03.053,25.018462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2482,17:44:03.054,25.018950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2483-2482,17:44:03.054,25.019459 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2484,17:44:03.054,25.019484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2485-2484,17:44:03.056,25.021460 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2486,17:44:03.057,25.021951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2487-2486,17:44:03.057,25.022460 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2488,17:44:03.057,25.022485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2489-2488,17:44:03.059,25.024461 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2490,17:44:03.060,25.024963 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2491-2490,17:44:03.060,25.025461 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2492,17:44:03.060,25.025489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2493-2492,17:44:03.062,25.027460 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2494,17:44:03.063,25.027950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2495-2494,17:44:03.063,25.028460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2496,17:44:03.063,25.028485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2497-2496,17:44:03.065,25.030460 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2498,17:44:03.066,25.030962 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2499-2498,17:44:03.066,25.031460 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2500,17:44:03.066,25.031488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2501-2500,17:44:03.068,25.033460 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2502,17:44:03.069,25.033953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2503-2502,17:44:03.069,25.034459 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2504,17:44:03.069,25.034484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2505-2504,17:44:03.071,25.036459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2506,17:44:03.072,25.036950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2507-2506,17:44:03.072,25.037460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2508,17:44:03.072,25.037485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2509-2508,17:44:03.074,25.039466 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2510,17:44:03.075,25.039951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2511-2510,17:44:03.075,25.040463 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2512,17:44:03.075,25.040489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2513-2512,17:44:03.077,25.042464 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2514,17:44:03.078,25.042954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2515-2514,17:44:03.078,25.043464 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2516,17:44:03.078,25.043493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2517-2516,17:44:03.080,25.045471 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2518,17:44:03.081,25.045956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2519-2518,17:44:03.081,25.046482 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2520,17:44:03.081,25.046520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2521-2520,17:44:03.083,25.048513 s,1.993 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2522,17:44:03.084,25.048960 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2523-2522,17:44:03.084,25.049488 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2524,17:44:03.084,25.049533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2525-2524,17:44:03.086,25.051467 s,1.933 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2526,17:44:03.087,25.051951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2527-2526,17:44:03.087,25.052461 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2528,17:44:03.087,25.052486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2529-2528,17:44:03.089,25.054461 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2530,17:44:03.090,25.054950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2531-2530,17:44:03.090,25.055460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2532,17:44:03.090,25.055484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2533-2532,17:44:03.092,25.057459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2534,17:44:03.093,25.057950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2535-2534,17:44:03.093,25.058460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2536,17:44:03.093,25.058484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2537-2536,17:44:03.095,25.060459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2538,17:44:03.096,25.060950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2539-2538,17:44:03.096,25.061460 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2540,17:44:03.096,25.061484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2541-2540,17:44:03.098,25.063462 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2542,17:44:03.099,25.063950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2543-2542,17:44:03.099,25.064459 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2544,17:44:03.099,25.064483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2545-2544,17:44:03.101,25.066470 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2546,17:44:03.102,25.067003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2547-2546,17:44:03.102,25.067459 s,456 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
-URB,2548,17:44:03.102,25.067490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2549-2548,17:44:03.104,25.069485 s,1.995 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2550,17:44:03.105,25.070003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2551-2550,17:44:03.105,25.070458 s,454 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2552,17:44:03.105,25.070489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2553-2552,17:44:03.107,25.072462 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2554,17:44:03.108,25.072954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2555-2554,17:44:03.108,25.073459 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2556,17:44:03.108,25.073484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2557-2556,17:44:03.110,25.075458 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2558,17:44:03.111,25.075950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2559-2558,17:44:03.111,25.076458 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2560,17:44:03.111,25.076483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2561-2560,17:44:03.113,25.078459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2562,17:44:03.114,25.078952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2563-2562,17:44:03.114,25.079459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2564,17:44:03.114,25.079483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2565-2564,17:44:03.116,25.081459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2566,17:44:03.117,25.081950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2567-2566,17:44:03.117,25.082458 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2568,17:44:03.117,25.082482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2569-2568,17:44:03.119,25.084459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2570,17:44:03.120,25.084952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2571-2570,17:44:03.120,25.085459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2572,17:44:03.120,25.085483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2573-2572,17:44:03.122,25.087460 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2574,17:44:03.123,25.087951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2575-2574,17:44:03.123,25.088459 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2576,17:44:03.123,25.088483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2577-2576,17:44:03.125,25.090459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2578,17:44:03.126,25.090954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2579-2578,17:44:03.126,25.091458 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2580,17:44:03.126,25.091483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2581-2580,17:44:03.128,25.093459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2582,17:44:03.129,25.093951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2583-2582,17:44:03.129,25.094459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2584,17:44:03.129,25.094482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2585-2584,17:44:03.131,25.096459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2586,17:44:03.132,25.096951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2587-2586,17:44:03.132,25.097458 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2588,17:44:03.132,25.097482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2589-2588,17:44:03.134,25.099459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2590,17:44:03.135,25.099954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2591-2590,17:44:03.135,25.100470 s,516 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2592,17:44:03.135,25.100505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2593-2592,17:44:03.137,25.102463 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2594,17:44:03.138,25.102964 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2595-2594,17:44:03.138,25.103458 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2596,17:44:03.138,25.103484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2597-2596,17:44:03.140,25.105459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2598,17:44:03.141,25.105951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2599-2598,17:44:03.141,25.106459 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2600,17:44:03.141,25.106483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2601-2600,17:44:03.143,25.108458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2602,17:44:03.144,25.108955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2603-2602,17:44:03.144,25.109458 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2604,17:44:03.144,25.109482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2605-2604,17:44:03.146,25.111458 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2606,17:44:03.147,25.111952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2607-2606,17:44:03.147,25.112458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2608,17:44:03.147,25.112482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2609-2608,17:44:03.149,25.114462 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2610,17:44:03.150,25.114952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2611-2610,17:44:03.150,25.115458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2612,17:44:03.150,25.115481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2613-2612,17:44:03.152,25.117461 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2614,17:44:03.153,25.117960 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2615-2614,17:44:03.153,25.118459 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2616,17:44:03.153,25.118486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2617-2616,17:44:03.155,25.120458 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2618,17:44:03.156,25.120953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2619-2618,17:44:03.156,25.121459 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2620,17:44:03.156,25.121482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2621-2620,17:44:03.158,25.123457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2622,17:44:03.159,25.123952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2623-2622,17:44:03.159,25.124457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2624,17:44:03.159,25.124481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2625-2624,17:44:03.161,25.126458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2626,17:44:03.162,25.126952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2627-2626,17:44:03.162,25.127458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2628,17:44:03.162,25.127481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2629-2628,17:44:03.164,25.129458 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2630,17:44:03.165,25.129955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2631-2630,17:44:03.165,25.130458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2632,17:44:03.165,25.130482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2633-2632,17:44:03.167,25.132458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2634,17:44:03.168,25.132953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2635-2634,17:44:03.168,25.133458 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2636,17:44:03.168,25.133482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2637-2636,17:44:03.170,25.135458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2638,17:44:03.171,25.135953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2639-2638,17:44:03.171,25.136458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2640,17:44:03.171,25.136482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2641-2640,17:44:03.173,25.138458 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2642,17:44:03.174,25.138957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2643-2642,17:44:03.174,25.139458 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2644,17:44:03.174,25.139482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2645-2644,17:44:03.176,25.141457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2646,17:44:03.177,25.141953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2647-2646,17:44:03.177,25.142457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2648,17:44:03.177,25.142481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2649-2648,17:44:03.179,25.144459 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2650,17:44:03.180,25.144952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2651-2650,17:44:03.180,25.145457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2652,17:44:03.180,25.145481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2653-2652,17:44:03.182,25.147457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2654,17:44:03.183,25.147953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2655-2654,17:44:03.183,25.148460 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2656,17:44:03.183,25.148484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2657-2656,17:44:03.185,25.150458 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2658,17:44:03.186,25.150956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2659-2658,17:44:03.186,25.151458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2660,17:44:03.186,25.151482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2661-2660,17:44:03.188,25.153457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2662,17:44:03.189,25.153953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2663-2662,17:44:03.189,25.154457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2664,17:44:03.189,25.154482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2665-2664,17:44:03.191,25.156457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2666,17:44:03.192,25.156953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2667-2666,17:44:03.192,25.157457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2668,17:44:03.192,25.157480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2669-2668,17:44:03.194,25.159457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2670,17:44:03.195,25.159953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2671-2670,17:44:03.195,25.160457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2672,17:44:03.195,25.160480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2673-2672,17:44:03.197,25.162460 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2674,17:44:03.198,25.162953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2675-2674,17:44:03.198,25.163457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2676,17:44:03.198,25.163480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2677-2676,17:44:03.200,25.165457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2678,17:44:03.201,25.165953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2679-2678,17:44:03.201,25.166457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2680,17:44:03.201,25.166481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2681-2680,17:44:03.203,25.168457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2682,17:44:03.204,25.168956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2683-2682,17:44:03.204,25.169458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2684,17:44:03.204,25.169482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2685-2684,17:44:03.206,25.171457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2686,17:44:03.207,25.171955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2687-2686,17:44:03.207,25.172456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2688,17:44:03.207,25.172480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2689-2688,17:44:03.209,25.174458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2690,17:44:03.210,25.174954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2691-2690,17:44:03.210,25.175457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2692,17:44:03.210,25.175482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2693-2692,17:44:03.212,25.177458 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2694,17:44:03.213,25.177957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2695-2694,17:44:03.213,25.178458 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2696,17:44:03.213,25.178481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2697-2696,17:44:03.215,25.180459 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2698,17:44:03.216,25.180956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2699-2698,17:44:03.216,25.181457 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2700,17:44:03.216,25.181481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2701-2700,17:44:03.218,25.183457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2702,17:44:03.219,25.183955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2703-2702,17:44:03.219,25.184457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2704,17:44:03.219,25.184481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2705-2704,17:44:03.221,25.186457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2706,17:44:03.222,25.186954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2707-2706,17:44:03.222,25.187456 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2708,17:44:03.222,25.187480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2709-2708,17:44:03.224,25.189457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2710,17:44:03.225,25.189958 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2711-2710,17:44:03.225,25.190456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2712,17:44:03.225,25.190481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2713-2712,17:44:03.227,25.192457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2714,17:44:03.228,25.192955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2715-2714,17:44:03.228,25.193456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2716,17:44:03.228,25.193480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2717-2716,17:44:03.230,25.195456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2718,17:44:03.231,25.195955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2719-2718,17:44:03.231,25.196459 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2720,17:44:03.231,25.196483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2721-2720,17:44:03.233,25.198457 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2722,17:44:03.234,25.198955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2723-2722,17:44:03.234,25.199457 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2724,17:44:03.234,25.199481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2725-2724,17:44:03.236,25.201456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2726,17:44:03.237,25.201954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2727-2726,17:44:03.237,25.202456 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2728,17:44:03.237,25.202481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2729-2728,17:44:03.239,25.204456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2730,17:44:03.240,25.204956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2731-2730,17:44:03.240,25.205456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2732,17:44:03.240,25.205479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2733-2732,17:44:03.242,25.207457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2734,17:44:03.243,25.207955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2735-2734,17:44:03.243,25.208456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2736,17:44:03.243,25.208479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2737-2736,17:44:03.245,25.210459 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2738,17:44:03.246,25.210958 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2739-2738,17:44:03.246,25.211456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2740,17:44:03.246,25.211480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2741-2740,17:44:03.248,25.213456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2742,17:44:03.249,25.213955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2743-2742,17:44:03.249,25.214457 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2744,17:44:03.249,25.214480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2745-2744,17:44:03.251,25.216456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2746,17:44:03.252,25.216957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2747-2746,17:44:03.252,25.217456 s,499 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2748,17:44:03.252,25.217480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2749-2748,17:44:03.254,25.219456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2750,17:44:03.255,25.219955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2751-2750,17:44:03.255,25.220455 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2752,17:44:03.255,25.220479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2753-2752,17:44:03.257,25.222457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2754,17:44:03.258,25.222957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2755-2754,17:44:03.258,25.223456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2756,17:44:03.258,25.223479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2757-2756,17:44:03.260,25.225457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2758,17:44:03.261,25.225955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2759-2758,17:44:03.261,25.226456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2760,17:44:03.261,25.226479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2761-2760,17:44:03.263,25.228456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2762,17:44:03.264,25.228957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2763-2762,17:44:03.264,25.229456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2764,17:44:03.264,25.229480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2765-2764,17:44:03.266,25.231456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2766,17:44:03.267,25.231956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2767-2766,17:44:03.267,25.232494 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2768,17:44:03.267,25.232518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2769-2768,17:44:03.269,25.234456 s,1.938 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2770,17:44:03.270,25.234955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2771-2770,17:44:03.270,25.235455 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2772,17:44:03.270,25.235478 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2773-2772,17:44:03.272,25.237456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2774,17:44:03.273,25.237956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2775-2774,17:44:03.273,25.238456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2776,17:44:03.273,25.238479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2777-2776,17:44:03.275,25.240457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2778,17:44:03.276,25.240956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2779-2778,17:44:03.276,25.241456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2780,17:44:03.276,25.241479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2781-2780,17:44:03.278,25.243459 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2782,17:44:03.279,25.243965 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2783-2782,17:44:03.279,25.244458 s,492 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2784,17:44:03.279,25.244483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2785-2784,17:44:03.281,25.246455 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2786,17:44:03.282,25.246957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2787-2786,17:44:03.282,25.247456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2788,17:44:03.282,25.247480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2789-2788,17:44:03.284,25.249456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2790,17:44:03.285,25.249961 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2791-2790,17:44:03.285,25.250455 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2792,17:44:03.285,25.250480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2793-2792,17:44:03.287,25.252455 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2794,17:44:03.288,25.252957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2795-2794,17:44:03.288,25.253455 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2796,17:44:03.288,25.253479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2797-2796,17:44:03.290,25.255456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2798,17:44:03.291,25.255961 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2799-2798,17:44:03.291,25.256455 s,495 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2800,17:44:03.291,25.256479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2801-2800,17:44:03.293,25.258459 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2802,17:44:03.493,25.457998 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2803-2802,17:44:03.494,25.459467 s,1.469 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2804,17:44:03.494,25.459504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2805-2804,17:44:03.496,25.461453 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2806,17:44:03.696,25.661009 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2807-2806,17:44:03.696,25.661459 s,450 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2808,17:44:03.696,25.661497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2809-2808,17:44:03.698,25.663451 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2810,17:44:03.898,25.863006 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2811-2810,17:44:03.899,25.864456 s,1.450 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2812,17:44:03.899,25.864490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2813-2812,17:44:03.901,25.866445 s,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2814,17:44:04.101,26.066042 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2815-2814,17:44:04.102,26.067440 s,1.397 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2816,17:44:04.102,26.067484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2817-2816,17:44:04.104,26.069440 s,1.957 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2818,17:44:04.304,26.269024 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2819-2818,17:44:04.305,26.270456 s,1.432 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2820,17:44:04.305,26.270494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2821-2820,17:44:04.307,26.272438 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2822,17:44:04.507,26.472043 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2823-2822,17:44:04.508,26.473433 s,1.390 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2824,17:44:04.508,26.473470 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2825-2824,17:44:04.510,26.475432 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2826,17:44:04.710,26.675053 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2827-2826,17:44:04.711,26.676426 s,1.373 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2828,17:44:04.711,26.676465 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2829-2828,17:44:04.713,26.678449 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2830,17:44:04.913,26.878041 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2831-2830,17:44:04.914,26.879423 s,1.382 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2832,17:44:04.914,26.879458 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2833-2832,17:44:04.916,26.881424 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2834,17:44:05.116,27.081075 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2835-2834,17:44:05.117,27.082449 s,1.373 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2836,17:44:05.117,27.082493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2837-2836,17:44:05.119,27.084422 s,1.929 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2838,17:44:05.319,27.284059 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2839-2838,17:44:05.319,27.284430 s,371 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2840,17:44:05.319,27.284465 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2841-2840,17:44:05.321,27.286417 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2842,17:44:05.521,27.486126 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2843-2842,17:44:05.522,27.487435 s,1.309 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2844,17:44:05.522,27.487488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2845-2844,17:44:05.524,27.489414 s,1.926 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2846,17:44:05.724,27.689111 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2847-2846,17:44:05.725,27.690425 s,1.314 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2848,17:44:05.725,27.690467 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2849-2848,17:44:05.727,27.692411 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2850,17:44:05.927,27.892084 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2851-2850,17:44:05.928,27.893411 s,1.327 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2852,17:44:05.928,27.893445 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2853-2852,17:44:05.930,27.895406 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2854,17:44:06.131,28.095131 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2855-2854,17:44:06.132,28.096402 s,1.271 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2856,17:44:06.132,28.096451 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2857-2856,17:44:06.134,28.098399 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2858,17:44:06.334,28.298115 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2859-2858,17:44:06.335,28.299412 s,1.297 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2860,17:44:06.335,28.299450 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2861-2860,17:44:06.337,28.301397 s,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2862,17:44:06.537,28.501282 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2863-2862,17:44:06.538,28.502510 s,1.228 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2864,17:44:06.538,28.502566 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2865-2864,17:44:06.540,28.504400 s,1.834 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2866,17:44:06.740,28.704127 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2867-2866,17:44:06.741,28.705415 s,1.288 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2868,17:44:06.741,28.705457 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2869-2868,17:44:06.743,28.707391 s,1.934 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2870,17:44:06.943,28.907119 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2871-2870,17:44:06.944,28.908393 s,1.273 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2872,17:44:06.944,28.908424 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2873-2872,17:44:06.946,28.910386 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2874,17:44:07.146,29.110143 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2875-2874,17:44:07.147,29.111401 s,1.257 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2876,17:44:07.147,29.111438 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2877-2876,17:44:07.149,29.113382 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2878,17:44:07.349,29.313134 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2879-2878,17:44:07.350,29.314382 s,1.248 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2880,17:44:07.350,29.314413 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2881-2880,17:44:07.352,29.316383 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2882,17:44:07.552,29.516148 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2883-2882,17:44:07.552,29.516414 s,266 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2884,17:44:07.552,29.516463 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2885-2884,17:44:07.554,29.518450 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2886,17:44:07.754,29.718162 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2887-2886,17:44:07.755,29.719393 s,1.231 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
-URB,2888,17:44:07.755,29.719435 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2889-2888,17:44:07.757,29.721372 s,1.937 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2890,17:44:07.957,29.921162 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2891-2890,17:44:07.958,29.922380 s,1.217 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,2892,17:44:07.958,29.922416 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2893-2892,17:44:07.960,29.924364 s,1.948 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2894,17:44:08.160,30.124182 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2895-2894,17:44:08.160,30.124382 s,200 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success)\r
-URB,2896,17:44:08.160,30.124421 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2897-2896,17:44:08.162,30.126362 s,1.941 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2898,17:44:08.362,30.326171 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2899-2898,17:44:08.363,30.327364 s,1.193 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success)\r
-URB,2900,17:44:08.363,30.327396 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2901-2900,17:44:08.365,30.329357 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2902,17:44:08.565,30.529243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2903-2902,17:44:08.566,30.530370 s,1.128 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success)\r
-URB,2904,17:44:08.566,30.530416 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2905-2904,17:44:08.568,30.532354 s,1.939 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2906,17:44:08.768,30.732226 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2907-2906,17:44:08.769,30.733354 s,1.128 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,2908,17:44:08.769,30.733390 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2909-2908,17:44:08.771,30.735349 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2910,17:44:08.971,30.935204 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2911-2910,17:44:08.972,30.936358 s,1.153 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,2912,17:44:08.972,30.936394 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2913-2912,17:44:08.974,30.938344 s,1.951 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2914,17:44:09.174,31.138386 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2915-2914,17:44:09.176,31.140614 s,2.228 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2916,17:44:09.176,31.141138 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2917-2916,17:44:09.178,31.142377 s,1.239 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2918,17:44:09.378,31.342234 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2919-2918,17:44:09.379,31.343364 s,1.130 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2920,17:44:09.379,31.343409 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2921-2920,17:44:09.381,31.345338 s,1.929 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2922,17:44:09.581,31.545238 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2923-2922,17:44:09.582,31.546405 s,1.167 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2924,17:44:09.582,31.546476 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2925-2924,17:44:09.584,31.548397 s,1.921 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2926,17:44:09.784,31.748253 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2927-2926,17:44:09.785,31.749373 s,1.120 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2928,17:44:09.785,31.749432 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2929-2928,17:44:09.787,31.751333 s,1.901 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2930,17:44:09.987,31.951274 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2931-2930,17:44:09.989,31.953326 s,2.052 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2932,17:44:09.989,31.953367 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2933-2932,17:44:09.991,31.955325 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2934,17:44:10.191,32.155260 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2935-2934,17:44:10.192,32.156329 s,1.070 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2936,17:44:10.192,32.156369 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2937-2936,17:44:10.194,32.158322 s,1.953 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2938,17:44:10.394,32.358247 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2939-2938,17:44:10.395,32.359313 s,1.066 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2940,17:44:10.395,32.359348 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2941-2940,17:44:10.397,32.361314 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2942,17:44:10.597,32.561287 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2943-2942,17:44:10.599,32.563314 s,2.027 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2944,17:44:10.599,32.563356 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2945-2944,17:44:10.601,32.565313 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2946,17:44:10.801,32.765267 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2947-2946,17:44:10.802,32.766328 s,1.061 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2948,17:44:10.802,32.766362 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2949-2948,17:44:10.804,32.768308 s,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2950,17:44:11.004,32.968270 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2951-2950,17:44:11.006,32.970303 s,2.033 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2952,17:44:11.006,32.970338 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2953-2952,17:44:11.008,32.972304 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2954,17:44:11.208,33.172295 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2955-2954,17:44:11.210,33.174324 s,2.029 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2956,17:44:11.210,33.174368 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2957-2956,17:44:11.212,33.176304 s,1.936 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2958,17:44:11.412,33.376288 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2959-2958,17:44:11.414,33.378296 s,2.008 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2960,17:44:11.414,33.378329 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2961-2960,17:44:11.416,33.380306 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2962,17:44:11.616,33.580321 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2963-2962,17:44:11.618,33.582321 s,2.000 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2964,17:44:11.618,33.582364 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2965-2964,17:44:11.620,33.584295 s,1.931 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2966,17:44:11.820,33.784305 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2967-2966,17:44:11.822,33.786293 s,1.988 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2968,17:44:11.822,33.786326 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2969-2968,17:44:11.824,33.788296 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2970,17:44:12.024,33.988313 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2971-2970,17:44:12.026,33.990287 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2972,17:44:12.026,33.990323 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2973-2972,17:44:12.028,33.992287 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2974,17:44:12.228,34.192334 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2975-2974,17:44:12.230,34.194289 s,1.955 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2976,17:44:12.230,34.194328 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2977-2976,17:44:12.232,34.196282 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2978,17:44:12.432,34.396337 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2979-2978,17:44:12.433,34.398278 s,1.941 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2980,17:44:12.434,34.398314 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2981-2980,17:44:12.435,34.400277 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2982,17:44:12.636,34.600355 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2983-2982,17:44:12.637,34.602271 s,1.917 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2984,17:44:12.638,34.602318 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2985-2984,17:44:12.639,34.604272 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2986,17:44:12.840,34.804346 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2987-2986,17:44:12.841,34.806287 s,1.941 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2988,17:44:12.842,34.806326 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2989-2988,17:44:12.843,34.808271 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2990,17:44:13.043,35.007405 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2991-2990,17:44:13.044,35.009268 s,1.863 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
-URB,2992,17:44:13.045,35.009318 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2993-2992,17:44:13.046,35.011270 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2994,17:44:13.247,35.211376 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2995-2994,17:44:13.248,35.213259 s,1.883 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,2996,17:44:13.248,35.213297 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,2997-2996,17:44:13.249,35.214282 s,985 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,2998,17:44:13.449,35.413373 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,2999-2998,17:44:13.450,35.415252 s,1.879 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,3000,17:44:13.450,35.415287 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3001-3000,17:44:13.452,35.417254 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3002,17:44:13.652,35.616388 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3003-3002,17:44:13.653,35.618251 s,1.864 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,3004,17:44:13.653,35.618291 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3005-3004,17:44:13.655,35.620252 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3006,17:44:13.855,35.819381 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3007-3006,17:44:13.856,35.821251 s,1.869 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,3008,17:44:13.856,35.821283 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3009-3008,17:44:13.858,35.823249 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3010,17:44:14.058,36.022442 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3011-3010,17:44:14.059,36.024267 s,1.826 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,3012,17:44:14.059,36.024319 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3013-3012,17:44:14.061,36.026260 s,1.941 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3014,17:44:14.261,36.225411 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3015-3014,17:44:14.262,36.227242 s,1.831 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,3016,17:44:14.262,36.227285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3017-3016,17:44:14.264,36.229241 s,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3018,17:44:14.464,36.428427 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3019-3018,17:44:14.465,36.430249 s,1.822 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,3020,17:44:14.465,36.430285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3021-3020,17:44:14.467,36.432237 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3022,17:44:14.667,36.631483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3023-3022,17:44:14.668,36.633340 s,1.857 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
-URB,3024,17:44:14.669,36.633598 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3025-3024,17:44:14.670,36.635238 s,1.640 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3026,17:44:14.870,36.834453 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3027-3026,17:44:14.871,36.836267 s,1.814 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3028,17:44:14.871,36.836320 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3029-3028,17:44:14.873,36.838287 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3030,17:44:15.073,37.037457 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3031-3030,17:44:15.074,37.039228 s,1.772 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3032,17:44:15.074,37.039285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3033-3032,17:44:15.076,37.041226 s,1.942 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3034,17:44:15.276,37.240460 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3035-3034,17:44:15.277,37.242230 s,1.770 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3036,17:44:15.277,37.242280 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3037-3036,17:44:15.279,37.244225 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3038,17:44:15.479,37.443460 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3039-3038,17:44:15.480,37.445219 s,1.759 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3040,17:44:15.480,37.445264 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3041-3040,17:44:15.482,37.447218 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3042,17:44:15.682,37.646461 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3043-3042,17:44:15.683,37.648213 s,1.752 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3044,17:44:15.683,37.648253 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3045-3044,17:44:15.685,37.650214 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3046,17:44:15.885,37.849462 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3047-3046,17:44:15.886,37.851209 s,1.746 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3048,17:44:15.886,37.851247 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3049-3048,17:44:15.888,37.853208 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3050,17:44:16.088,38.052541 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3051-3050,17:44:16.089,38.054228 s,1.688 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3052,17:44:16.089,38.054373 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3053-3052,17:44:16.091,38.056220 s,1.847 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3054,17:44:16.291,38.255483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3055-3054,17:44:16.292,38.257199 s,1.717 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3056,17:44:16.292,38.257234 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3057-3056,17:44:16.294,38.259200 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3058,17:44:16.494,38.458488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3059-3058,17:44:16.495,38.460196 s,1.708 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3060,17:44:16.495,38.460231 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3061-3060,17:44:16.497,38.462220 s,1.989 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3062,17:44:16.697,38.661501 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3063-3062,17:44:16.698,38.663191 s,1.690 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3064,17:44:16.698,38.663232 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3065-3064,17:44:16.700,38.665190 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-URB,3066,17:44:16.900,38.864494 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,3067-3066,17:44:16.901,38.866188 s,1.694 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
-URB,3068,17:44:16.901,38.866223 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,3069-3068,17:44:16.903,38.868189 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
-\r
-This report was generated by USBlyzer http://www.usblyzer.com/\r
+++ /dev/null
-. tools used for reversing under windows (all free or eval version)
- . ST set tools package contains a working programmer (stvp)
- . http://www.st.com/internet/com/SOFTWARE_RESOURCES/TOOL/TOOLSET/sttoolset.zip
- . IAR latest version contains a working debugger
- . http://www.iar.com/website1/1.0.1.0/68/1/
- . usblyzer to snif the corresponding usb frames
- . http://www.usblyzer.com/
-
-. Linux
- . usb kernel module compiled with debugging enabled
- . usbmon
- . libusb
-
-. stm32l chip
- . http://www.st.com/internet/mcu/product/248820.jsp
\ No newline at end of file
+++ /dev/null
-USBlyzer Report\r
-\r
-Capture List\r
-\r
-Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
-START,0001,15:09:38.756,,,,,,,,,,,,\r
-Create,0002,15:12:32.934,174.174733 s,,Create,stvp.exe,,,,FFFFFA80074F4960h,,WinUsb,FFFFFA8006FD8320h,\r
-Create,0003-0002,15:12:32.935,174.174759 s,26 us,Create,stvp.exe,,,,FFFFFA80074F4960h,,WinUsb,FFFFFA8006FD8320h,Success\r
-URB,0004,15:12:32.935,174.174880 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0005-0004,15:12:32.936,174.176236 s,1.356 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0006,15:12:32.936,174.176269 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0007-0006,15:12:32.938,174.178222 s,1.953 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),23 80 83 04 48 37\r
-URB,0008,15:12:32.938,174.178249 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0009-0008,15:12:32.939,174.179221 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0010,15:12:32.939,174.179239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0011-0010,15:12:32.941,174.181221 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 01\r
-URB,0012,15:12:32.941,174.181243 s,,Bulk or Interrupt Transfer,16 bytes data,F3 07 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F3 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0013-0012,15:12:32.942,174.182221 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0014,15:12:32.943,174.182760 s,,Bulk or Interrupt Transfer,16 bytes data,F2 30 A3 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 30 A3 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0015-0014,15:12:32.944,174.184221 s,1.462 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0016,15:12:32.944,174.184238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0017-0016,15:12:32.945,174.185221 s,982 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0018,15:12:32.945,174.185242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 32 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0019-0018,15:12:32.946,174.186221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0020,15:12:32.946,174.186239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0021-0020,15:12:32.948,174.188221 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0022,15:12:32.948,174.188240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00\r
-URB,0023-0022,15:12:32.949,174.189220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0024,15:12:32.949,174.189237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0025-0024,15:12:32.951,174.191221 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0026,15:12:32.951,174.191240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0027-0026,15:12:32.952,174.192221 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0028,15:12:32.952,174.192237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0029-0028,15:12:32.953,174.193222 s,985 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 03,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 03\r
-URB,0030,15:12:32.953,174.193242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00\r
-URB,0031-0030,15:12:32.954,174.194221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0032,15:12:32.954,174.194239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0033-0032,15:12:32.956,174.196221 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0034,15:12:32.956,174.196241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0035-0034,15:12:32.957,174.197221 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0036,15:12:32.957,174.197240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0037-0036,15:12:32.959,174.199220 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 00\r
-URB,0038,15:12:32.959,174.199240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 FC ED 00 E0 01 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 FC ED 00 E0 01 00 00 00 00 00 00 00 00 00\r
-URB,0039-0038,15:12:32.960,174.200220 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0040,15:12:32.960,174.200237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0041-0040,15:12:32.961,174.201221 s,984 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0042,15:12:32.961,174.201241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 0C ED 00 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 0C ED 00 E0 04 00 FA 05 00 00 00 00 00 00\r
-URB,0043-0042,15:12:32.962,174.202220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0044,15:12:32.962,174.202237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0045-0044,15:12:32.964,174.204220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0046,15:12:32.964,174.204243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 0C ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 0C ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0047-0046,15:12:32.965,174.205221 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0048,15:12:32.965,174.205238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0049-0048,15:12:32.967,174.207220 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 00 00 05 FA,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 00 00 05 FA\r
-URB,0050,15:12:32.967,174.207239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0051-0050,15:12:32.968,174.208219 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0052,15:12:32.968,174.208236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0053-0052,15:12:32.969,174.209220 s,984 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 02,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 02\r
-URB,0054,15:12:32.969,174.209241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0055-0054,15:12:32.970,174.210220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0056,15:12:32.970,174.210237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0057-0056,15:12:32.972,174.212221 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 00\r
-URB,0058,15:12:32.972,174.212240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 FC ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 FC ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0059-0058,15:12:32.973,174.213220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0060,15:12:32.973,174.213237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0061-0060,15:12:32.975,174.215220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0062,15:12:32.975,174.215241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 31 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0063-0062,15:12:32.976,174.216220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0064,15:12:32.976,174.216238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0065-0064,15:12:32.977,174.217220 s,983 us,Bulk or Interrupt Transfer,12 bytes data,80 00 00 00 77 14 A0 2B...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 77 14 A0 2B 00 00 00 00\r
-URB,0066,15:12:32.977,174.217240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 04 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 04 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0067-0066,15:12:32.978,174.218220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0068,15:12:32.978,174.218237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0069-0068,15:12:32.980,174.220220 s,1.983 ms,Bulk or Interrupt Transfer,4 bytes data,16 64 18 10,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),16 64 18 10\r
-URB,0070,15:12:32.980,174.220240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0071-0070,15:12:32.981,174.221220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0072,15:12:32.981,174.221237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0073-0072,15:12:32.983,174.223220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0074,15:12:32.983,174.223243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 0F 00 00 00 20 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 0F 00 00 00 20 00 00 00 00 00 00 00 00 00\r
-URB,0075-0074,15:12:32.984,174.224222 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0076,15:12:32.984,174.224239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0077-0076,15:12:32.985,174.225220 s,981 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0078,15:12:32.985,174.225239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 11 00 40 00 20 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 11 00 40 00 20 00 00 00 00 00 00 00 00 00\r
-URB,0079-0078,15:12:32.986,174.226221 s,981 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0080,15:12:32.986,174.226238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0081-0080,15:12:32.988,174.228225 s,1.987 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0082,15:12:32.988,174.228257 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 10 00 00 00 01 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 10 00 00 00 01 00 00 00 00 00 00 00 00 00\r
-URB,0083-0082,15:12:32.989,174.229225 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0084,15:12:32.989,174.229243 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0085-0084,15:12:32.991,174.231221 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0086,15:12:32.991,174.231244 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 00 00 00 20 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 08 00 00 00 20 04 00 00 00 00 00 00 00 00 00\r
-URB,0087-0086,15:12:32.992,174.232221 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0088,15:12:32.992,174.232239 s,,Bulk or Interrupt Transfer,4 bytes data,55 AA 88 00,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,55 AA 88 00\r
-URB,0089-0088,15:12:32.993,174.233221 s,982 us,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0090,15:12:32.993,174.233239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0091-0090,15:12:32.994,174.234222 s,983 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0092,15:12:32.994,174.234242 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0093-0092,15:12:32.996,174.236221 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0094,15:12:32.996,174.236242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 00 00 20 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 00 00 20 04 00 00 00 00 00 00 00 00 00\r
-URB,0095-0094,15:12:32.997,174.237221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0096,15:12:32.997,174.237238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0097-0096,15:12:32.999,174.239222 s,1.984 ms,Bulk or Interrupt Transfer,4 bytes data,55 AA 88 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),55 AA 88 00\r
-URB,0098,15:12:32.999,174.239260 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0099-0098,15:12:33.000,174.240228 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0100,15:12:33.000,174.240266 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0101-0100,15:12:33.002,174.242226 s,1.960 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0102,15:12:33.002,174.242263 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 04 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 04 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0103-0102,15:12:33.003,174.243226 s,964 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0104,15:12:33.003,174.243245 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0105-0104,15:12:33.005,174.245219 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,16 64 18 10,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),16 64 18 10\r
-URB,0106,15:12:33.005,174.245240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0107-0106,15:12:33.006,174.246220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0108,15:12:33.006,174.246237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0109-0108,15:12:33.008,174.248219 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0110,15:12:33.008,174.248242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 1C 3C 02 40 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 1C 3C 02 40 04 00 00 00 00 00 00 00 00 00\r
-URB,0111-0110,15:12:33.009,174.249219 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0112,15:12:33.009,174.249236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0113-0112,15:12:33.010,174.250220 s,984 us,Bulk or Interrupt Transfer,4 bytes data,AA 00 78 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),AA 00 78 00\r
-URB,0114,15:12:33.010,174.250239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0115-0114,15:12:33.011,174.251219 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0116,15:12:33.011,174.251236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0117-0116,15:12:33.013,174.253220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0118,15:12:33.013,174.253240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 20 3C 02 40 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 20 3C 02 40 04 00 00 00 00 00 00 00 00 00\r
-URB,0119-0118,15:12:33.014,174.254220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0120,15:12:33.014,174.254239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0121-0120,15:12:33.016,174.256221 s,1.982 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00\r
-URB,0122,15:12:33.016,174.256241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0123-0122,15:12:33.017,174.257219 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0124,15:12:33.017,174.257236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0125-0124,15:12:33.018,174.258220 s,984 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0126,15:12:33.018,174.258252 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 00 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 00 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0127-0126,15:12:33.019,174.259220 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0128,15:12:33.019,174.259241 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0129-0128,15:12:33.097,174.337240 s,77.999 ms,Bulk or Interrupt Transfer,4096 bytes data,28 06 00 20 69 58 00 08...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),28 06 00 20 69 58 00 08 91 54 00 08 93 54 00 08 95 54 00 08 97 54 00 08 99 54 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9B 54 00 08 9D 54 00 08 00 00 00 00 9F 54 00 08 A1 54 00 08 B1 58 00 08 B5 58 00 08 B9 58 00 08 75 56 00 08 C1 58 00 08 C5 58 00 08 27 56 00 08 CD 58 00 08 D1 58 00 08 D5 58 00 08 D9 58 00 08 DD 58 00 08 E1 58 00 08 E5 58 00 08 E9 58 00 08 ED 58 00 08 F1 58 00 08 F5 58 00 08 F9 58 00 08 FD 58 00 08 01 59 00 08 05 59 00 08 09 59 00 08 0D 59 00 08 11 59 00 08 15 59 00 08 19 59 00 08 1D 59 00 08 21 59 00 08 25 59 00 08 29 59 00 08 2D 59 00 08 31 59 00 08 35 59 00 08 39 59 00 08 3D 59 00 08 41 59 00 08 45 59 00 08 49 59 00 08 4D 59 00 08 51 59 00 08 55 59 00 08 59 59 00 08 5D 59 00 08 61 59 00 08 10 B5 84 B0 20 20 AD F8 00 00 AD F8\r
-URB,0130,15:12:33.097,174.337275 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0131-0130,15:12:33.099,174.339219 s,1.944 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0132,15:12:33.099,174.339238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0133-0132,15:12:33.101,174.341218 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0134,15:12:33.103,174.343580 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 10 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 10 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0135-0134,15:12:33.105,174.345221 s,1.641 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0136,15:12:33.105,174.345247 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0137-0136,15:12:33.183,174.423249 s,78.002 ms,Bulk or Interrupt Transfer,4096 bytes data,01 01 43 EA 81 31 11 43...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),01 01 43 EA 81 31 11 43 81 61 FF F7 CC FD 01 F0 A4 FD 31 BD 38 B5 04 46 01 25 07 E0 2B 46 00 22 11 46 20 46 FF F7 44 FE 64 1C 6D 1C 20 78 00 28 02 D0 ED B2 08 2D F1 D3 31 BD 38 B5 04 46 01 25 06 E0 00 22 11 46 00 A8 FF F7 32 FE A4 1C 6D 1C 20 88 00 28 1B D0 ED B2 08 2D 18 D2 8D F8 00 00 20 88 00 F4 70 40 B0 F5 80 4F 09 D0 B0 F5 00 4F 2B 46 E6 D1 00 22 01 21 00 A8 FF F7 19 FE E5 E7 2B 46 01 22 00 21 00 A8 FF F7 12 FE DE E7 31 BD 80 B5 04 20 01 F0 65 FD 00 28 FA D1 00 20 3F 49 02 46 02 E0 41 F8 20 20 40 1C 10 28 FA D3 BD E8 01 40 01 F0 52 BD 2D E9 F0 43 83 B0 05 46 0E 46 14 46 00 A8 07 21 01 F0 BB FD 00 2D 5E D0 28 46 00 27 02 E0 7F 1C FF B2 40 1C 01 78 00 29 F9 D1 28 46 FF F7 97 FF 20 46 00 F0 87 FB 4F F0 00 08 0A E0 20 46 00 F0 81 FB 09 F1 01 09 5F FA 89 F9\r
-URB,0138,15:12:33.183,174.423297 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0139-0138,15:12:33.185,174.425217 s,1.920 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0140,15:12:33.185,174.425240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0141-0140,15:12:33.187,174.427221 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0142,15:12:33.189,174.428964 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0143-0142,15:12:33.190,174.430218 s,1.254 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0144,15:12:33.190,174.430240 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0145-0144,15:12:33.268,174.508249 s,78.008 ms,Bulk or Interrupt Transfer,4096 bytes data,0A 98 78 60 0C 98 F8 60...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),0A 98 78 60 0C 98 F8 60 0E 98 78 61 0D 98 38 61 FF F7 B1 FA 4F F4 00 60 00 F0 6F FE 00 20 00 F0 86 FE 00 20 00 F0 5B FE 00 20 00 F0 6D F8 FF F7 7F FD 01 20 00 F0 1D FF 01 20 00 F0 16 FE FE F7 7D FD 01 20 20 70 40 46 10 B0 BD E8 F0 81 00 00 18 ED 00 E0 00 E4 00 E0 10 E0 00 E0 34 01 00 20 00 00 02 40 00 04 02 40 00 08 02 40 00 0C 02 40 00 10 02 40 00 14 02 40 00 24 01 40 1C 38 02 40 22 02 00 20 23 02 00 20 10 B5 04 00 06 D0 01 2C 04 D0 B5 21 0F F2 00 20 FF F7 DC FB DF F8 C0 01 01 68 49 08 54 EA 41 01 01 60 10 BD 10 B5 04 00 06 D0 01 2C 04 D0 CB 21 0F F2 DC 10 FF F7 CA FB DF F8 9C 01 00 2C 01 68 03 D0 41 F0 02 01 01 60 10 BD 21 F0 02 01 01 60 10 BD 10 B5 04 00 06 D0 01 2C 04 D0 E6 21 0F F2 B0 10 FF F7 B3 FB DF F8 70 01 00 2C 01 68 03 D0 41 F0 04 01 01 60 10 BD\r
-URB,0146,15:12:33.268,174.508317 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0147-0146,15:12:33.270,174.510218 s,1.900 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0148,15:12:33.270,174.510240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0149-0148,15:12:33.272,174.512259 s,2.019 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0150,15:12:33.274,174.514519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 30 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 30 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0151-0150,15:12:33.275,174.515232 s,712 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0152,15:12:33.275,174.515266 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0153-0152,15:12:33.353,174.593260 s,77.994 ms,Bulk or Interrupt Transfer,4096 bytes data,04 60 10 BD 10 B5 04 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),04 60 10 BD 10 B5 04 00 09 D0 01 2C 07 D0 05 2C 05 D0 40 F2 BD 11 0F F2 78 40 FE F7 1B FC DF F8 28 04 00 21 01 70 04 70 10 BD 10 B5 04 00 07 D0 01 2C 05 D0 40 F2 D5 11 0F F2 54 40 FE F7 0A FC DF F8 08 04 04 60 10 BD 10 B5 04 00 0B D0 01 2C 09 D0 02 2C 07 D0 03 2C 05 D0 40 F2 B7 21 0F F2 30 40 FE F7 F7 FB DF F8 E8 03 01 68 89 08 54 EA 81 01 01 60 10 BD DF F8 D8 03 00 68 00 F0 0C 00 70 47 10 B5 04 00 15 D0 80 2C 13 D0 90 2C 11 D0 A0 2C 0F D0 B0 2C 0D D0 C0 2C 0B D0 D0 2C 09 D0 E0 2C 07 D0 F0 2C 05 D0 40 F2 ED 21 0F F2 E0 30 FE F7 D0 FB DF F8 98 03 01 68 21 F0 F0 01 21 43 01 60 10 BD 10 B5 04 00 11 D0 B4 F5 80 6F 0E D0 B4 F5 A0 6F 0B D0 B4 F5 C0 6F 08 D0 B4 F5 E0 6F 05 D0 4F F4 43 71 0F F2 A8 30 FE F7 B3 FB DF F8 60 03 01 68 21 F4 E0 61 21 43 01 60 10 BD 10 B5\r
-URB,0154,15:12:33.353,174.593333 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0155-0154,15:12:33.355,174.595215 s,1.882 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0156,15:12:33.355,174.595238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0157-0156,15:12:33.357,174.597214 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0158,15:12:33.359,174.599172 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 40 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 40 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0159-0158,15:12:33.360,174.600219 s,1.047 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0160,15:12:33.360,174.600245 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0161-0160,15:12:33.438,174.678234 s,77.989 ms,Bulk or Interrupt Transfer,4096 bytes data,B8 F1 04 0F 0E D0 B8 F1...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),B8 F1 04 0F 0E D0 B8 F1 05 0F 0B D0 B8 F1 06 0F 08 D0 B8 F1 07 0F 05 D0 40 F2 FF 21 0F F2 8C 10 FD F7 18 FC 07 21 14 2D 0B D3 E0 68 A5 F1 14 02 02 EB 42 02 91 40 88 43 08 FA 02 F1 08 43 E0 60 16 E0 0A 2D 0B D3 20 69 A5 F1 0A 02 02 EB 42 02 91 40 88 43 08 FA 02 F1 08 43 20 61 08 E0 60 69 05 EB 45 02 91 40 88 43 08 FA 02 F1 08 43 60 61 1F 21 07 2E 09 D2 20 6C 07 EB 87 02 91 40 88 43 05 FA 02 F1 08 43 20 64 33 E0 0D 2E 0A D2 E0 6B F2 1F 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 E0 63 26 E0 13 2E 0B D2 A0 6B A6 F1 0D 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 A0 63 18 E0 19 2E 0B D2 60 6B A6 F1 13 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 60 63 0A E0 20 6B A6 F1 19 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 20 63 BD E8 F0 81 10 B5 04 46 DF F8 3C 00 84 42\r
-URB,0162,15:12:33.438,174.678274 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0163-0162,15:12:33.440,174.680211 s,1.937 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0164,15:12:33.440,174.680231 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0165-0164,15:12:33.441,174.681211 s,980 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0166,15:12:33.443,174.682929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 50 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 50 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0167-0166,15:12:33.443,174.683214 s,285 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0168,15:12:33.443,174.683237 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0169-0168,15:12:33.521,174.761232 s,77.994 ms,Bulk or Interrupt Transfer,4096 bytes data,41 02 08 4B 1B 68 03 EB...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),41 02 08 4B 1B 68 03 EB 42 02 52 89 96 3A 41 F2 F3 23 92 B2 9A 42 ED D3 FF 20 70 47 00 20 70 47 95 01 00 20 10 02 00 20 B8 01 00 20 24 02 00 20 30 01 00 20 F8 01 00 20 58 58 00 08 60 58 00 08 B0 01 00 20 A8 01 00 20 18 02 00 20 97 01 00 20 98 01 00 20 1A 02 00 20 1C 02 00 20 1E 02 00 20 84 58 00 08 00 01 00 08 00 02 00 00 00 00 A0 FF A0 00 20 00 00 00 60 FF 20 FF 60 00 00 00 00 00 10 B5 08 4C 00 20 20 83 01 20 00 F0 D8 F8 01 00 02 D0 20 8B 08 43 20 83 20 8B 00 28 01 D0 FF F7 61 FA 10 BD DC 01 00 20 2D E9 F8 4F 01 20 80 F3 10 88 DF F8 84 03 DF F8 84 13 02 68 0A 60 00 21 01 60 08 46 80 F3 10 88 DF F8 74 43 DF F8 74 B3 DF F8 74 63 DF F8 64 03 00 68 41 1E DF F8 5C 23 11 60 00 28 00 F0 A9 80 DF F8 60 73 38 78 40 1E 38 70 DF F8 5C 03 01 78 49 1E 01 70 C9 B2 00 29\r
-URB,0170,15:12:33.521,174.761271 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0171-0170,15:12:33.523,174.763211 s,1.940 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0172,15:12:33.523,174.763233 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0173-0172,15:12:33.525,174.765209 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0174,15:12:33.527,174.766919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 60 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 60 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0175-0174,15:12:33.528,174.768211 s,1.291 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0176,15:12:33.528,174.768234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0177-0176,15:12:33.604,174.844240 s,76.007 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0178,15:12:33.604,174.844301 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0179-0178,15:12:33.606,174.846214 s,1.913 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0180,15:12:33.606,174.846234 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0181-0180,15:12:33.608,174.848208 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0182,15:12:33.610,174.849977 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 70 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 70 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0183-0182,15:12:33.610,174.850213 s,236 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0184,15:12:33.610,174.850235 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0185-0184,15:12:33.687,174.927228 s,76.993 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0186,15:12:33.687,174.927268 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0187-0186,15:12:33.689,174.929206 s,1.939 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0188,15:12:33.689,174.929226 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0189-0188,15:12:33.690,174.930206 s,980 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0190,15:12:33.692,174.932148 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 80 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 80 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0191-0190,15:12:33.693,174.933211 s,1.062 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0192,15:12:33.693,174.933237 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0193-0192,15:12:33.769,175.009241 s,76.004 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0194,15:12:33.769,175.009307 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0195-0194,15:12:33.771,175.011249 s,1.942 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0196,15:12:33.771,175.011349 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0197-0196,15:12:33.773,175.013221 s,1.872 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0198,15:12:33.775,175.015272 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 90 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 90 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0199-0198,15:12:33.777,175.017218 s,1.946 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0200,15:12:33.777,175.017254 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0201-0200,15:12:33.853,175.093245 s,75.991 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0202,15:12:33.853,175.093309 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0203-0202,15:12:33.855,175.095204 s,1.895 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0204,15:12:33.855,175.095227 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0205-0204,15:12:33.857,175.097203 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0206,15:12:33.859,175.098972 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 A0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 A0 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0207-0206,15:12:33.859,175.099209 s,237 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0208,15:12:33.859,175.099233 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0209-0208,15:12:33.936,175.176223 s,76.990 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0210,15:12:33.936,175.176266 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0211-0210,15:12:33.938,175.178203 s,1.937 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0212,15:12:33.938,175.178223 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0213-0212,15:12:33.940,175.180202 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0214,15:12:33.942,175.181915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 B0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 B0 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0215-0214,15:12:33.943,175.183205 s,1.291 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0216,15:12:33.943,175.183234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0217-0216,15:12:34.019,175.259226 s,75.993 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0218,15:12:34.019,175.259275 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0219-0218,15:12:34.021,175.261201 s,1.926 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0220,15:12:34.021,175.261221 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0221-0220,15:12:34.023,175.263200 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0222,15:12:34.025,175.265126 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 C0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 C0 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0223-0222,15:12:34.026,175.266209 s,1.083 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0224,15:12:34.026,175.266234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0225-0224,15:12:34.102,175.342223 s,75.989 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0226,15:12:34.102,175.342270 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0227-0226,15:12:34.104,175.344199 s,1.929 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0228,15:12:34.104,175.344219 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0229-0228,15:12:34.105,175.345202 s,983 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0230,15:12:34.107,175.346917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 D0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 D0 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0231-0230,15:12:34.107,175.347202 s,285 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0232,15:12:34.107,175.347225 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0233-0232,15:12:34.184,175.424221 s,76.996 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0234,15:12:34.184,175.424272 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0235-0234,15:12:34.186,175.426198 s,1.926 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0236,15:12:34.186,175.426219 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0237-0236,15:12:34.188,175.428197 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0238,15:12:34.190,175.429912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 E0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 E0 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0239-0238,15:12:34.191,175.431198 s,1.286 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0240,15:12:34.191,175.431220 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0241-0240,15:12:34.267,175.507225 s,76.005 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0242,15:12:34.267,175.507282 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0243-0242,15:12:34.269,175.509198 s,1.916 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
-URB,0244,15:12:34.269,175.509228 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0245-0244,15:12:34.271,175.511235 s,2.007 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-URB,0246,15:12:34.274,175.513803 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 F0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,,F2 07 00 F0 00 08 00 10 00 00 00 00 00 00 00 00\r
-URB,0247-0246,15:12:34.274,175.514220 s,417 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,Success (Success)\r
-URB,0248,15:12:34.274,175.514296 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0249-0248,15:12:34.351,175.591234 s,76.938 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0250,15:12:34.351,175.591304 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0251-0250,15:12:34.353,175.593195 s,1.891 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,Success (Success)\r
-URB,0252,15:12:34.353,175.593216 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
-URB,0253-0252,15:12:34.354,175.594194 s,978 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
-\r
-This report was generated by USBlyzer http://www.usblyzer.com/\r
+++ /dev/null
-USBlyzer Report\r
-\r
-Capture List\r
-\r
-Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
-START,0001,17:41:03.981,,,,,,,,,,,,\r
-URB,0002,17:41:09.226,5.245187 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0003-0002,17:41:09.227,5.246467 s,1.280 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0004,17:41:09.227,5.246524 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0005-0004,17:41:09.229,5.248463 s,1.939 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
-URB,0006,17:41:09.229,5.248519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0007-0006,17:41:09.230,5.249462 s,943 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0008,17:41:09.230,5.249491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0009-0008,17:41:09.232,5.251472 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0010,17:41:09.232,5.251514 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0011-0010,17:41:09.233,5.252465 s,951 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0012,17:41:09.233,5.252495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0013-0012,17:41:09.235,5.254462 s,1.967 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
-URB,0014,17:41:09.235,5.254493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0015-0014,17:41:09.236,5.255462 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0016,17:41:09.236,5.255498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0017-0016,17:41:09.238,5.257465 s,1.967 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0018,17:41:09.238,5.257575 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 36 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 36 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0019-0018,17:41:09.239,5.258462 s,887 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0020,17:41:09.239,5.258490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0021-0020,17:41:09.241,5.260462 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,05 4A,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),05 4A\r
-URB,0022,17:41:09.241,5.260493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0023-0022,17:41:09.242,5.261461 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0024,17:41:09.242,5.261486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0025-0024,17:41:09.244,5.263461 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0026,17:41:09.244,5.263495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0027-0026,17:41:09.245,5.264470 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0028,17:41:09.245,5.264534 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0029-0028,17:41:09.247,5.266457 s,1.923 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
-URB,0030,17:41:09.247,5.266509 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0031-0030,17:41:09.248,5.267458 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0032,17:41:09.248,5.267484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0033-0032,17:41:09.250,5.269465 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0034,17:41:09.250,5.269495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0035-0034,17:41:09.251,5.270461 s,966 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0036,17:41:09.251,5.270485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 01\r
-URB,0037-0036,17:41:09.253,5.272462 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0038,17:41:09.253,5.272486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0039-0038,17:41:09.255,5.274460 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0040,17:41:09.255,5.274484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0041-0040,17:41:09.257,5.276460 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0042,17:41:09.257,5.276493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0043-0042,17:41:09.258,5.277460 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0044,17:41:09.258,5.277485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0045-0044,17:41:09.260,5.279461 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0046,17:41:09.260,5.279486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0047-0046,17:41:09.262,5.281461 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0048,17:41:09.262,5.281488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0049-0048,17:41:09.264,5.283461 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0050,17:41:09.264,5.283491 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0051-0050,17:41:09.265,5.284460 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0052,17:41:09.265,5.284484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0053-0052,17:41:09.267,5.286461 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0054,17:41:09.267,5.286485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0055-0054,17:41:09.269,5.288460 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0056,17:41:09.269,5.288485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0057-0056,17:41:09.271,5.290460 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0058,17:41:09.271,5.290487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0059-0058,17:41:09.272,5.291462 s,976 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0060,17:41:09.272,5.291486 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0061-0060,17:41:09.274,5.293460 s,1.974 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0062,17:41:09.274,5.293485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0063-0062,17:41:09.276,5.295460 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0064,17:41:09.276,5.295487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0065-0064,17:41:09.278,5.297460 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0066,17:41:09.278,5.297488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0067-0066,17:41:09.279,5.298460 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0068,17:41:09.279,5.298485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0069-0068,17:41:09.281,5.300460 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0070,17:41:09.281,5.300484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0071-0070,17:41:09.283,5.302461 s,1.976 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0072,17:41:09.283,5.302485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0073-0072,17:41:09.285,5.304460 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0074,17:41:09.285,5.304502 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0075-0074,17:41:09.286,5.305459 s,957 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0076,17:41:09.286,5.305483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0077-0076,17:41:09.288,5.307460 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
-URB,0078,17:41:09.288,5.307486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0079-0078,17:41:09.289,5.308460 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0080,17:41:09.289,5.308484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0081-0080,17:41:09.291,5.310459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0082,17:41:09.291,5.310485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0D 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0D 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0083-0082,17:41:09.292,5.311460 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0084,17:41:09.292,5.311483 s,,Bulk or Interrupt Transfer,2 bytes data,BE BE,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,BE BE\r
-URB,0085-0084,17:41:09.294,5.313462 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0086,17:41:09.294,5.313486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0087-0086,17:41:09.296,5.315460 s,1.973 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0088,17:41:09.296,5.315487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0089-0088,17:41:09.298,5.317461 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0090,17:41:09.298,5.317488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 01 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 35 F0 ED 00 E0 01 00 5F A0 00 00 00 00 00 00\r
-URB,0091-0090,17:41:09.299,5.318460 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0092,17:41:09.299,5.318484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0093-0092,17:41:09.301,5.320459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0094,17:41:09.302,5.321032 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
-URB,0095-0094,17:41:09.302,5.321463 s,431 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0096,17:41:09.302,5.321490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0097-0096,17:41:09.304,5.323462 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 01\r
-URB,0098,17:41:09.304,5.323500 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0D 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0D 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0099-0098,17:41:09.305,5.324460 s,960 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0100,17:41:09.305,5.324491 s,,Bulk or Interrupt Transfer,2 bytes data,70 47,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,70 47\r
-URB,0101-0100,17:41:09.307,5.326459 s,1.968 ms,Bulk or Interrupt Transfer,2 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0102,17:41:09.307,5.326489 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0103-0102,17:41:09.309,5.328461 s,1.972 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0104,17:41:09.309,5.328488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0105-0104,17:41:09.311,5.330458 s,1.971 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0106,17:41:09.311,5.330495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 41 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0107-0106,17:41:09.312,5.331460 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0108,17:41:09.312,5.331487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0109-0108,17:41:09.314,5.333460 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0110,17:41:09.314,5.333511 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0111-0110,17:41:09.315,5.334459 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0112,17:41:09.315,5.334485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0113-0112,17:41:09.317,5.336460 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
-URB,0114,17:41:09.317,5.336490 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0115-0114,17:41:09.318,5.337458 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0116,17:41:09.318,5.337484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0117-0116,17:41:09.320,5.339459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0118,17:41:09.320,5.339487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0119-0118,17:41:09.321,5.340459 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0120,17:41:09.321,5.340484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 01\r
-URB,0121-0120,17:41:09.323,5.342460 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0122,17:41:09.323,5.342484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0123-0122,17:41:09.325,5.344459 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0124,17:41:09.325,5.344483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0125-0124,17:41:09.327,5.346460 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0126,17:41:09.327,5.346487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0127-0126,17:41:09.328,5.347459 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0128,17:41:09.328,5.347483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0129-0128,17:41:09.330,5.349459 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0130,17:41:09.330,5.349484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0131-0130,17:41:09.332,5.351459 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0132,17:41:09.332,5.351482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0133-0132,17:41:09.334,5.353460 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0134,17:41:09.334,5.353486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0135-0134,17:41:09.335,5.354459 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0136,17:41:09.335,5.354484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0137-0136,17:41:09.337,5.356459 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0138,17:41:09.337,5.356487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0139-0138,17:41:09.339,5.358460 s,1.972 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0140,17:41:09.339,5.358485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0141-0140,17:41:09.341,5.360459 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0142,17:41:09.341,5.360486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0143-0142,17:41:09.342,5.361458 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0144,17:41:09.342,5.361483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0145-0144,17:41:09.344,5.363461 s,1.979 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0146,17:41:09.344,5.363486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0147-0146,17:41:09.346,5.365459 s,1.973 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0148,17:41:09.346,5.365483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0149-0148,17:41:09.348,5.367459 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0150,17:41:09.348,5.367485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0151-0150,17:41:09.349,5.368459 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0152,17:41:09.349,5.368483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
-URB,0153-0152,17:41:09.351,5.370458 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0154,17:41:09.351,5.370483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0155-0154,17:41:09.353,5.372460 s,1.976 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0156,17:41:09.353,5.372483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0157-0156,17:41:09.355,5.374458 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0158,17:41:09.355,5.374493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3A 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0159-0158,17:41:09.356,5.375459 s,966 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0160,17:41:09.356,5.375486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0161-0160,17:41:09.361,5.380459 s,4.973 ms,Bulk or Interrupt Transfer,64 bytes data,80 00 00 01 00 00 00 20...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 00 00 00 20 08 ED 00 E0 80 FF FF 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 19 00 20 6B 0E 00 20\r
-URB,0162,17:41:09.361,5.380468 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0163-0162,17:41:09.363,5.382453 s,1.984 ms,Bulk or Interrupt Transfer,24 bytes data,40 11 00 20 00 00 00 01...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),40 11 00 20 00 00 00 01 A0 19 00 20 00 00 00 00 00 00 00 00 01 00 00 00\r
-URB,0164,17:41:09.363,5.382485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
-URB,0165-0164,17:41:09.364,5.383456 s,970 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0166,17:41:09.364,5.383480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0167-0166,17:41:09.366,5.385458 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
-URB,0168,17:41:09.366,5.385484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0169-0168,17:41:09.367,5.386458 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0170,17:41:09.367,5.386482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0171-0170,17:41:09.369,5.388460 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0172,17:41:09.369,5.388623 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 04 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 04 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
-URB,0173-0172,17:41:09.370,5.389462 s,839 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0174,17:41:09.370,5.389487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0175-0174,17:41:09.372,5.391459 s,1.972 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 00\r
-URB,0176,17:41:09.372,5.391485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0177-0176,17:41:09.373,5.392459 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
-URB,0178,17:41:09.373,5.392482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0179-0178,17:41:09.375,5.394458 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-URB,0180,17:41:09.386,5.405429 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 E4 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,,F2 07 E4 19 00 20 04 00 00 00 00 00 00 00 00 00\r
-URB,0181-0180,17:41:09.387,5.406464 s,1.035 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,Success (Success)\r
-URB,0182,17:41:09.387,5.406495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0183-0182,17:41:09.389,5.408458 s,1.963 ms,Bulk or Interrupt Transfer,4 bytes data,67 14 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),67 14 00 20\r
-URB,0184,17:41:09.389,5.408487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
-URB,0185-0184,17:41:09.390,5.409458 s,971 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,Success (Success)\r
-URB,0186,17:41:09.390,5.409483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
-URB,0187-0186,17:41:09.392,5.411458 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
-\r
-This report was generated by USBlyzer http://www.usblyzer.com/\r
--- /dev/null
+#ifndef STLINK_HW_H_INCLUDED
+# define STLINK_HW_H_INCLUDED
+
+// STLINK_DEBUG_RESETSYS, etc:
+#define STLINK_OK 0x80
+#define STLINK_FALSE 0x81
+#define STLINK_CORE_RUNNING 0x80
+#define STLINK_CORE_HALTED 0x81
+#define STLINK_CORE_STAT_UNKNOWN -1
+
+#define STLINK_GET_VERSION 0xf1
+#define STLINK_GET_CURRENT_MODE 0xf5
+
+#define STLINK_DEBUG_COMMAND 0xF2
+#define STLINK_DFU_COMMAND 0xF3
+#define STLINK_DFU_EXIT 0x07
+
+// STLINK_GET_CURRENT_MODE
+#define STLINK_DEV_DFU_MODE 0x00
+#define STLINK_DEV_MASS_MODE 0x01
+#define STLINK_DEV_DEBUG_MODE 0x02
+#define STLINK_DEV_UNKNOWN_MODE -1
+
+// jtag mode cmds
+#define STLINK_DEBUG_ENTER 0x20
+#define STLINK_DEBUG_EXIT 0x21
+#define STLINK_DEBUG_READCOREID 0x22
+#define STLINK_DEBUG_GETSTATUS 0x01
+#define STLINK_DEBUG_FORCEDEBUG 0x02
+#define STLINK_DEBUG_RESETSYS 0x03
+#define STLINK_DEBUG_READALLREGS 0x04
+#define STLINK_DEBUG_READREG 0x05
+#define STLINK_DEBUG_WRITEREG 0x06
+#define STLINK_DEBUG_READMEM_32BIT 0x07
+#define STLINK_DEBUG_WRITEMEM_32BIT 0x08
+#define STLINK_DEBUG_RUNCORE 0x09
+#define STLINK_DEBUG_STEPCORE 0x0a
+#define STLINK_DEBUG_SETFP 0x0b
+#define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
+#define STLINK_DEBUG_CLEARFP 0x0e
+#define STLINK_DEBUG_WRITEDEBUGREG 0x0f
+#define STLINK_DEBUG_ENTER_SWD 0xa3
+#define STLINK_DEBUG_ENTER_JTAG 0x00
+
+#endif /* STLINK_HW_H_INCLUDED */
--- /dev/null
+USBlyzer Report\r
+\r
+Capture List\r
+\r
+Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
+START,0001,17:45:39.429,,,,,,,,,,,,\r
+URB,0002,17:45:39.503,73.849 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0003-0002,17:45:39.505,75.843 ms,1.995 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0004,17:45:39.505,75.897 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0005-0004,17:45:39.507,77.812 ms,1.916 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0006,17:45:39.707,277.851 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0007-0006,17:45:39.709,279.821 ms,1.969 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0008,17:45:39.709,279.860 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0009-0008,17:45:39.711,281.806 ms,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0010,17:45:39.911,481.876 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0011-0010,17:45:39.913,483.827 ms,1.952 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0012,17:45:39.913,483.872 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0013-0012,17:45:39.915,485.806 ms,1.934 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0014,17:45:40.115,685.865 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0015-0014,17:45:40.116,687.797 ms,1.932 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0016,17:45:40.117,687.841 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0017-0016,17:45:40.118,689.796 ms,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0018,17:45:40.319,889.869 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0019-0018,17:45:40.320,891.792 ms,1.922 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0020,17:45:40.321,891.830 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0021-0020,17:45:40.321,892.814 ms,984 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0022,17:45:40.522,1.092884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0023-0022,17:45:40.523,1.094793 s,1.909 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0024,17:45:40.524,1.094839 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0025-0024,17:45:40.525,1.096788 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0026,17:45:40.725,1.295894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0027-0026,17:45:40.726,1.297784 s,1.891 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0028,17:45:40.726,1.297822 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0029-0028,17:45:40.728,1.299784 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0030,17:45:40.928,1.498899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0031-0030,17:45:40.929,1.500780 s,1.881 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0032,17:45:40.929,1.500814 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0033-0032,17:45:40.931,1.502781 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0034,17:45:41.131,1.701903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0035-0034,17:45:41.132,1.703782 s,1.879 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0036,17:45:41.132,1.703816 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0037-0036,17:45:41.134,1.705777 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0038,17:45:41.334,1.904910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0039-0038,17:45:41.335,1.906771 s,1.862 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0040,17:45:41.335,1.906805 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0041-0040,17:45:41.337,1.908771 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0042,17:45:41.537,2.107928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0043-0042,17:45:41.538,2.109777 s,1.849 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0044,17:45:41.538,2.109811 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0045-0044,17:45:41.540,2.111768 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0046,17:45:41.540,2.111800 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00\r
+URB,0047-0046,17:45:41.541,2.112767 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0048,17:45:41.541,2.112791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0049-0048,17:45:41.543,2.114766 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0050,17:45:41.543,2.114793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0051-0050,17:45:41.544,2.115767 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0052,17:45:41.544,2.115790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0053-0052,17:45:41.546,2.117768 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 01\r
+URB,0054,17:45:41.546,2.117799 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0055-0054,17:45:41.547,2.118768 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0056,17:45:41.547,2.118793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0057-0056,17:45:41.549,2.120767 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 00\r
+URB,0058,17:45:41.549,2.120798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 41 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0059-0058,17:45:41.550,2.121767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0060,17:45:41.550,2.121792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0061-0060,17:45:41.552,2.123768 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0062,17:45:41.552,2.123798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0063-0062,17:45:41.553,2.124767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0064,17:45:41.553,2.124791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0065-0064,17:45:41.555,2.126767 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
+URB,0066,17:45:41.555,2.126794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0067-0066,17:45:41.556,2.127767 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0068,17:45:41.556,2.127791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0069-0068,17:45:41.558,2.129767 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0070,17:45:41.558,2.129794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0071-0070,17:45:41.559,2.130767 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0072,17:45:41.559,2.130791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 01\r
+URB,0073-0072,17:45:41.561,2.132768 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0074,17:45:41.561,2.132793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0075-0074,17:45:41.563,2.134767 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0076,17:45:41.563,2.134790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0077-0076,17:45:41.565,2.136767 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0078,17:45:41.565,2.136798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0079-0078,17:45:41.566,2.137767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0080,17:45:41.566,2.137791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
+URB,0081-0080,17:45:41.568,2.139766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0082,17:45:41.568,2.139792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0083-0082,17:45:41.570,2.141767 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0084,17:45:41.570,2.141792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0085-0084,17:45:41.572,2.143769 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0086,17:45:41.572,2.143800 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0087-0086,17:45:41.573,2.144767 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0088,17:45:41.573,2.144791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
+URB,0089-0088,17:45:41.575,2.146766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0090,17:45:41.575,2.146791 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0091-0090,17:45:41.577,2.148766 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0092,17:45:41.577,2.148790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0093-0092,17:45:41.579,2.150766 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0094,17:45:41.579,2.150793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0095-0094,17:45:41.580,2.151767 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0096,17:45:41.580,2.151790 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
+URB,0097-0096,17:45:41.582,2.153766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0098,17:45:41.582,2.153790 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0099-0098,17:45:41.584,2.155769 s,1.979 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0100,17:45:41.584,2.155793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0101-0100,17:45:41.586,2.157767 s,1.974 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0102,17:45:41.586,2.157797 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0103-0102,17:45:41.587,2.158767 s,970 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0104,17:45:41.587,2.158791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00\r
+URB,0105-0104,17:45:41.589,2.160766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0106,17:45:41.589,2.160792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0107-0106,17:45:41.591,2.162766 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0108,17:45:41.591,2.162791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0109-0108,17:45:41.593,2.164767 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0110,17:45:41.593,2.164801 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3A 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0111-0110,17:45:41.594,2.165766 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0112,17:45:41.594,2.165790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0113-0112,17:45:41.599,2.170766 s,4.976 ms,Bulk or Interrupt Transfer,64 bytes data,80 00 00 01 04 00 00 00...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 04 00 00 00 00 00 00 00 3F 00 00 00 06 00 00 00 C8 14 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 19 00 20 6B 01 00 20\r
+URB,0114,17:45:41.599,2.170777 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0115-0114,17:45:41.601,2.172761 s,1.984 ms,Bulk or Interrupt Transfer,24 bytes data,A8 0A 00 20 00 00 00 21...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),A8 0A 00 20 00 00 00 21 88 19 00 20 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0116,17:45:41.601,2.172796 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C A8 0A 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 0C A8 0A 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0117-0116,17:45:41.602,2.173763 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0118,17:45:41.602,2.173789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0119-0118,17:45:41.604,2.175766 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,01 D0,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),01 D0\r
+URB,0120,17:45:41.604,2.175792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0121-0120,17:45:41.605,2.176766 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0122,17:45:41.605,2.176794 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0123-0122,17:45:41.607,2.178767 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0124,17:45:41.608,2.178876 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 04 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 07 04 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0125-0124,17:45:41.608,2.179765 s,889 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0126,17:45:41.608,2.179791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0127-0126,17:45:41.610,2.181767 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 00\r
+URB,0128,17:45:41.610,2.181793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0129-0128,17:45:41.611,2.182766 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,0130,17:45:41.611,2.182789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0131-0130,17:45:41.613,2.184766 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0132,17:45:41.614,2.185390 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 94 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 94 19 00 20 04 00 00 00 00 00 00 00 00 00\r
+URB,0133-0132,17:45:41.614,2.185766 s,376 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,0134,17:45:41.614,2.185793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0135-0134,17:45:41.616,2.187766 s,1.972 ms,Bulk or Interrupt Transfer,4 bytes data,1D 0E 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),1D 0E 00 20\r
+URB,0136,17:45:41.616,2.187794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0137-0136,17:45:41.617,2.188767 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,0138,17:45:41.617,2.188791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0139-0138,17:45:41.619,2.190766 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0140,17:45:41.620,2.191087 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 9C 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 9C 19 00 20 04 00 00 00 00 00 00 00 00 00\r
+URB,0141-0140,17:45:41.620,2.191766 s,679 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,0142,17:45:41.620,2.191790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0143-0142,17:45:41.622,2.193765 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,83 0F 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),83 0F 00 20\r
+URB,0144,17:45:41.622,2.193791 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0145-0144,17:45:41.623,2.194768 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,0146,17:45:41.623,2.194792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0147-0146,17:45:41.625,2.196767 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0148,17:45:41.626,2.197059 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 E4 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 E4 19 00 20 04 00 00 00 00 00 00 00 00 00\r
+URB,0149-0148,17:45:41.626,2.197765 s,706 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,0150,17:45:41.626,2.197789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0151-0150,17:45:41.628,2.199766 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes data,67 14 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),67 14 00 20\r
+URB,0152,17:45:41.628,2.199792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0153-0152,17:45:41.629,2.200766 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,0154,17:45:41.629,2.200790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0155-0154,17:45:41.631,2.202765 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+\r
+This report was generated by USBlyzer http://www.usblyzer.com/\r
--- /dev/null
+USBlyzer Report\r
+\r
+Capture List\r
+\r
+Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
+START,0001,16:01:27.054,,,,,,,,,,,,\r
+Create,0002,16:05:07.963,220.908617 s,,Create,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA8002864690h,\r
+Create,0003-0002,16:05:07.963,220.908641 s,24 us,Create,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA8002864690h,Success\r
+URB,0004,16:05:07.963,220.908764 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0005-0004,16:05:07.965,220.910795 s,2.032 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
+URB,0006,16:05:07.965,220.910876 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
+URB,0007-0006,16:05:07.968,220.912779 s,1.903 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),23 80 83 04 48 37\r
+URB,0008,16:05:07.968,220.912813 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0009-0008,16:05:07.968,220.913777 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
+URB,0010,16:05:07.968,220.913800 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
+URB,0011-0010,16:05:07.970,220.914777 s,978 us,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),00 01\r
+URB,0012,16:05:07.970,220.914803 s,,Bulk or Interrupt Transfer,16 bytes data,F3 08 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F3 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0013-0012,16:05:07.970,220.915778 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
+URB,0014,16:05:07.970,220.915799 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
+URB,0015-0014,16:05:07.973,220.917778 s,1.979 ms,Bulk or Interrupt Transfer,20 bytes data,40 00 FF FF 4A 82 34 06...,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),40 00 FF FF 4A 82 34 06 53 FF 68 06 48 82 57 51 07 38 12 87\r
+URB,0016,16:05:07.973,220.917815 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0017-0016,16:05:07.973,220.918777 s,963 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success)\r
+URB,0018,16:05:07.973,220.918799 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,\r
+URB,0019-0018,16:05:07.975,220.920778 s,1.978 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),23 80 83 04 48 37\r
+Cleanup,0020,16:07:29.920,362.863914 s,,Cleanup,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,\r
+Cleanup,0021-0020,16:07:29.920,362.863990 s,76 us,Cleanup,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,Success\r
+Close,0022,16:07:29.920,362.863994 s,,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,\r
+Close,0023-0022,16:07:29.920,362.863998 s,4 us,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,Success\r
+Create,0024,16:07:43.292,376.235500 s,,Create,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80067CE0D0h,\r
+Create,0025-0024,16:07:43.292,376.235525 s,24 us,Create,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80067CE0D0h,Success\r
+URB,0026,16:07:43.292,376.235653 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0027-0026,16:07:43.294,376.237673 s,2.020 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success)\r
+URB,0028,16:07:43.294,376.237720 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
+URB,0029-0028,16:07:43.296,376.239653 s,1.933 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),23 80 83 04 48 37\r
+URB,0030,16:07:43.296,376.239690 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0031-0030,16:07:43.297,376.240648 s,959 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success)\r
+URB,0032,16:07:43.297,376.240676 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
+URB,0033-0032,16:07:43.299,376.242648 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),00 01\r
+URB,0034,16:07:43.299,376.242680 s,,Bulk or Interrupt Transfer,16 bytes data,F3 07 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F3 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0035-0034,16:07:43.300,376.243647 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success)\r
+URB,0036,16:07:43.301,376.244139 s,,Bulk or Interrupt Transfer,16 bytes data,F2 30 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0037-0036,16:07:43.302,376.245654 s,1.515 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
+URB,0038,16:07:43.302,376.245686 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
+URB,0039-0038,16:07:43.304,376.247651 s,1.965 ms,Bulk or Interrupt Transfer,2 bytes data,04 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),04 00\r
+URB,0040,16:07:43.305,376.247993 s,,Bulk or Interrupt Transfer,16 bytes data,F2 32 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0041-0040,16:07:43.305,376.248654 s,661 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
+URB,0042,16:07:43.305,376.248685 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
+URB,0043-0042,16:07:43.307,376.250665 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,04 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),04 00\r
+URB,0044,16:07:43.307,376.250708 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0045-0044,16:07:43.309,376.251656 s,948 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
+URB,0046,16:07:43.309,376.251689 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
+URB,0047-0046,16:07:43.310,376.253650 s,1.961 ms,Bulk or Interrupt Transfer,2 bytes data,02 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),02 00\r
+URB,0048,16:07:43.310,376.253680 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 35 F0 ED 00 E0 00 00 5F A0 00 00 00 00 00 00\r
+URB,0049-0048,16:07:43.311,376.254647 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
+URB,0050,16:07:43.311,376.254672 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,\r
+URB,0051-0050,16:07:43.314,376.256648 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,08 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),08 00\r
+URB,0052,16:07:43.314,376.256675 s,,Bulk or Interrupt Transfer,16 bytes data,F2 21 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 21 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0053-0052,16:07:43.314,376.257649 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success)\r
+Cleanup,0054,16:07:43.314,376.257674 s,,Cleanup,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,\r
+Cleanup,0055-0054,16:07:43.314,376.257719 s,45 us,Cleanup,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,Success\r
+Close,0056,16:07:43.314,376.257722 s,,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,\r
+Close,0057-0056,16:07:43.314,376.257726 s,3 us,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,Success\r
+\r
+This report was generated by USBlyzer http://www.usblyzer.com/\r
--- /dev/null
+USBlyzer Report\r
+\r
+Capture List\r
+\r
+Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
+START,0001,17:43:38.035,,,,,,,,,,,,\r
+URB,0002,17:44:01.236,23.201589 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0003-0002,17:44:01.238,23.203514 s,1.924 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,0004,17:44:01.238,23.203558 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0005-0004,17:44:01.240,23.205498 s,1.940 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
+URB,0006,17:44:01.240,23.205532 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0007-0006,17:44:01.241,23.206491 s,960 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0008,17:44:01.241,23.206517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0009-0008,17:44:01.243,23.208494 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0010,17:44:01.243,23.208535 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0011-0010,17:44:01.244,23.209491 s,956 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0012,17:44:01.244,23.209515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0013-0012,17:44:01.246,23.211490 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
+URB,0014,17:44:01.246,23.211517 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0015-0014,17:44:01.247,23.212490 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0016,17:44:01.247,23.212515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0017-0016,17:44:01.249,23.214501 s,1.986 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0018,17:44:01.249,23.214544 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0019-0018,17:44:01.250,23.215493 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0020,17:44:01.250,23.215522 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 01\r
+URB,0021-0020,17:44:01.252,23.217580 s,2.058 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0022,17:44:01.252,23.217648 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0023-0022,17:44:01.254,23.219490 s,1.843 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0024,17:44:01.254,23.219518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0025-0024,17:44:01.256,23.221489 s,1.971 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0026,17:44:01.256,23.221519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0027-0026,17:44:01.257,23.222489 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0028,17:44:01.257,23.222512 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
+URB,0029-0028,17:44:01.259,23.224489 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0030,17:44:01.259,23.224513 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0031-0030,17:44:01.261,23.226489 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0032,17:44:01.261,23.226512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0033-0032,17:44:01.263,23.228488 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0034,17:44:01.263,23.228515 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0035-0034,17:44:01.264,23.229489 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0036,17:44:01.264,23.229513 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
+URB,0037-0036,17:44:01.266,23.231489 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0038,17:44:01.266,23.231523 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0039-0038,17:44:01.268,23.233488 s,1.965 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0040,17:44:01.268,23.233512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0041-0040,17:44:01.270,23.235488 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0042,17:44:01.270,23.235514 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0043-0042,17:44:01.271,23.236487 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0044,17:44:01.271,23.236510 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
+URB,0045-0044,17:44:01.272,23.237487 s,977 us,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0046,17:44:01.272,23.237512 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0047-0046,17:44:01.273,23.238488 s,976 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0048,17:44:01.273,23.238512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0049-0048,17:44:01.275,23.240489 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0050,17:44:01.275,23.240516 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0051-0050,17:44:01.276,23.241489 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0052,17:44:01.276,23.241511 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00\r
+URB,0053-0052,17:44:01.278,23.243487 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0054,17:44:01.278,23.243511 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0055-0054,17:44:01.279,23.244488 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0056,17:44:01.279,23.244513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0057-0056,17:44:01.281,23.246491 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0058,17:44:01.281,23.246535 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 01 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 35 F0 ED 00 E0 01 00 5F A0 00 00 00 00 00 00\r
+URB,0059-0058,17:44:01.282,23.247488 s,953 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0060,17:44:01.282,23.247512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0061-0060,17:44:01.284,23.249527 s,2.015 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0062,17:44:01.285,23.249896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0063-0062,17:44:01.285,23.250503 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0064,17:44:01.285,23.250533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0065-0064,17:44:01.287,23.252495 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0066,17:44:01.288,23.252884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0067-0066,17:44:01.288,23.253503 s,619 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0068,17:44:01.288,23.253528 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0069-0068,17:44:01.290,23.255495 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0070,17:44:01.291,23.255892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0071-0070,17:44:01.291,23.256498 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0072,17:44:01.291,23.256526 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0073-0072,17:44:01.293,23.258496 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0074,17:44:01.294,23.258894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0075-0074,17:44:01.294,23.259494 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0076,17:44:01.294,23.259523 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0077-0076,17:44:01.296,23.261494 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0078,17:44:01.297,23.261891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0079-0078,17:44:01.297,23.262495 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0080,17:44:01.297,23.262521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0081-0080,17:44:01.299,23.264495 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0082,17:44:01.300,23.264888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0083-0082,17:44:01.300,23.265494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0084,17:44:01.300,23.265520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0085-0084,17:44:01.302,23.267581 s,2.061 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0086,17:44:01.303,23.267906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0087-0086,17:44:01.303,23.268497 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0088,17:44:01.303,23.268527 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0089-0088,17:44:01.305,23.270494 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0090,17:44:01.306,23.270899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0091-0090,17:44:01.306,23.271494 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0092,17:44:01.306,23.271522 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0093-0092,17:44:01.308,23.273498 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0094,17:44:01.309,23.273886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0095-0094,17:44:01.309,23.274495 s,609 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0096,17:44:01.309,23.274520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0097-0096,17:44:01.311,23.276494 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0098,17:44:01.312,23.276884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0099-0098,17:44:01.312,23.277494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0100,17:44:01.312,23.277518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0101-0100,17:44:01.314,23.279495 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0102,17:44:01.315,23.279888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0103-0102,17:44:01.315,23.280494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0104,17:44:01.315,23.280517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0105-0104,17:44:01.317,23.282495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0106,17:44:01.318,23.282883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0107-0106,17:44:01.318,23.283494 s,611 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0108,17:44:01.318,23.283517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0109-0108,17:44:01.320,23.285493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0110,17:44:01.321,23.285893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0111-0110,17:44:01.321,23.286494 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0112,17:44:01.321,23.286520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0113-0112,17:44:01.323,23.288494 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0114,17:44:01.324,23.288887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0115-0114,17:44:01.324,23.289495 s,608 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0116,17:44:01.324,23.289519 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0117-0116,17:44:01.326,23.291494 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0118,17:44:01.327,23.291891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0119-0118,17:44:01.327,23.292493 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0120,17:44:01.327,23.292517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0121-0120,17:44:01.329,23.294494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0122,17:44:01.330,23.294883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0123-0122,17:44:01.330,23.295494 s,611 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0124,17:44:01.330,23.295517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0125-0124,17:44:01.332,23.297495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0126,17:44:01.333,23.297883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0127-0126,17:44:01.333,23.298494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0128,17:44:01.333,23.298517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0129-0128,17:44:01.335,23.300494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0130,17:44:01.336,23.300889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0131-0130,17:44:01.336,23.301494 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0132,17:44:01.336,23.301518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0133-0132,17:44:01.338,23.303494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0134,17:44:01.339,23.303884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0135-0134,17:44:01.339,23.304494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0136,17:44:01.339,23.304517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0137-0136,17:44:01.341,23.306493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0138,17:44:01.342,23.306884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0139-0138,17:44:01.342,23.307496 s,612 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0140,17:44:01.342,23.307520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0141-0140,17:44:01.344,23.309501 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0142,17:44:01.345,23.309893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0143-0142,17:44:01.345,23.310495 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0144,17:44:01.345,23.310521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0145-0144,17:44:01.347,23.312495 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0146,17:44:01.348,23.312884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0147-0146,17:44:01.348,23.313493 s,609 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0148,17:44:01.348,23.313517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0149-0148,17:44:01.350,23.315494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0150,17:44:01.351,23.315884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0151-0150,17:44:01.351,23.316494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0152,17:44:01.351,23.316517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0153-0152,17:44:01.353,23.318494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0154,17:44:01.354,23.318886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0155-0154,17:44:01.354,23.319494 s,608 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0156,17:44:01.354,23.319518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0157-0156,17:44:01.356,23.321494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0158,17:44:01.357,23.321890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0159-0158,17:44:01.357,23.322494 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0160,17:44:01.357,23.322517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0161-0160,17:44:01.359,23.324493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0162,17:44:01.360,23.324886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0163-0162,17:44:01.360,23.325493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0164,17:44:01.360,23.325517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0165-0164,17:44:01.362,23.327495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0166,17:44:01.363,23.327887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0167-0166,17:44:01.363,23.328494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0168,17:44:01.363,23.328517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0169-0168,17:44:01.365,23.330494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0170,17:44:01.366,23.330888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0171-0170,17:44:01.366,23.331493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0172,17:44:01.366,23.331518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0173-0172,17:44:01.368,23.333493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0174,17:44:01.369,23.333885 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0175-0174,17:44:01.369,23.334497 s,612 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0176,17:44:01.369,23.334520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0177-0176,17:44:01.371,23.336494 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0178,17:44:01.372,23.336887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0179-0178,17:44:01.372,23.337493 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0180,17:44:01.372,23.337516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0181-0180,17:44:01.374,23.339494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0182,17:44:01.375,23.339889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0183-0182,17:44:01.375,23.340492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0184,17:44:01.375,23.340517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0185-0184,17:44:01.377,23.342494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0186,17:44:01.378,23.342886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0187-0186,17:44:01.378,23.343493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0188,17:44:01.378,23.343516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0189-0188,17:44:01.380,23.345494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0190,17:44:01.381,23.345888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0191-0190,17:44:01.381,23.346493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0192,17:44:01.381,23.346516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0193-0192,17:44:01.383,23.348495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0194,17:44:01.384,23.348887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0195-0194,17:44:01.384,23.349493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0196,17:44:01.384,23.349516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0197-0196,17:44:01.386,23.351494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0198,17:44:01.387,23.351891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0199-0198,17:44:01.387,23.352493 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0200,17:44:01.387,23.352516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0201-0200,17:44:01.389,23.354493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0202,17:44:01.390,23.354887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0203-0202,17:44:01.390,23.355492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0204,17:44:01.390,23.355516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0205-0204,17:44:01.392,23.357492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0206,17:44:01.393,23.357886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0207-0206,17:44:01.393,23.358493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0208,17:44:01.393,23.358516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0209-0208,17:44:01.395,23.360494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0210,17:44:01.396,23.360885 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0211-0210,17:44:01.396,23.361493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0212,17:44:01.396,23.361516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0213-0212,17:44:01.398,23.363492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0214,17:44:01.399,23.363886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0215-0214,17:44:01.399,23.364493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0216,17:44:01.399,23.364516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0217-0216,17:44:01.401,23.366493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0218,17:44:01.402,23.366886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0219-0218,17:44:01.402,23.367492 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0220,17:44:01.402,23.367516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0221-0220,17:44:01.404,23.369494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0222,17:44:01.405,23.369888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0223-0222,17:44:01.405,23.370492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0224,17:44:01.405,23.370516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0225-0224,17:44:01.407,23.372492 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0226,17:44:01.408,23.372890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0227-0226,17:44:01.408,23.373492 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0228,17:44:01.408,23.373515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0229-0228,17:44:01.410,23.375494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0230,17:44:01.411,23.375887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0231-0230,17:44:01.411,23.376492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0232,17:44:01.411,23.376516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0233-0232,17:44:01.413,23.378492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0234,17:44:01.414,23.378886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0235-0234,17:44:01.414,23.379492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0236,17:44:01.414,23.379515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0237-0236,17:44:01.416,23.381492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0238,17:44:01.417,23.381895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0239-0238,17:44:01.417,23.382503 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0240,17:44:01.417,23.382534 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0241-0240,17:44:01.419,23.384495 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0242,17:44:01.420,23.384887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0243-0242,17:44:01.420,23.385492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0244,17:44:01.420,23.385516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0245-0244,17:44:01.422,23.387493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0246,17:44:01.423,23.387888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0247-0246,17:44:01.423,23.388492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0248,17:44:01.423,23.388516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0249-0248,17:44:01.425,23.390493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0250,17:44:01.426,23.390889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0251-0250,17:44:01.426,23.391492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0252,17:44:01.426,23.391516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0253-0252,17:44:01.428,23.393492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0254,17:44:01.429,23.393887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0255-0254,17:44:01.429,23.394492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0256,17:44:01.429,23.394516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0257-0256,17:44:01.431,23.396491 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0258,17:44:01.432,23.396887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0259-0258,17:44:01.432,23.397492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0260,17:44:01.432,23.397515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0261-0260,17:44:01.434,23.399492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0262,17:44:01.435,23.399888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0263-0262,17:44:01.435,23.400492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0264,17:44:01.435,23.400515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0265-0264,17:44:01.437,23.402492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0266,17:44:01.438,23.402893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0267-0266,17:44:01.438,23.403492 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0268,17:44:01.438,23.403517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0269-0268,17:44:01.440,23.405492 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0270,17:44:01.441,23.405888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0271-0270,17:44:01.441,23.406492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0272,17:44:01.441,23.406515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0273-0272,17:44:01.443,23.408491 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0274,17:44:01.444,23.408912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0275-0274,17:44:01.444,23.409490 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0276,17:44:01.444,23.409520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0277-0276,17:44:01.446,23.411489 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0278,17:44:01.447,23.411894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0279-0278,17:44:01.447,23.412492 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0280,17:44:01.447,23.412516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0281-0280,17:44:01.449,23.414492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0282,17:44:01.450,23.414888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0283-0282,17:44:01.450,23.415491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0284,17:44:01.450,23.415515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0285-0284,17:44:01.452,23.417492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0286,17:44:01.453,23.417888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0287-0286,17:44:01.453,23.418491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0288,17:44:01.453,23.418514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0289-0288,17:44:01.455,23.420492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0290,17:44:01.456,23.420890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0291-0290,17:44:01.456,23.421491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0292,17:44:01.456,23.421515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0293-0292,17:44:01.458,23.423496 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0294,17:44:01.459,23.423889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0295-0294,17:44:01.459,23.424492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0296,17:44:01.459,23.424515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0297-0296,17:44:01.461,23.426492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0298,17:44:01.462,23.426888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0299-0298,17:44:01.462,23.427491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0300,17:44:01.462,23.427515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0301-0300,17:44:01.464,23.429492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0302,17:44:01.465,23.429892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0303-0302,17:44:01.465,23.430491 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0304,17:44:01.465,23.430516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0305-0304,17:44:01.467,23.432491 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0306,17:44:01.468,23.432889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0307-0306,17:44:01.468,23.433491 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0308,17:44:01.468,23.433514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0309-0308,17:44:01.470,23.435492 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0310,17:44:01.471,23.435891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0311-0310,17:44:01.471,23.436491 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0312,17:44:01.471,23.436516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0313-0312,17:44:01.473,23.438493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0314,17:44:01.474,23.438890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0315-0314,17:44:01.474,23.439491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0316,17:44:01.474,23.439516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0317-0316,17:44:01.476,23.441492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0318,17:44:01.477,23.441894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0319-0318,17:44:01.477,23.442492 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0320,17:44:01.477,23.442516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0321-0320,17:44:01.479,23.444490 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0322,17:44:01.480,23.444892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0323-0322,17:44:01.480,23.445491 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0324,17:44:01.480,23.445514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0325-0324,17:44:01.482,23.447492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0326,17:44:01.483,23.447889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0327-0326,17:44:01.483,23.448490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0328,17:44:01.483,23.448514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0329-0328,17:44:01.485,23.450491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0330,17:44:01.486,23.450892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0331-0330,17:44:01.486,23.451490 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0332,17:44:01.486,23.451514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0333-0332,17:44:01.488,23.453491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0334,17:44:01.489,23.453892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0335-0334,17:44:01.489,23.454492 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0336,17:44:01.489,23.454516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0337-0336,17:44:01.491,23.456490 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0338,17:44:01.492,23.456889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0339-0338,17:44:01.492,23.457494 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0340,17:44:01.492,23.457517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0341-0340,17:44:01.494,23.459491 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0342,17:44:01.495,23.459889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0343-0342,17:44:01.495,23.460490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0344,17:44:01.495,23.460513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0345-0344,17:44:01.497,23.462490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0346,17:44:01.498,23.462889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0347-0346,17:44:01.498,23.463490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0348,17:44:01.498,23.463514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0349-0348,17:44:01.500,23.465491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0350,17:44:01.501,23.465890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0351-0350,17:44:01.501,23.466491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0352,17:44:01.501,23.466514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0353-0352,17:44:01.503,23.468491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0354,17:44:01.504,23.468891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0355-0354,17:44:01.504,23.469490 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0356,17:44:01.504,23.469513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0357-0356,17:44:01.506,23.471493 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0358,17:44:01.507,23.471897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0359-0358,17:44:01.507,23.472491 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0360,17:44:01.507,23.472516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0361-0360,17:44:01.509,23.474490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0362,17:44:01.510,23.474890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0363-0362,17:44:01.510,23.475490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0364,17:44:01.510,23.475514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0365-0364,17:44:01.512,23.477491 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0366,17:44:01.513,23.477891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0367-0366,17:44:01.513,23.478490 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0368,17:44:01.513,23.478514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0369-0368,17:44:01.515,23.480491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0370,17:44:01.516,23.480890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0371-0370,17:44:01.516,23.481490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0372,17:44:01.516,23.481514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0373-0372,17:44:01.518,23.483491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0374,17:44:01.519,23.483891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0375-0374,17:44:01.519,23.484490 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0376,17:44:01.519,23.484515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0377-0376,17:44:01.521,23.486490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0378,17:44:01.522,23.486890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0379-0378,17:44:01.522,23.487490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0380,17:44:01.522,23.487514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0381-0380,17:44:01.524,23.489490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0382,17:44:01.525,23.489894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0383-0382,17:44:01.525,23.490491 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0384,17:44:01.525,23.490515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0385-0384,17:44:01.527,23.492490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0386,17:44:01.528,23.492891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0387-0386,17:44:01.528,23.493489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0388,17:44:01.528,23.493513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0389-0388,17:44:01.530,23.495490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0390,17:44:01.531,23.495891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0391-0390,17:44:01.531,23.496489 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0392,17:44:01.531,23.496513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0393-0392,17:44:01.533,23.498490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0394,17:44:01.534,23.498891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0395-0394,17:44:01.534,23.499489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0396,17:44:01.534,23.499513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0397-0396,17:44:01.536,23.501506 s,1.992 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0398,17:44:01.537,23.501906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0399-0398,17:44:01.537,23.502503 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0400,17:44:01.537,23.502536 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0401-0400,17:44:01.539,23.504496 s,1.960 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0402,17:44:01.540,23.504897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0403-0402,17:44:01.540,23.505490 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0404,17:44:01.540,23.505514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0405-0404,17:44:01.542,23.507490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0406,17:44:01.543,23.507891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0407-0406,17:44:01.543,23.508489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0408,17:44:01.543,23.508513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0409-0408,17:44:01.545,23.510491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0410,17:44:01.546,23.510917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0411-0410,17:44:01.546,23.511487 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0412,17:44:01.546,23.511515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0413-0412,17:44:01.548,23.513484 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0414,17:44:01.549,23.513914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0415-0414,17:44:01.549,23.514487 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0416,17:44:01.549,23.514515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0417-0416,17:44:01.551,23.516490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0418,17:44:01.552,23.516893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0419-0418,17:44:01.552,23.517489 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0420,17:44:01.552,23.517513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0421-0420,17:44:01.554,23.519493 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0422,17:44:01.555,23.519892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0423-0422,17:44:01.555,23.520491 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0424,17:44:01.555,23.520514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0425-0424,17:44:01.557,23.522490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0426,17:44:01.558,23.522894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0427-0426,17:44:01.558,23.523489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0428,17:44:01.558,23.523513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0429-0428,17:44:01.560,23.525489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0430,17:44:01.561,23.525892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0431-0430,17:44:01.561,23.526489 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0432,17:44:01.561,23.526513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0433-0432,17:44:01.563,23.528490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0434,17:44:01.564,23.528894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0435-0434,17:44:01.564,23.529489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0436,17:44:01.564,23.529514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0437-0436,17:44:01.566,23.531489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0438,17:44:01.567,23.531899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0439-0438,17:44:01.567,23.532489 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0440,17:44:01.567,23.532514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0441-0440,17:44:01.569,23.534489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0442,17:44:01.570,23.534893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0443-0442,17:44:01.570,23.535490 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0444,17:44:01.570,23.535513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0445-0444,17:44:01.572,23.537489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0446,17:44:01.573,23.537899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0447-0446,17:44:01.573,23.538489 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0448,17:44:01.573,23.538513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0449-0448,17:44:01.575,23.540489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0450,17:44:01.576,23.540893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0451-0450,17:44:01.576,23.541488 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0452,17:44:01.576,23.541511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0453-0452,17:44:01.578,23.543489 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0454,17:44:01.579,23.543893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0455-0454,17:44:01.579,23.544489 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0456,17:44:01.579,23.544513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0457-0456,17:44:01.581,23.546491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0458,17:44:01.582,23.546895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0459-0458,17:44:01.582,23.547488 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0460,17:44:01.582,23.547512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0461-0460,17:44:01.584,23.549489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0462,17:44:01.585,23.549896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0463-0462,17:44:01.585,23.550490 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0464,17:44:01.585,23.550514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0465-0464,17:44:01.587,23.552489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0466,17:44:01.588,23.552894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0467-0466,17:44:01.588,23.553491 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0468,17:44:01.588,23.553515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0469-0468,17:44:01.590,23.555488 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0470,17:44:01.591,23.555918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8007DE2010h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0471-0470,17:44:01.591,23.556484 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8007DE2010h,Success (Success)\r
+URB,0472,17:44:01.591,23.556512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0473-0472,17:44:01.593,23.558529 s,2.017 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0474,17:44:01.594,23.558897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0475-0474,17:44:01.594,23.559500 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0476,17:44:01.594,23.559530 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0477-0476,17:44:01.596,23.561491 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0478,17:44:01.597,23.561907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0479-0478,17:44:01.597,23.562488 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0480,17:44:01.597,23.562513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0481-0480,17:44:01.599,23.564489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0482,17:44:01.600,23.564895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0483-0482,17:44:01.600,23.565492 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0484,17:44:01.600,23.565517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0485-0484,17:44:01.602,23.567488 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0486,17:44:01.603,23.567894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0487-0486,17:44:01.603,23.568488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0488,17:44:01.603,23.568512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0489-0488,17:44:01.605,23.570493 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0490,17:44:01.606,23.570895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0491-0490,17:44:01.606,23.571489 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0492,17:44:01.606,23.571514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0493-0492,17:44:01.608,23.573489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0494,17:44:01.609,23.573900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0495-0494,17:44:01.609,23.574489 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0496,17:44:01.609,23.574513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0497-0496,17:44:01.611,23.576489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0498,17:44:01.612,23.576894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0499-0498,17:44:01.612,23.577488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0500,17:44:01.612,23.577511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0501-0500,17:44:01.614,23.579490 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0502,17:44:01.615,23.579894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0503-0502,17:44:01.615,23.580489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0504,17:44:01.615,23.580512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0505-0504,17:44:01.617,23.582489 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0506,17:44:01.618,23.582894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0507-0506,17:44:01.618,23.583489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0508,17:44:01.618,23.583512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0509-0508,17:44:01.620,23.585489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0510,17:44:01.621,23.585894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0511-0510,17:44:01.621,23.586488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0512,17:44:01.621,23.586511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0513-0512,17:44:01.623,23.588488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0514,17:44:01.624,23.588898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0515-0514,17:44:01.624,23.589488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0516,17:44:01.624,23.589512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0517-0516,17:44:01.626,23.591487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0518,17:44:01.627,23.591900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0519-0518,17:44:01.627,23.592489 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0520,17:44:01.627,23.592513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0521-0520,17:44:01.629,23.594488 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0522,17:44:01.630,23.594894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0523-0522,17:44:01.630,23.595488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0524,17:44:01.630,23.595511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0525-0524,17:44:01.632,23.597487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0526,17:44:01.633,23.597894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0527-0526,17:44:01.633,23.598488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0528,17:44:01.633,23.598512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0529-0528,17:44:01.635,23.600490 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0530,17:44:01.636,23.600905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0531-0530,17:44:01.636,23.601502 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0532,17:44:01.636,23.601530 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0533-0532,17:44:01.638,23.603487 s,1.957 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0534,17:44:01.639,23.603897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0535-0534,17:44:01.639,23.604488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0536,17:44:01.639,23.604512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0537-0536,17:44:01.641,23.606489 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0538,17:44:01.642,23.606897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0539-0538,17:44:01.642,23.607488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0540,17:44:01.642,23.607512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0541-0540,17:44:01.644,23.609487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0542,17:44:01.645,23.609899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0543-0542,17:44:01.645,23.610488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0544,17:44:01.645,23.610513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0545-0544,17:44:01.647,23.612487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0546,17:44:01.648,23.612896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0547-0546,17:44:01.648,23.613490 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0548,17:44:01.648,23.613514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0549-0548,17:44:01.650,23.615488 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0550,17:44:01.651,23.615895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0551-0550,17:44:01.651,23.616488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0552,17:44:01.651,23.616511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0553-0552,17:44:01.653,23.618488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0554,17:44:01.654,23.618896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0555-0554,17:44:01.654,23.619487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0556,17:44:01.654,23.619511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0557-0556,17:44:01.656,23.621487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0558,17:44:01.657,23.621901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0559-0558,17:44:01.657,23.622487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0560,17:44:01.657,23.622511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0561-0560,17:44:01.659,23.624488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0562,17:44:01.660,23.624895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0563-0562,17:44:01.660,23.625488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0564,17:44:01.660,23.625511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0565-0564,17:44:01.662,23.627489 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0566,17:44:01.663,23.627896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0567-0566,17:44:01.663,23.628487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0568,17:44:01.663,23.628510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0569-0568,17:44:01.665,23.630488 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0570,17:44:01.666,23.630898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0571-0570,17:44:01.666,23.631488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0572,17:44:01.666,23.631512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0573-0572,17:44:01.668,23.633487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0574,17:44:01.669,23.633896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0575-0574,17:44:01.669,23.634487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0576,17:44:01.669,23.634511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0577-0576,17:44:01.671,23.636487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0578,17:44:01.672,23.636896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0579-0578,17:44:01.672,23.637489 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0580,17:44:01.672,23.637512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0581-0580,17:44:01.674,23.639488 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0582,17:44:01.675,23.639897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0583-0582,17:44:01.675,23.640488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0584,17:44:01.675,23.640511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0585-0584,17:44:01.677,23.642487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0586,17:44:01.678,23.642896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0587-0586,17:44:01.678,23.643487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0588,17:44:01.678,23.643510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0589-0588,17:44:01.680,23.645487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0590,17:44:01.681,23.645896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0591-0590,17:44:01.681,23.646487 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0592,17:44:01.681,23.646510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0593-0592,17:44:01.683,23.648487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0594,17:44:01.684,23.648899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0595-0594,17:44:01.684,23.649487 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0596,17:44:01.684,23.649511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0597-0596,17:44:01.686,23.651487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0598,17:44:01.687,23.651901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0599-0598,17:44:01.687,23.652487 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0600,17:44:01.687,23.652510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0601-0600,17:44:01.689,23.654489 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0602,17:44:01.690,23.654899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0603-0602,17:44:01.690,23.655490 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0604,17:44:01.690,23.655514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0605-0604,17:44:01.692,23.657487 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0606,17:44:01.693,23.657898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0607-0606,17:44:01.693,23.658488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0608,17:44:01.693,23.658511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0609-0608,17:44:01.695,23.660486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0610,17:44:01.696,23.660897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0611-0610,17:44:01.696,23.661486 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0612,17:44:01.696,23.661510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0613-0612,17:44:01.698,23.663487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0614,17:44:01.699,23.663899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0615-0614,17:44:01.699,23.664486 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0616,17:44:01.699,23.664511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0617-0616,17:44:01.701,23.666486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0618,17:44:01.702,23.666898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0619-0618,17:44:01.702,23.667486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0620,17:44:01.702,23.667510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0621-0620,17:44:01.704,23.669490 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0622,17:44:01.705,23.669901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0623-0622,17:44:01.705,23.670487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0624,17:44:01.705,23.670512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0625-0624,17:44:01.707,23.672487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0626,17:44:01.708,23.672898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0627-0626,17:44:01.708,23.673487 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0628,17:44:01.708,23.673510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0629-0628,17:44:01.710,23.675486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0630,17:44:01.711,23.675898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0631-0630,17:44:01.711,23.676487 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0632,17:44:01.711,23.676510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0633-0632,17:44:01.713,23.678487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0634,17:44:01.714,23.678898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0635-0634,17:44:01.714,23.679486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0636,17:44:01.714,23.679510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0637-0636,17:44:01.716,23.681486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0638,17:44:01.717,23.681904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0639-0638,17:44:01.717,23.682486 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0640,17:44:01.717,23.682510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0641-0640,17:44:01.719,23.684485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0642,17:44:01.720,23.684898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0643-0642,17:44:01.720,23.685486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0644,17:44:01.720,23.685510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0645-0644,17:44:01.722,23.687486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0646,17:44:01.723,23.687898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0647-0646,17:44:01.723,23.688486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0648,17:44:01.723,23.688510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0649-0648,17:44:01.725,23.690486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0650,17:44:01.726,23.690901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0651-0650,17:44:01.726,23.691486 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0652,17:44:01.726,23.691509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0653-0652,17:44:01.728,23.693486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0654,17:44:01.729,23.693898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0655-0654,17:44:01.729,23.694486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0656,17:44:01.729,23.694510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0657-0656,17:44:01.731,23.696486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0658,17:44:01.732,23.696899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0659-0658,17:44:01.732,23.697486 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0660,17:44:01.732,23.697509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0661-0660,17:44:01.734,23.699487 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0662,17:44:01.735,23.699900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0663-0662,17:44:01.735,23.700486 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0664,17:44:01.735,23.700512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0665-0664,17:44:01.737,23.702486 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0666,17:44:01.738,23.702899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0667-0666,17:44:01.738,23.703490 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0668,17:44:01.738,23.703514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0669-0668,17:44:01.740,23.705486 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0670,17:44:01.741,23.705899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0671-0670,17:44:01.741,23.706487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0672,17:44:01.741,23.706511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0673-0672,17:44:01.743,23.708486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0674,17:44:01.744,23.708904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0675-0674,17:44:01.744,23.709488 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0676,17:44:01.744,23.709515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0677-0676,17:44:01.746,23.711487 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0678,17:44:01.747,23.711906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0679-0678,17:44:01.747,23.712491 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0680,17:44:01.747,23.712520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0681-0680,17:44:01.749,23.714489 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0682,17:44:01.750,23.714913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0683-0682,17:44:01.750,23.715487 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0684,17:44:01.750,23.715516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0685-0684,17:44:01.752,23.717495 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0686,17:44:01.753,23.717908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0687-0686,17:44:01.753,23.718488 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0688,17:44:01.753,23.718516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0689-0688,17:44:01.755,23.720485 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0690,17:44:01.756,23.720912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0691-0690,17:44:01.756,23.721490 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0692,17:44:01.756,23.721516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0693-0692,17:44:01.758,23.723484 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0694,17:44:01.759,23.723901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0695-0694,17:44:01.759,23.724485 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0696,17:44:01.759,23.724508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0697-0696,17:44:01.761,23.726486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0698,17:44:01.762,23.726899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0699-0698,17:44:01.762,23.727485 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0700,17:44:01.762,23.727508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0701-0700,17:44:01.764,23.729487 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0702,17:44:01.765,23.729910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0703-0702,17:44:01.765,23.730486 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0704,17:44:01.765,23.730512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0705-0704,17:44:01.767,23.732485 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0706,17:44:01.768,23.732900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0707-0706,17:44:01.768,23.733485 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0708,17:44:01.768,23.733509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0709-0708,17:44:01.770,23.735486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0710,17:44:01.771,23.735900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0711-0710,17:44:01.771,23.736489 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0712,17:44:01.771,23.736512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0713-0712,17:44:01.773,23.738485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0714,17:44:01.774,23.738900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0715-0714,17:44:01.774,23.739485 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0716,17:44:01.774,23.739508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0717-0716,17:44:01.776,23.741485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0718,17:44:01.777,23.741907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0719-0718,17:44:01.777,23.742485 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0720,17:44:01.777,23.742509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0721-0720,17:44:01.779,23.744486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0722,17:44:01.780,23.744906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0723-0722,17:44:01.780,23.745486 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0724,17:44:01.780,23.745512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0725-0724,17:44:01.782,23.747486 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0726,17:44:01.783,23.747908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0727-0726,17:44:01.783,23.748485 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0728,17:44:01.783,23.748511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0729-0728,17:44:01.785,23.750485 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0730,17:44:01.786,23.750906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0731-0730,17:44:01.786,23.751486 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0732,17:44:01.786,23.751510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0733-0732,17:44:01.788,23.753485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0734,17:44:01.789,23.753901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0735-0734,17:44:01.789,23.754484 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0736,17:44:01.789,23.754507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0737-0736,17:44:01.791,23.756487 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0738,17:44:01.792,23.756901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0739-0738,17:44:01.792,23.757484 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0740,17:44:01.792,23.757508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0741-0740,17:44:01.794,23.759485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0742,17:44:01.795,23.759904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0743-0742,17:44:01.795,23.760485 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0744,17:44:01.795,23.760509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0745-0744,17:44:01.797,23.762486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0746,17:44:01.798,23.762904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0747-0746,17:44:01.798,23.763484 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0748,17:44:01.798,23.763508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0749-0748,17:44:01.800,23.765484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0750,17:44:01.801,23.765902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0751-0750,17:44:01.801,23.766529 s,627 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0752,17:44:01.801,23.766553 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0753-0752,17:44:01.803,23.768492 s,1.939 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0754,17:44:01.804,23.768914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0755-0754,17:44:01.804,23.769490 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0756,17:44:01.804,23.769519 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0757-0756,17:44:01.806,23.771485 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0758,17:44:01.807,23.771909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0759-0758,17:44:01.807,23.772484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0760,17:44:01.807,23.772508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0761-0760,17:44:01.809,23.774486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0762,17:44:01.810,23.774901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0763-0762,17:44:01.810,23.775487 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0764,17:44:01.810,23.775511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0765-0764,17:44:01.812,23.777486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0766,17:44:01.813,23.777906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0767-0766,17:44:01.813,23.778486 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0768,17:44:01.813,23.778511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0769-0768,17:44:01.815,23.780484 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0770,17:44:01.816,23.780907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0771-0770,17:44:01.816,23.781485 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0772,17:44:01.816,23.781508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0773-0772,17:44:01.818,23.783486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0774,17:44:01.819,23.783904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0775-0774,17:44:01.819,23.784486 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0776,17:44:01.819,23.784509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0777-0776,17:44:01.821,23.786485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0778,17:44:01.822,23.786902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0779-0778,17:44:01.822,23.787483 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0780,17:44:01.822,23.787507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0781-0780,17:44:01.824,23.789485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0782,17:44:01.825,23.789906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0783-0782,17:44:01.825,23.790484 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0784,17:44:01.825,23.790509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0785-0784,17:44:01.827,23.792485 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0786,17:44:01.828,23.792902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0787-0786,17:44:01.828,23.793484 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0788,17:44:01.828,23.793508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0789-0788,17:44:01.830,23.795484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0790,17:44:01.831,23.795902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0791-0790,17:44:01.831,23.796484 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0792,17:44:01.831,23.796508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0793-0792,17:44:01.833,23.798484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0794,17:44:01.834,23.798902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0795-0794,17:44:01.834,23.799485 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0796,17:44:01.834,23.799509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0797-0796,17:44:01.836,23.801485 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0798,17:44:01.837,23.801908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0799-0798,17:44:01.837,23.802484 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0800,17:44:01.837,23.802508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0801-0800,17:44:01.839,23.804483 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0802,17:44:01.840,23.804903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0803-0802,17:44:01.840,23.805484 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0804,17:44:01.840,23.805507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0805-0804,17:44:01.842,23.807488 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0806,17:44:01.843,23.807910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0807-0806,17:44:01.843,23.808486 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0808,17:44:01.843,23.808511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0809-0808,17:44:01.845,23.810485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0810,17:44:01.846,23.810909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0811-0810,17:44:01.846,23.811484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0812,17:44:01.846,23.811508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0813-0812,17:44:01.848,23.813484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0814,17:44:01.849,23.813904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0815-0814,17:44:01.849,23.814485 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0816,17:44:01.849,23.814508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0817-0816,17:44:01.851,23.816484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0818,17:44:01.852,23.816905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0819-0818,17:44:01.852,23.817483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0820,17:44:01.852,23.817508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0821-0820,17:44:01.854,23.819484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0822,17:44:01.855,23.819903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0823-0822,17:44:01.855,23.820483 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0824,17:44:01.855,23.820507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0825-0824,17:44:01.857,23.822484 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0826,17:44:01.858,23.822903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0827-0826,17:44:01.858,23.823483 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0828,17:44:01.858,23.823506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0829-0828,17:44:01.860,23.825487 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0830,17:44:01.861,23.825922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0831-0830,17:44:01.861,23.826480 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0832,17:44:01.861,23.826509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0833-0832,17:44:01.863,23.828476 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0834,17:44:01.864,23.828919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0835-0834,17:44:01.864,23.829481 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0836,17:44:01.864,23.829508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0837-0836,17:44:01.866,23.831484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0838,17:44:01.867,23.831911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0839-0838,17:44:01.867,23.832483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0840,17:44:01.867,23.832507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0841-0840,17:44:01.869,23.834484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0842,17:44:01.870,23.834905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0843-0842,17:44:01.870,23.835483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0844,17:44:01.870,23.835506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0845-0844,17:44:01.872,23.837484 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0846,17:44:01.873,23.837910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0847-0846,17:44:01.873,23.838484 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0848,17:44:01.873,23.838508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0849-0848,17:44:01.875,23.840485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0850,17:44:01.876,23.840907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0851-0850,17:44:01.876,23.841479 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0852,17:44:01.876,23.841506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0853-0852,17:44:01.878,23.843476 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0854,17:44:01.879,23.843916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0855-0854,17:44:01.879,23.844485 s,568 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0856,17:44:01.879,23.844511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0857-0856,17:44:01.881,23.846483 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0858,17:44:01.882,23.846906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0859-0858,17:44:01.882,23.847482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0860,17:44:01.882,23.847507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0861-0860,17:44:01.884,23.849485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0862,17:44:01.885,23.849911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0863-0862,17:44:01.885,23.850482 s,571 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0864,17:44:01.885,23.850508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0865-0864,17:44:01.887,23.852483 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0866,17:44:01.888,23.852905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0867-0866,17:44:01.888,23.853482 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0868,17:44:01.888,23.853507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0869-0868,17:44:01.890,23.855484 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0870,17:44:01.891,23.855908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0871-0870,17:44:01.891,23.856483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0872,17:44:01.891,23.856507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0873-0872,17:44:01.893,23.858485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0874,17:44:01.894,23.858905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0875-0874,17:44:01.894,23.859483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0876,17:44:01.894,23.859506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0877-0876,17:44:01.896,23.861483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0878,17:44:01.897,23.861910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0879-0878,17:44:01.897,23.862483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0880,17:44:01.897,23.862506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0881-0880,17:44:01.899,23.864482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0882,17:44:01.900,23.864904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0883-0882,17:44:01.900,23.865483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0884,17:44:01.900,23.865506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0885-0884,17:44:01.902,23.867483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0886,17:44:01.903,23.867905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0887-0886,17:44:01.903,23.868482 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0888,17:44:01.903,23.868506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0889-0888,17:44:01.905,23.870518 s,2.013 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0890,17:44:01.906,23.870911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0891-0890,17:44:01.906,23.871488 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0892,17:44:01.906,23.871517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0893-0892,17:44:01.908,23.873487 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0894,17:44:01.909,23.873914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0895-0894,17:44:01.909,23.874486 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0896,17:44:01.909,23.874513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0897-0896,17:44:01.911,23.876488 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0898,17:44:01.912,23.876909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0899-0898,17:44:01.912,23.877482 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0900,17:44:01.912,23.877506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0901-0900,17:44:01.914,23.879483 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0902,17:44:01.915,23.879906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0903-0902,17:44:01.915,23.880482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0904,17:44:01.915,23.880505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0905-0904,17:44:01.917,23.882483 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0906,17:44:01.918,23.882910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0907-0906,17:44:01.918,23.883483 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0908,17:44:01.918,23.883506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0909-0908,17:44:01.920,23.885483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0910,17:44:01.921,23.885906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0911-0910,17:44:01.921,23.886482 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0912,17:44:01.921,23.886505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0913-0912,17:44:01.923,23.888483 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0914,17:44:01.924,23.888907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0915-0914,17:44:01.924,23.889483 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0916,17:44:01.924,23.889508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0917-0916,17:44:01.926,23.891482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0918,17:44:01.927,23.891913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0919-0918,17:44:01.927,23.892482 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0920,17:44:01.927,23.892506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0921-0920,17:44:01.929,23.894483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0922,17:44:01.930,23.894906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0923-0922,17:44:01.930,23.895483 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0924,17:44:01.930,23.895507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0925-0924,17:44:01.932,23.897482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0926,17:44:01.933,23.897906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0927-0926,17:44:01.933,23.898482 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0928,17:44:01.933,23.898506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0929-0928,17:44:01.935,23.900482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0930,17:44:01.936,23.900906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0931-0930,17:44:01.936,23.901482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0932,17:44:01.936,23.901506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0933-0932,17:44:01.938,23.903482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0934,17:44:01.939,23.903906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0935-0934,17:44:01.939,23.904482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0936,17:44:01.939,23.904506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0937-0936,17:44:01.941,23.906483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0938,17:44:01.942,23.906906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0939-0938,17:44:01.942,23.907482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0940,17:44:01.942,23.907506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0941-0940,17:44:01.944,23.909481 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0942,17:44:01.945,23.909909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0943-0942,17:44:01.945,23.910513 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0944,17:44:01.945,23.910539 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0945-0944,17:44:01.947,23.912487 s,1.948 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0946,17:44:01.948,23.912912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0947-0946,17:44:01.948,23.913485 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0948,17:44:01.948,23.913512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0949-0948,17:44:01.950,23.915486 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0950,17:44:01.951,23.915911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0951-0950,17:44:01.951,23.916481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0952,17:44:01.951,23.916506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0953-0952,17:44:01.953,23.918507 s,2.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0954,17:44:01.954,23.918910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0955-0954,17:44:01.954,23.919487 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0956,17:44:01.954,23.919513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0957-0956,17:44:01.956,23.921482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0958,17:44:01.957,23.921915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0959-0958,17:44:01.957,23.922481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0960,17:44:01.957,23.922506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0961-0960,17:44:01.959,23.924482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0962,17:44:01.960,23.924910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0963-0962,17:44:01.960,23.925483 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0964,17:44:01.960,23.925509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0965-0964,17:44:01.961,23.926505 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0966,17:44:01.962,23.926908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0967-0966,17:44:01.962,23.927483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0968,17:44:01.962,23.927509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0969-0968,17:44:01.964,23.929482 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0970,17:44:01.965,23.929915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0971-0970,17:44:01.965,23.930482 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0972,17:44:01.965,23.930508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0973-0972,17:44:01.967,23.932481 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0974,17:44:01.968,23.932908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0975-0974,17:44:01.968,23.933481 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0976,17:44:01.968,23.933504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0977-0976,17:44:01.969,23.934505 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0978,17:44:01.970,23.934910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0979-0978,17:44:01.970,23.935488 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0980,17:44:01.970,23.935515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0981-0980,17:44:01.972,23.937484 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0982,17:44:01.973,23.937918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0983-0982,17:44:01.973,23.938482 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0984,17:44:01.973,23.938507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0985-0984,17:44:01.975,23.940482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0986,17:44:01.976,23.940910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0987-0986,17:44:01.976,23.941484 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0988,17:44:01.976,23.941508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0989-0988,17:44:01.977,23.942504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0990,17:44:01.978,23.942909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0991-0990,17:44:01.978,23.943484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0992,17:44:01.978,23.943509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0993-0992,17:44:01.980,23.945482 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0994,17:44:01.981,23.945910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0995-0994,17:44:01.981,23.946481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,0996,17:44:01.981,23.946505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0997-0996,17:44:01.983,23.948481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,0998,17:44:01.984,23.948909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0999-0998,17:44:01.984,23.949481 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1000,17:44:01.984,23.949505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1001-1000,17:44:01.985,23.950503 s,998 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1002,17:44:01.986,23.950914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1003-1002,17:44:01.986,23.951485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1004,17:44:01.986,23.951513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1005-1004,17:44:01.988,23.953482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1006,17:44:01.989,23.953911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1007-1006,17:44:01.989,23.954481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1008,17:44:01.989,23.954505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1009-1008,17:44:01.991,23.956480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1010,17:44:01.992,23.956908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1011-1010,17:44:01.992,23.957484 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1012,17:44:01.992,23.957508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1013-1012,17:44:01.993,23.958504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1014,17:44:01.994,23.958909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1015-1014,17:44:01.994,23.959485 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1016,17:44:01.994,23.959510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1017-1016,17:44:01.996,23.961481 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1018,17:44:01.997,23.961911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1019-1018,17:44:01.997,23.962481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1020,17:44:01.997,23.962505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1021-1020,17:44:01.999,23.964481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1022,17:44:02.000,23.964908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1023-1022,17:44:02.000,23.965481 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1024,17:44:02.000,23.965504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1025-1024,17:44:02.001,23.966505 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1026,17:44:02.002,23.966909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1027-1026,17:44:02.002,23.967484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1028,17:44:02.002,23.967509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1029-1028,17:44:02.004,23.969482 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1030,17:44:02.005,23.969919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1031-1030,17:44:02.005,23.970480 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1032,17:44:02.005,23.970505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1033-1032,17:44:02.007,23.972481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1034,17:44:02.008,23.972909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1035-1034,17:44:02.008,23.973483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1036,17:44:02.008,23.973507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1037-1036,17:44:02.009,23.974504 s,997 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1038,17:44:02.010,23.974911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1039-1038,17:44:02.010,23.975484 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1040,17:44:02.010,23.975511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1041-1040,17:44:02.012,23.977482 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1042,17:44:02.013,23.977912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1043-1042,17:44:02.013,23.978480 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1044,17:44:02.013,23.978504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1045-1044,17:44:02.015,23.980481 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1046,17:44:02.016,23.980914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1047-1046,17:44:02.016,23.981481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1048,17:44:02.016,23.981506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1049-1048,17:44:02.017,23.982505 s,1000 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1050,17:44:02.018,23.982911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1051-1050,17:44:02.018,23.983486 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1052,17:44:02.018,23.983513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1053-1052,17:44:02.020,23.985482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1054,17:44:02.021,23.985915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1055-1054,17:44:02.021,23.986480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1056,17:44:02.021,23.986505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1057-1056,17:44:02.023,23.988480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1058,17:44:02.024,23.988911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1059-1058,17:44:02.024,23.989483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1060,17:44:02.024,23.989508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1061-1060,17:44:02.025,23.990504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1062,17:44:02.026,23.990912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1063-1062,17:44:02.026,23.991487 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1064,17:44:02.026,23.991515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1065-1064,17:44:02.028,23.993482 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1066,17:44:02.029,23.993913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1067-1066,17:44:02.029,23.994480 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1068,17:44:02.029,23.994504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1069-1068,17:44:02.031,23.996480 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1070,17:44:02.032,23.996910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1071-1070,17:44:02.032,23.997480 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1072,17:44:02.032,23.997503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1073-1072,17:44:02.033,23.998504 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1074,17:44:02.034,23.998910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1075-1074,17:44:02.034,23.999484 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1076,17:44:02.034,23.999510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1077-1076,17:44:02.036,24.001489 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1078,17:44:02.037,24.001970 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1079-1078,17:44:02.037,24.002479 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success)\r
+URB,1080,17:44:02.037,24.002521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1081-1080,17:44:02.039,24.004477 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1082,17:44:02.040,24.004914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1083-1082,17:44:02.040,24.005485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1084,17:44:02.040,24.005510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1085-1084,17:44:02.041,24.006513 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1086,17:44:02.042,24.006912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1087-1086,17:44:02.042,24.007486 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1088,17:44:02.042,24.007513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1089-1088,17:44:02.044,24.009483 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1090,17:44:02.045,24.009923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1091-1090,17:44:02.045,24.010480 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1092,17:44:02.045,24.010506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1093-1092,17:44:02.047,24.012481 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1094,17:44:02.048,24.012915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1095-1094,17:44:02.048,24.013481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1096,17:44:02.048,24.013506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1097-1096,17:44:02.049,24.014511 s,1.005 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1098,17:44:02.050,24.014915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1099-1098,17:44:02.050,24.015483 s,568 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1100,17:44:02.050,24.015508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1101-1100,17:44:02.052,24.017482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1102,17:44:02.053,24.017913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1103-1102,17:44:02.053,24.018478 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1104,17:44:02.053,24.018502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1105-1104,17:44:02.055,24.020484 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1106,17:44:02.056,24.020913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1107-1106,17:44:02.056,24.021480 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1108,17:44:02.056,24.021504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1109-1108,17:44:02.057,24.022503 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1110,17:44:02.058,24.022912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1111-1110,17:44:02.058,24.023485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1112,17:44:02.058,24.023513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1113-1112,17:44:02.060,24.025485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1114,17:44:02.061,24.025922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1115-1114,17:44:02.061,24.026479 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1116,17:44:02.061,24.026505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1117-1116,17:44:02.063,24.028479 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1118,17:44:02.064,24.028913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1119-1118,17:44:02.064,24.029479 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1120,17:44:02.064,24.029503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1121-1120,17:44:02.065,24.030507 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1122,17:44:02.066,24.030913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1123-1122,17:44:02.066,24.031483 s,571 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1124,17:44:02.066,24.031508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1125-1124,17:44:02.068,24.033482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1126,17:44:02.069,24.033916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1127-1126,17:44:02.069,24.034480 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1128,17:44:02.069,24.034504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1129-1128,17:44:02.071,24.036483 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1130,17:44:02.072,24.036914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1131-1130,17:44:02.072,24.037479 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1132,17:44:02.072,24.037503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1133-1132,17:44:02.073,24.038504 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1134,17:44:02.074,24.038912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1135-1134,17:44:02.074,24.039481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1136,17:44:02.074,24.039508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1137-1136,17:44:02.076,24.041483 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1138,17:44:02.077,24.041921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1139-1138,17:44:02.077,24.042479 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1140,17:44:02.077,24.042505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1141-1140,17:44:02.079,24.044478 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1142,17:44:02.080,24.044913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1143-1142,17:44:02.080,24.045479 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1144,17:44:02.080,24.045504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1145-1144,17:44:02.081,24.046502 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1146,17:44:02.082,24.046913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1147-1146,17:44:02.082,24.047481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1148,17:44:02.082,24.047507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1149-1148,17:44:02.084,24.049479 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1150,17:44:02.085,24.049921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1151-1150,17:44:02.085,24.050478 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1152,17:44:02.085,24.050505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1153-1152,17:44:02.087,24.052479 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1154,17:44:02.088,24.052916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1155-1154,17:44:02.088,24.053479 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1156,17:44:02.088,24.053503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1157-1156,17:44:02.089,24.054503 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1158,17:44:02.090,24.054914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1159-1158,17:44:02.090,24.055484 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1160,17:44:02.090,24.055510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1161-1160,17:44:02.092,24.057479 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1162,17:44:02.093,24.057917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1163-1162,17:44:02.093,24.058478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1164,17:44:02.093,24.058502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1165-1164,17:44:02.095,24.060479 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1166,17:44:02.096,24.060915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1167-1166,17:44:02.096,24.061479 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1168,17:44:02.096,24.061504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1169-1168,17:44:02.097,24.062502 s,998 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1170,17:44:02.098,24.062913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1171-1170,17:44:02.098,24.063482 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1172,17:44:02.098,24.063508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1173-1172,17:44:02.100,24.065480 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1174,17:44:02.101,24.065915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1175-1174,17:44:02.101,24.066478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1176,17:44:02.101,24.066502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1177-1176,17:44:02.103,24.068479 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1178,17:44:02.104,24.068918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1179-1178,17:44:02.104,24.069479 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1180,17:44:02.104,24.069506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1181-1180,17:44:02.105,24.070506 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1182,17:44:02.106,24.070916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1183-1182,17:44:02.106,24.071486 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1184,17:44:02.106,24.071513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1185-1184,17:44:02.108,24.073479 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1186,17:44:02.109,24.073920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1187-1186,17:44:02.109,24.074478 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1188,17:44:02.109,24.074502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1189-1188,17:44:02.111,24.076478 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1190,17:44:02.112,24.076912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1191-1190,17:44:02.112,24.077478 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1192,17:44:02.112,24.077502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1193-1192,17:44:02.113,24.078502 s,1.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1194,17:44:02.114,24.078917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1195-1194,17:44:02.114,24.079482 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1196,17:44:02.114,24.079507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1197-1196,17:44:02.116,24.081480 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1198,17:44:02.117,24.081916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1199-1198,17:44:02.117,24.082479 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1200,17:44:02.117,24.082504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1201-1200,17:44:02.119,24.084478 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1202,17:44:02.120,24.084913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1203-1202,17:44:02.120,24.085478 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1204,17:44:02.120,24.085501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1205-1204,17:44:02.121,24.086502 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1206,17:44:02.122,24.086925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1207-1206,17:44:02.122,24.087482 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1208,17:44:02.122,24.087515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1209-1208,17:44:02.124,24.089479 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1210,17:44:02.125,24.089939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1211-1210,17:44:02.125,24.090481 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1212,17:44:02.125,24.090511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1213-1212,17:44:02.127,24.092478 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1214,17:44:02.128,24.092915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1215-1214,17:44:02.128,24.093479 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1216,17:44:02.128,24.093503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1217-1216,17:44:02.129,24.094510 s,1.007 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1218,17:44:02.130,24.094914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1219-1218,17:44:02.130,24.095481 s,567 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1220,17:44:02.130,24.095508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1221-1220,17:44:02.132,24.097479 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1222,17:44:02.133,24.097918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1223-1222,17:44:02.133,24.098478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1224,17:44:02.133,24.098503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1225-1224,17:44:02.135,24.100478 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1226,17:44:02.136,24.100914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1227-1226,17:44:02.136,24.101478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1228,17:44:02.136,24.101501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1229-1228,17:44:02.137,24.102512 s,1.011 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1230,17:44:02.138,24.102924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1231-1230,17:44:02.138,24.103484 s,559 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1232,17:44:02.138,24.103510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1233-1232,17:44:02.140,24.105481 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1234,17:44:02.141,24.105924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1235-1234,17:44:02.141,24.106478 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1236,17:44:02.141,24.106504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1237-1236,17:44:02.143,24.108478 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1238,17:44:02.144,24.108924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1239-1238,17:44:02.144,24.109482 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1240,17:44:02.144,24.109507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1241-1240,17:44:02.145,24.110507 s,1.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1242,17:44:02.146,24.110915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1243-1242,17:44:02.146,24.111480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1244,17:44:02.146,24.111505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1245-1244,17:44:02.148,24.113480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1246,17:44:02.149,24.113917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1247-1246,17:44:02.149,24.114477 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1248,17:44:02.149,24.114501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1249-1248,17:44:02.151,24.116478 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1250,17:44:02.152,24.116914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1251-1250,17:44:02.152,24.117478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1252,17:44:02.152,24.117501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1253-1252,17:44:02.153,24.118501 s,1000 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1254,17:44:02.154,24.118915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1255-1254,17:44:02.154,24.119481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1256,17:44:02.154,24.119506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1257-1256,17:44:02.156,24.121479 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1258,17:44:02.157,24.121923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1259-1258,17:44:02.157,24.122478 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1260,17:44:02.157,24.122506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1261-1260,17:44:02.159,24.124482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1262,17:44:02.160,24.124918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1263-1262,17:44:02.160,24.125476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1264,17:44:02.160,24.125500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1265-1264,17:44:02.161,24.126501 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1266,17:44:02.162,24.126916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1267-1266,17:44:02.162,24.127480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1268,17:44:02.162,24.127506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1269-1268,17:44:02.164,24.129478 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1270,17:44:02.165,24.129925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1271-1270,17:44:02.165,24.130477 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1272,17:44:02.165,24.130502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1273-1272,17:44:02.167,24.132478 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1274,17:44:02.168,24.132915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1275-1274,17:44:02.168,24.133477 s,562 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1276,17:44:02.168,24.133501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1277-1276,17:44:02.169,24.134503 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1278,17:44:02.170,24.134916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1279-1278,17:44:02.170,24.135482 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1280,17:44:02.170,24.135508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1281-1280,17:44:02.172,24.137480 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1282,17:44:02.173,24.137939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1283-1282,17:44:02.173,24.138479 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1284,17:44:02.173,24.138508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1285-1284,17:44:02.175,24.140477 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1286,17:44:02.176,24.140918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1287-1286,17:44:02.176,24.141476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1288,17:44:02.176,24.141500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1289-1288,17:44:02.177,24.142502 s,1.002 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1290,17:44:02.178,24.142916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1291-1290,17:44:02.178,24.143480 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1292,17:44:02.178,24.143505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1293-1292,17:44:02.180,24.145477 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1294,17:44:02.181,24.145917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1295-1294,17:44:02.181,24.146478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1296,17:44:02.181,24.146502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1297-1296,17:44:02.183,24.148477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1298,17:44:02.184,24.148917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1299-1298,17:44:02.184,24.149477 s,560 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1300,17:44:02.184,24.149502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1301-1300,17:44:02.185,24.150501 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1302,17:44:02.186,24.150917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1303-1302,17:44:02.186,24.151481 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1304,17:44:02.186,24.151506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1305-1304,17:44:02.188,24.153478 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1306,17:44:02.189,24.153919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1307-1306,17:44:02.189,24.154477 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1308,17:44:02.189,24.154502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1309-1308,17:44:02.191,24.156477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1310,17:44:02.192,24.156918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1311-1310,17:44:02.192,24.157477 s,559 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1312,17:44:02.192,24.157502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1313-1312,17:44:02.193,24.158501 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1314,17:44:02.194,24.158917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1315-1314,17:44:02.194,24.159489 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1316,17:44:02.194,24.159523 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1317-1316,17:44:02.196,24.161480 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1318,17:44:02.197,24.161929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1319-1318,17:44:02.197,24.162471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1320,17:44:02.197,24.162494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1321-1320,17:44:02.199,24.164470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1322,17:44:02.200,24.164914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1323-1322,17:44:02.200,24.165470 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1324,17:44:02.200,24.165492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1325-1324,17:44:02.201,24.166510 s,1.018 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1326,17:44:02.202,24.166918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1327-1326,17:44:02.202,24.167473 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1328,17:44:02.202,24.167500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1329-1328,17:44:02.204,24.169485 s,1.986 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1330,17:44:02.205,24.169923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1331-1330,17:44:02.205,24.170474 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1332,17:44:02.205,24.170502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1333-1332,17:44:02.207,24.172477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1334,17:44:02.208,24.172921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1335-1334,17:44:02.208,24.173470 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1336,17:44:02.208,24.173494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1337-1336,17:44:02.209,24.174504 s,1.009 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1338,17:44:02.210,24.174916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1339-1338,17:44:02.210,24.175474 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1340,17:44:02.210,24.175500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1341-1340,17:44:02.212,24.177474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1342,17:44:02.213,24.177917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1343-1342,17:44:02.213,24.178470 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1344,17:44:02.213,24.178493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1345-1344,17:44:02.215,24.180469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1346,17:44:02.216,24.180928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80085419A0h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1347-1346,17:44:02.216,24.181471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80085419A0h,Success (Success)\r
+URB,1348,17:44:02.216,24.181503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1349-1348,17:44:02.217,24.182498 s,994 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1350,17:44:02.218,24.182915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1351-1350,17:44:02.218,24.183472 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1352,17:44:02.218,24.183498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1353-1352,17:44:02.220,24.185472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1354,17:44:02.221,24.185917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1355-1354,17:44:02.221,24.186471 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1356,17:44:02.221,24.186493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1357-1356,17:44:02.223,24.188469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1358,17:44:02.224,24.188916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1359-1358,17:44:02.224,24.189470 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1360,17:44:02.224,24.189494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1361-1360,17:44:02.225,24.190497 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1362,17:44:02.226,24.190916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1363-1362,17:44:02.226,24.191472 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1364,17:44:02.226,24.191497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1365-1364,17:44:02.228,24.193472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1366,17:44:02.229,24.193917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1367-1366,17:44:02.229,24.194470 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1368,17:44:02.229,24.194493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1369-1368,17:44:02.231,24.196469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1370,17:44:02.232,24.196914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1371-1370,17:44:02.232,24.197469 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1372,17:44:02.232,24.197491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1373-1372,17:44:02.233,24.198469 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1374,17:44:02.234,24.198915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1375-1374,17:44:02.234,24.199469 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1376,17:44:02.234,24.199492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1377-1376,17:44:02.236,24.201470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1378,17:44:02.237,24.201917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1379-1378,17:44:02.237,24.202478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1380,17:44:02.237,24.202509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1381-1380,17:44:02.239,24.204473 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1382,17:44:02.240,24.204920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1383-1382,17:44:02.240,24.205471 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1384,17:44:02.240,24.205495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1385-1384,17:44:02.241,24.206505 s,1.010 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1386,17:44:02.242,24.206918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1387-1386,17:44:02.242,24.207493 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1388,17:44:02.242,24.207524 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1389-1388,17:44:02.244,24.209481 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1390,17:44:02.245,24.209930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1391-1390,17:44:02.245,24.210476 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1392,17:44:02.245,24.210503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1393-1392,17:44:02.247,24.212475 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1394,17:44:02.248,24.212919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1395-1394,17:44:02.248,24.213476 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1396,17:44:02.248,24.213499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1397-1396,17:44:02.249,24.214511 s,1.012 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1398,17:44:02.250,24.214919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1399-1398,17:44:02.250,24.215479 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1400,17:44:02.250,24.215505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1401-1400,17:44:02.252,24.217477 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1402,17:44:02.253,24.217922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1403-1402,17:44:02.253,24.218475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1404,17:44:02.253,24.218499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1405-1404,17:44:02.255,24.220476 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1406,17:44:02.256,24.220918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1407-1406,17:44:02.256,24.221476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1408,17:44:02.256,24.221499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1409-1408,17:44:02.257,24.222504 s,1.005 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1410,17:44:02.258,24.222924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1411-1410,17:44:02.258,24.223479 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1412,17:44:02.258,24.223505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1413-1412,17:44:02.260,24.225476 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1414,17:44:02.261,24.225921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1415-1414,17:44:02.261,24.226476 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1416,17:44:02.261,24.226500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1417-1416,17:44:02.263,24.228476 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1418,17:44:02.264,24.228922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1419-1418,17:44:02.264,24.229479 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1420,17:44:02.264,24.229506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1421-1420,17:44:02.266,24.231784 s,2.278 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1422,17:44:02.267,24.231919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1423-1422,17:44:02.267,24.232477 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1424,17:44:02.267,24.232503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1425-1424,17:44:02.269,24.234476 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1426,17:44:02.270,24.234918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1427-1426,17:44:02.270,24.235475 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1428,17:44:02.270,24.235498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1429-1428,17:44:02.272,24.237476 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1430,17:44:02.273,24.237925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1431-1430,17:44:02.273,24.238476 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1432,17:44:02.273,24.238499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1433-1432,17:44:02.275,24.240480 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1434,17:44:02.276,24.240921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1435-1434,17:44:02.276,24.241475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1436,17:44:02.276,24.241500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1437-1436,17:44:02.278,24.243475 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1438,17:44:02.279,24.243919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1439-1438,17:44:02.279,24.244475 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1440,17:44:02.279,24.244499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1441-1440,17:44:02.281,24.246475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1442,17:44:02.282,24.246919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1443-1442,17:44:02.282,24.247476 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1444,17:44:02.282,24.247499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1445-1444,17:44:02.284,24.249475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1446,17:44:02.285,24.249924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1447-1446,17:44:02.285,24.250475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1448,17:44:02.285,24.250500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1449-1448,17:44:02.287,24.252474 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1450,17:44:02.288,24.252919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1451-1450,17:44:02.288,24.253475 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1452,17:44:02.288,24.253499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1453-1452,17:44:02.290,24.255475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1454,17:44:02.291,24.255959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1455-1454,17:44:02.291,24.256471 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success)\r
+URB,1456,17:44:02.291,24.256501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1457-1456,17:44:02.293,24.258473 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1458,17:44:02.294,24.258921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1459-1458,17:44:02.294,24.259474 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1460,17:44:02.294,24.259499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1461-1460,17:44:02.295,24.260521 s,1.022 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1462,17:44:02.296,24.260928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1463-1462,17:44:02.296,24.261476 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1464,17:44:02.296,24.261505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1465-1464,17:44:02.298,24.263476 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1466,17:44:02.299,24.263930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1467-1466,17:44:02.299,24.264476 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1468,17:44:02.299,24.264502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1469-1468,17:44:02.301,24.266475 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1470,17:44:02.302,24.266922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1471-1470,17:44:02.302,24.267474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1472,17:44:02.302,24.267498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1473-1472,17:44:02.304,24.269475 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1474,17:44:02.305,24.269923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1475-1474,17:44:02.305,24.270475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1476,17:44:02.305,24.270500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1477-1476,17:44:02.307,24.272476 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1478,17:44:02.308,24.272920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1479-1478,17:44:02.308,24.273475 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1480,17:44:02.308,24.273498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1481-1480,17:44:02.310,24.275475 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1482,17:44:02.311,24.275922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1483-1482,17:44:02.311,24.276474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1484,17:44:02.311,24.276498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1485-1484,17:44:02.313,24.278475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1486,17:44:02.314,24.278921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1487-1486,17:44:02.314,24.279475 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1488,17:44:02.314,24.279499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1489-1488,17:44:02.316,24.281475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1490,17:44:02.317,24.281930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1491-1490,17:44:02.317,24.282475 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1492,17:44:02.317,24.282499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1493-1492,17:44:02.319,24.284474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1494,17:44:02.320,24.284921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1495-1494,17:44:02.320,24.285477 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1496,17:44:02.320,24.285501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1497-1496,17:44:02.322,24.287475 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1498,17:44:02.323,24.287920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1499-1498,17:44:02.323,24.288475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1500,17:44:02.323,24.288498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1501-1500,17:44:02.325,24.290474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1502,17:44:02.326,24.290924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1503-1502,17:44:02.326,24.291474 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1504,17:44:02.326,24.291499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1505-1504,17:44:02.328,24.293474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1506,17:44:02.329,24.293923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1507-1506,17:44:02.329,24.294475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1508,17:44:02.329,24.294500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1509-1508,17:44:02.331,24.296477 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1510,17:44:02.332,24.296928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1511-1510,17:44:02.332,24.297474 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1512,17:44:02.332,24.297498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1513-1512,17:44:02.334,24.299474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1514,17:44:02.335,24.299921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1515-1514,17:44:02.335,24.300474 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1516,17:44:02.335,24.300497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1517-1516,17:44:02.337,24.302474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1518,17:44:02.338,24.302921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1519-1518,17:44:02.338,24.303474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1520,17:44:02.338,24.303497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1521-1520,17:44:02.340,24.305475 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1522,17:44:02.341,24.305925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1523-1522,17:44:02.341,24.306476 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1524,17:44:02.341,24.306503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1525-1524,17:44:02.343,24.308474 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1526,17:44:02.344,24.308940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1527-1526,17:44:02.344,24.309470 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1528,17:44:02.344,24.309501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1529-1528,17:44:02.346,24.311472 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1530,17:44:02.347,24.311930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1531-1530,17:44:02.347,24.312474 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1532,17:44:02.347,24.312498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1533-1532,17:44:02.349,24.314474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1534,17:44:02.350,24.314922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1535-1534,17:44:02.350,24.315473 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1536,17:44:02.350,24.315497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1537-1536,17:44:02.352,24.317474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1538,17:44:02.353,24.317922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1539-1538,17:44:02.353,24.318476 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1540,17:44:02.353,24.318500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1541-1540,17:44:02.355,24.320475 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1542,17:44:02.356,24.320922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1543-1542,17:44:02.356,24.321474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1544,17:44:02.356,24.321497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1545-1544,17:44:02.358,24.323482 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1546,17:44:02.359,24.323937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1547-1546,17:44:02.359,24.324475 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1548,17:44:02.359,24.324504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1549-1548,17:44:02.361,24.326477 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1550,17:44:02.362,24.326932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1551-1550,17:44:02.362,24.327473 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1552,17:44:02.362,24.327498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1553-1552,17:44:02.364,24.329474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1554,17:44:02.365,24.329925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1555-1554,17:44:02.365,24.330473 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1556,17:44:02.365,24.330498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1557-1556,17:44:02.367,24.332473 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1558,17:44:02.368,24.332922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1559-1558,17:44:02.368,24.333473 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1560,17:44:02.368,24.333497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1561-1560,17:44:02.370,24.335474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1562,17:44:02.371,24.335922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1563-1562,17:44:02.371,24.336474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1564,17:44:02.371,24.336498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1565-1564,17:44:02.373,24.338474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1566,17:44:02.374,24.338922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1567-1566,17:44:02.374,24.339474 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1568,17:44:02.374,24.339497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1569-1568,17:44:02.376,24.341473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1570,17:44:02.377,24.341929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1571-1570,17:44:02.377,24.342474 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1572,17:44:02.377,24.342497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1573-1572,17:44:02.379,24.344473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1574,17:44:02.380,24.344923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1575-1574,17:44:02.380,24.345473 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1576,17:44:02.380,24.345496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1577-1576,17:44:02.382,24.347473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1578,17:44:02.383,24.347923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1579-1578,17:44:02.383,24.348473 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1580,17:44:02.383,24.348496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1581-1580,17:44:02.385,24.350474 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1582,17:44:02.386,24.350927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1583-1582,17:44:02.386,24.351477 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1584,17:44:02.386,24.351502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1585-1584,17:44:02.388,24.353473 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1586,17:44:02.389,24.353924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1587-1586,17:44:02.389,24.354473 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1588,17:44:02.389,24.354497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1589-1588,17:44:02.391,24.356472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1590,17:44:02.392,24.356925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1591-1590,17:44:02.392,24.357472 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1592,17:44:02.392,24.357497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1593-1592,17:44:02.394,24.359474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1594,17:44:02.395,24.359927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1595-1594,17:44:02.395,24.360473 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1596,17:44:02.395,24.360496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1597-1596,17:44:02.397,24.362473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1598,17:44:02.398,24.362923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1599-1598,17:44:02.398,24.363472 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1600,17:44:02.398,24.363495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1601-1600,17:44:02.400,24.365476 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1602,17:44:02.401,24.365924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1603-1602,17:44:02.401,24.366473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1604,17:44:02.401,24.366496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1605-1604,17:44:02.403,24.368472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1606,17:44:02.404,24.368924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1607-1606,17:44:02.404,24.369473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1608,17:44:02.404,24.369497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1609-1608,17:44:02.406,24.371473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1610,17:44:02.407,24.371929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1611-1610,17:44:02.407,24.372472 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1612,17:44:02.407,24.372496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1613-1612,17:44:02.409,24.374473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1614,17:44:02.410,24.374924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1615-1614,17:44:02.410,24.375472 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1616,17:44:02.410,24.375496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1617-1616,17:44:02.412,24.377473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1618,17:44:02.413,24.377924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1619-1618,17:44:02.413,24.378473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1620,17:44:02.413,24.378497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1621-1620,17:44:02.415,24.380514 s,2.018 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1622,17:44:02.416,24.380926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1623-1622,17:44:02.416,24.381478 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1624,17:44:02.416,24.381506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1625-1624,17:44:02.418,24.383488 s,1.982 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1626,17:44:02.419,24.383932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1627-1626,17:44:02.419,24.384475 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1628,17:44:02.419,24.384503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1629-1628,17:44:02.421,24.386473 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1630,17:44:02.422,24.386924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1631-1630,17:44:02.422,24.387473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1632,17:44:02.422,24.387497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1633-1632,17:44:02.424,24.389473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1634,17:44:02.425,24.389930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1635-1634,17:44:02.425,24.390472 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1636,17:44:02.425,24.390498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1637-1636,17:44:02.427,24.392473 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1638,17:44:02.428,24.392929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1639-1638,17:44:02.428,24.393473 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1640,17:44:02.428,24.393497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1641-1640,17:44:02.430,24.395472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1642,17:44:02.431,24.395924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1643-1642,17:44:02.431,24.396472 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1644,17:44:02.431,24.396496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1645-1644,17:44:02.433,24.398473 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1646,17:44:02.434,24.398925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1647-1646,17:44:02.434,24.399473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1648,17:44:02.434,24.399497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1649-1648,17:44:02.436,24.401473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1650,17:44:02.437,24.401931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1651-1650,17:44:02.437,24.402473 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1652,17:44:02.437,24.402496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1653-1652,17:44:02.439,24.404472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1654,17:44:02.440,24.404924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1655-1654,17:44:02.440,24.405474 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1656,17:44:02.440,24.405498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1657-1656,17:44:02.442,24.407473 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1658,17:44:02.443,24.407924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1659-1658,17:44:02.443,24.408472 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1660,17:44:02.443,24.408495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1661-1660,17:44:02.445,24.410473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1662,17:44:02.446,24.410929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1663-1662,17:44:02.446,24.411471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1664,17:44:02.446,24.411496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1665-1664,17:44:02.448,24.413471 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1666,17:44:02.449,24.413926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1667-1666,17:44:02.449,24.414472 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1668,17:44:02.449,24.414496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1669-1668,17:44:02.451,24.416472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1670,17:44:02.452,24.416925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1671-1670,17:44:02.452,24.417473 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1672,17:44:02.452,24.417496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1673-1672,17:44:02.454,24.419475 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1674,17:44:02.455,24.419927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1675-1674,17:44:02.455,24.420471 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1676,17:44:02.455,24.420495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1677-1676,17:44:02.457,24.422472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1678,17:44:02.458,24.422930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1679-1678,17:44:02.458,24.423471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1680,17:44:02.458,24.423495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1681-1680,17:44:02.460,24.425473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1682,17:44:02.461,24.425926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1683-1682,17:44:02.461,24.426472 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1684,17:44:02.461,24.426496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1685-1684,17:44:02.463,24.428472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1686,17:44:02.464,24.428927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1687-1686,17:44:02.464,24.429471 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1688,17:44:02.464,24.429495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1689-1688,17:44:02.466,24.431472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1690,17:44:02.467,24.431932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1691-1690,17:44:02.467,24.432472 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1692,17:44:02.467,24.432496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1693-1692,17:44:02.469,24.434472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1694,17:44:02.470,24.434926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1695-1694,17:44:02.470,24.435471 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1696,17:44:02.470,24.435495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1697-1696,17:44:02.472,24.437471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1698,17:44:02.473,24.437932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1699-1698,17:44:02.473,24.438471 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1700,17:44:02.473,24.438495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1701-1700,17:44:02.475,24.440473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1702,17:44:02.476,24.440926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1703-1702,17:44:02.476,24.441471 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1704,17:44:02.476,24.441494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1705-1704,17:44:02.478,24.443471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1706,17:44:02.479,24.443927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1707-1706,17:44:02.479,24.444472 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1708,17:44:02.479,24.444495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1709-1708,17:44:02.481,24.446472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1710,17:44:02.482,24.446927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1711-1710,17:44:02.482,24.447472 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1712,17:44:02.482,24.447495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1713-1712,17:44:02.484,24.449471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1714,17:44:02.485,24.449929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1715-1714,17:44:02.485,24.450471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1716,17:44:02.485,24.450496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1717-1716,17:44:02.487,24.452471 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1718,17:44:02.488,24.452927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1719-1718,17:44:02.488,24.453474 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1720,17:44:02.488,24.453498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1721-1720,17:44:02.490,24.455472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1722,17:44:02.491,24.455972 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1723-1722,17:44:02.491,24.456466 s,495 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success)\r
+URB,1724,17:44:02.491,24.456494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1725-1724,17:44:02.493,24.458469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1726,17:44:02.494,24.458928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1727-1726,17:44:02.494,24.459471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1728,17:44:02.494,24.459494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1729-1728,17:44:02.496,24.461471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1730,17:44:02.497,24.461931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1731-1730,17:44:02.497,24.462471 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1732,17:44:02.497,24.462495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1733-1732,17:44:02.499,24.464471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1734,17:44:02.500,24.464927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1735-1734,17:44:02.500,24.465470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1736,17:44:02.500,24.465494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1737-1736,17:44:02.502,24.467473 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1738,17:44:02.503,24.467927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1739-1738,17:44:02.503,24.468470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1740,17:44:02.503,24.468494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1741-1740,17:44:02.505,24.470472 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1742,17:44:02.506,24.470930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1743-1742,17:44:02.506,24.471471 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1744,17:44:02.506,24.471495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1745-1744,17:44:02.508,24.473471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1746,17:44:02.509,24.473928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1747-1746,17:44:02.509,24.474470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1748,17:44:02.509,24.474494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1749-1748,17:44:02.511,24.476470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1750,17:44:02.512,24.476929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1751-1750,17:44:02.512,24.477471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1752,17:44:02.512,24.477494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1753-1752,17:44:02.514,24.479471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1754,17:44:02.515,24.479928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1755-1754,17:44:02.515,24.480470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1756,17:44:02.515,24.480494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1757-1756,17:44:02.517,24.482471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1758,17:44:02.518,24.482928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1759-1758,17:44:02.518,24.483470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1760,17:44:02.518,24.483493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1761-1760,17:44:02.520,24.485470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1762,17:44:02.521,24.485928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1763-1762,17:44:02.521,24.486470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1764,17:44:02.521,24.486494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1765-1764,17:44:02.523,24.488471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1766,17:44:02.524,24.488929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1767-1766,17:44:02.524,24.489471 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1768,17:44:02.524,24.489494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1769-1768,17:44:02.526,24.491470 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1770,17:44:02.527,24.491932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1771-1770,17:44:02.527,24.492470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1772,17:44:02.527,24.492494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1773-1772,17:44:02.529,24.494470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1774,17:44:02.530,24.494928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1775-1774,17:44:02.530,24.495471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1776,17:44:02.530,24.495494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1777-1776,17:44:02.532,24.497470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1778,17:44:02.533,24.497928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1779-1778,17:44:02.533,24.498470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1780,17:44:02.533,24.498494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1781-1780,17:44:02.535,24.500470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1782,17:44:02.536,24.500929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1783-1782,17:44:02.536,24.501485 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1784,17:44:02.536,24.501514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1785-1784,17:44:02.538,24.503473 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1786,17:44:02.539,24.503932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1787-1786,17:44:02.539,24.504470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1788,17:44:02.539,24.504494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1789-1788,17:44:02.541,24.506469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1790,17:44:02.542,24.506928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1791-1790,17:44:02.542,24.507470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1792,17:44:02.542,24.507493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1793-1792,17:44:02.544,24.509470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1794,17:44:02.545,24.509933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1795-1794,17:44:02.545,24.510470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1796,17:44:02.545,24.510495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1797-1796,17:44:02.547,24.512470 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1798,17:44:02.548,24.512929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1799-1798,17:44:02.548,24.513470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1800,17:44:02.548,24.513493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1801-1800,17:44:02.550,24.515470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1802,17:44:02.551,24.515929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1803-1802,17:44:02.551,24.516470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1804,17:44:02.551,24.516493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1805-1804,17:44:02.553,24.518471 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1806,17:44:02.554,24.518929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1807-1806,17:44:02.554,24.519470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1808,17:44:02.554,24.519493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1809-1808,17:44:02.556,24.521471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1810,17:44:02.557,24.521934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1811-1810,17:44:02.557,24.522473 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1812,17:44:02.557,24.522497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1813-1812,17:44:02.559,24.524484 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1814,17:44:02.560,24.524933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1815-1814,17:44:02.560,24.525474 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1816,17:44:02.560,24.525502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1817-1816,17:44:02.562,24.527474 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1818,17:44:02.563,24.527930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1819-1818,17:44:02.563,24.528470 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1820,17:44:02.563,24.528494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1821-1820,17:44:02.565,24.530470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1822,17:44:02.566,24.530932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1823-1822,17:44:02.566,24.531469 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1824,17:44:02.566,24.531494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1825-1824,17:44:02.567,24.532523 s,1.029 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1826,17:44:02.568,24.532932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1827-1826,17:44:02.568,24.533476 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1828,17:44:02.568,24.533504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1829-1828,17:44:02.570,24.535471 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1830,17:44:02.571,24.535939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1831-1830,17:44:02.571,24.536470 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1832,17:44:02.571,24.536495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1833-1832,17:44:02.573,24.538471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1834,17:44:02.574,24.538930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1835-1834,17:44:02.574,24.539472 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1836,17:44:02.574,24.539497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1837-1836,17:44:02.576,24.541470 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1838,17:44:02.577,24.541932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1839-1838,17:44:02.577,24.542469 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1840,17:44:02.577,24.542493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1841-1840,17:44:02.579,24.544470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1842,17:44:02.580,24.544930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1843-1842,17:44:02.580,24.545470 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1844,17:44:02.580,24.545493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1845-1844,17:44:02.582,24.547469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1846,17:44:02.583,24.547930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1847-1846,17:44:02.583,24.548493 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1848,17:44:02.583,24.548518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1849-1848,17:44:02.585,24.550471 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1850,17:44:02.586,24.550933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1851-1850,17:44:02.586,24.551470 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1852,17:44:02.586,24.551495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1853-1852,17:44:02.588,24.553473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1854,17:44:02.589,24.553931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1855-1854,17:44:02.589,24.554469 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1856,17:44:02.589,24.554493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1857-1856,17:44:02.591,24.556469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1858,17:44:02.592,24.556933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1859-1858,17:44:02.592,24.557468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1860,17:44:02.592,24.557492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1861-1860,17:44:02.594,24.559470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1862,17:44:02.595,24.559931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1863-1862,17:44:02.595,24.560469 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1864,17:44:02.595,24.560492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1865-1864,17:44:02.597,24.562470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1866,17:44:02.598,24.562931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1867-1866,17:44:02.598,24.563468 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1868,17:44:02.598,24.563492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1869-1868,17:44:02.600,24.565469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1870,17:44:02.601,24.565930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1871-1870,17:44:02.601,24.566470 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1872,17:44:02.601,24.566494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1873-1872,17:44:02.603,24.568469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1874,17:44:02.604,24.568933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1875-1874,17:44:02.604,24.569468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1876,17:44:02.604,24.569492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1877-1876,17:44:02.606,24.571469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1878,17:44:02.607,24.571932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1879-1878,17:44:02.607,24.572468 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1880,17:44:02.607,24.572492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1881-1880,17:44:02.609,24.574469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1882,17:44:02.610,24.574934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1883-1882,17:44:02.610,24.575469 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1884,17:44:02.610,24.575493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1885-1884,17:44:02.612,24.577470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1886,17:44:02.613,24.577932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1887-1886,17:44:02.613,24.578470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1888,17:44:02.613,24.578493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1889-1888,17:44:02.615,24.580469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1890,17:44:02.616,24.580934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1891-1890,17:44:02.616,24.581469 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1892,17:44:02.616,24.581492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1893-1892,17:44:02.618,24.583469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1894,17:44:02.619,24.583932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1895-1894,17:44:02.619,24.584468 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1896,17:44:02.619,24.584492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1897-1896,17:44:02.621,24.586470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1898,17:44:02.622,24.586938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1899-1898,17:44:02.622,24.587467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1900,17:44:02.622,24.587493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1901-1900,17:44:02.624,24.589468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1902,17:44:02.625,24.589943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1903-1902,17:44:02.625,24.590468 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1904,17:44:02.625,24.590494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1905-1904,17:44:02.627,24.592469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1906,17:44:02.628,24.592935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1907-1906,17:44:02.628,24.593471 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1908,17:44:02.628,24.593496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1909-1908,17:44:02.630,24.595468 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1910,17:44:02.631,24.595933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1911-1910,17:44:02.631,24.596468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1912,17:44:02.631,24.596492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1913-1912,17:44:02.633,24.598468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1914,17:44:02.634,24.598933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1915-1914,17:44:02.634,24.599468 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1916,17:44:02.634,24.599492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1917-1916,17:44:02.636,24.601469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1918,17:44:02.637,24.601933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1919-1918,17:44:02.637,24.602468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1920,17:44:02.637,24.602492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1921-1920,17:44:02.639,24.604468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1922,17:44:02.640,24.604932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1923-1922,17:44:02.640,24.605468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1924,17:44:02.640,24.605491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1925-1924,17:44:02.642,24.607471 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1926,17:44:02.643,24.607934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1927-1926,17:44:02.643,24.608468 s,534 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1928,17:44:02.643,24.608491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1929-1928,17:44:02.645,24.610468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1930,17:44:02.646,24.610935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1931-1930,17:44:02.646,24.611468 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1932,17:44:02.646,24.611492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1933-1932,17:44:02.648,24.613469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1934,17:44:02.649,24.613937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1935-1934,17:44:02.649,24.614467 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1936,17:44:02.649,24.614493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1937-1936,17:44:02.651,24.616468 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1938,17:44:02.652,24.616933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1939-1938,17:44:02.652,24.617468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1940,17:44:02.652,24.617491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1941-1940,17:44:02.654,24.619468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1942,17:44:02.655,24.619933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1943-1942,17:44:02.655,24.620467 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1944,17:44:02.655,24.620491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1945-1944,17:44:02.657,24.622468 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1946,17:44:02.658,24.622937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1947-1946,17:44:02.658,24.623468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1948,17:44:02.658,24.623491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1949-1948,17:44:02.660,24.625467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1950,17:44:02.661,24.625933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1951-1950,17:44:02.661,24.626468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1952,17:44:02.661,24.626492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1953-1952,17:44:02.663,24.628467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1954,17:44:02.664,24.628935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1955-1954,17:44:02.664,24.629468 s,533 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1956,17:44:02.664,24.629492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1957-1956,17:44:02.666,24.631468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1958,17:44:02.667,24.631934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1959-1958,17:44:02.667,24.632468 s,534 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1960,17:44:02.667,24.632491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1961-1960,17:44:02.669,24.634469 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1962,17:44:02.670,24.634936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1963-1962,17:44:02.670,24.635467 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1964,17:44:02.670,24.635491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1965-1964,17:44:02.672,24.637468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1966,17:44:02.673,24.637940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1967-1966,17:44:02.673,24.638468 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1968,17:44:02.673,24.638492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1969-1968,17:44:02.675,24.640468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1970,17:44:02.676,24.640934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1971-1970,17:44:02.676,24.641470 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1972,17:44:02.676,24.641493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1973-1972,17:44:02.678,24.643467 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1974,17:44:02.679,24.643934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1975-1974,17:44:02.679,24.644467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1976,17:44:02.679,24.644490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1977-1976,17:44:02.681,24.646467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1978,17:44:02.682,24.646934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1979-1978,17:44:02.682,24.647467 s,533 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1980,17:44:02.682,24.647491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1981-1980,17:44:02.684,24.649468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1982,17:44:02.685,24.649937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1983-1982,17:44:02.685,24.650468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1984,17:44:02.685,24.650492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1985-1984,17:44:02.687,24.652467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1986,17:44:02.688,24.652934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1987-1986,17:44:02.688,24.653467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1988,17:44:02.688,24.653491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1989-1988,17:44:02.690,24.655470 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1990,17:44:02.691,24.655938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1991-1990,17:44:02.691,24.656468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1992,17:44:02.691,24.656491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1993-1992,17:44:02.693,24.658467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1994,17:44:02.694,24.658936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1995-1994,17:44:02.694,24.659468 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,1996,17:44:02.694,24.659491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,1997-1996,17:44:02.696,24.661467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,1998,17:44:02.697,24.661935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,1999-1998,17:44:02.697,24.662467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2000,17:44:02.697,24.662490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2001-2000,17:44:02.699,24.664467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2002,17:44:02.700,24.664934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2003-2002,17:44:02.700,24.665467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2004,17:44:02.700,24.665490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2005-2004,17:44:02.702,24.667469 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2006,17:44:02.703,24.667936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2007-2006,17:44:02.703,24.668467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2008,17:44:02.703,24.668492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2009-2008,17:44:02.705,24.670468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2010,17:44:02.706,24.670938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2011-2010,17:44:02.706,24.671467 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2012,17:44:02.706,24.671492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2013-2012,17:44:02.708,24.673467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2014,17:44:02.709,24.673937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2015-2014,17:44:02.709,24.674467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2016,17:44:02.709,24.674492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2017-2016,17:44:02.711,24.676467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2018,17:44:02.712,24.676936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2019-2018,17:44:02.712,24.677466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2020,17:44:02.712,24.677490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2021-2020,17:44:02.714,24.679468 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2022,17:44:02.715,24.679936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2023-2022,17:44:02.715,24.680466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2024,17:44:02.715,24.680490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2025-2024,17:44:02.717,24.682467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2026,17:44:02.718,24.682935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2027-2026,17:44:02.718,24.683467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2028,17:44:02.718,24.683490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2029-2028,17:44:02.720,24.685467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2030,17:44:02.721,24.685935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2031-2030,17:44:02.721,24.686467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2032,17:44:02.721,24.686490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2033-2032,17:44:02.723,24.688470 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2034,17:44:02.724,24.688938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2035-2034,17:44:02.724,24.689481 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2036,17:44:02.724,24.689511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2037-2036,17:44:02.726,24.691474 s,1.963 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2038,17:44:02.727,24.691937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2039-2038,17:44:02.727,24.692473 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2040,17:44:02.727,24.692498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2041-2040,17:44:02.729,24.694467 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2042,17:44:02.730,24.694936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2043-2042,17:44:02.730,24.695466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2044,17:44:02.730,24.695491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2045-2044,17:44:02.732,24.697467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2046,17:44:02.733,24.697936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2047-2046,17:44:02.733,24.698466 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2048,17:44:02.733,24.698490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2049-2048,17:44:02.735,24.700473 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2050,17:44:02.736,24.700936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2051-2050,17:44:02.736,24.701466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2052,17:44:02.736,24.701490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2053-2052,17:44:02.738,24.703469 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2054,17:44:02.739,24.703937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2055-2054,17:44:02.739,24.704475 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2056,17:44:02.739,24.704498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2057-2056,17:44:02.741,24.706474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2058,17:44:02.742,24.706937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2059-2058,17:44:02.742,24.707474 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2060,17:44:02.742,24.707497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2061-2060,17:44:02.744,24.709467 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2062,17:44:02.745,24.709945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2063-2062,17:44:02.745,24.710474 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2064,17:44:02.745,24.710500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2065-2064,17:44:02.747,24.712468 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2066,17:44:02.748,24.712944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2067-2066,17:44:02.748,24.713475 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2068,17:44:02.748,24.713500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2069-2068,17:44:02.750,24.715466 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2070,17:44:02.751,24.715937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2071-2070,17:44:02.751,24.716466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2072,17:44:02.751,24.716490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2073-2072,17:44:02.753,24.718466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2074,17:44:02.754,24.718937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2075-2074,17:44:02.754,24.719466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2076,17:44:02.754,24.719491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2077-2076,17:44:02.756,24.721466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2078,17:44:02.757,24.721937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2079-2078,17:44:02.757,24.722467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2080,17:44:02.757,24.722491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2081-2080,17:44:02.759,24.724466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2082,17:44:02.760,24.724937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2083-2082,17:44:02.760,24.725465 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2084,17:44:02.760,24.725489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2085-2084,17:44:02.762,24.727467 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2086,17:44:02.763,24.727937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2087-2086,17:44:02.763,24.728465 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2088,17:44:02.763,24.728489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2089-2088,17:44:02.765,24.730466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2090,17:44:02.766,24.730941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2091-2090,17:44:02.766,24.731465 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2092,17:44:02.766,24.731490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2093-2092,17:44:02.768,24.733466 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2094,17:44:02.769,24.733937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2095-2094,17:44:02.769,24.734466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2096,17:44:02.769,24.734490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2097-2096,17:44:02.771,24.736465 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2098,17:44:02.772,24.736937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2099-2098,17:44:02.772,24.737468 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2100,17:44:02.772,24.737492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2101-2100,17:44:02.774,24.739466 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2102,17:44:02.775,24.739937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2103-2102,17:44:02.775,24.740465 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2104,17:44:02.775,24.740489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2105-2104,17:44:02.777,24.742467 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2106,17:44:02.778,24.742938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2107-2106,17:44:02.778,24.743465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2108,17:44:02.778,24.743489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2109-2108,17:44:02.780,24.745466 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2110,17:44:02.781,24.745938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2111-2110,17:44:02.781,24.746465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2112,17:44:02.781,24.746489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2113-2112,17:44:02.783,24.748465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2114,17:44:02.784,24.748939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2115-2114,17:44:02.784,24.749465 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2116,17:44:02.784,24.749489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2117-2116,17:44:02.786,24.751468 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2118,17:44:02.787,24.751938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2119-2118,17:44:02.787,24.752465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2120,17:44:02.787,24.752488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2121-2120,17:44:02.789,24.754465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2122,17:44:02.790,24.754939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2123-2122,17:44:02.790,24.755464 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2124,17:44:02.790,24.755488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2125-2124,17:44:02.792,24.757465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2126,17:44:02.793,24.757938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2127-2126,17:44:02.793,24.758465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2128,17:44:02.793,24.758488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2129-2128,17:44:02.795,24.760466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2130,17:44:02.796,24.760940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2131-2130,17:44:02.796,24.761466 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2132,17:44:02.796,24.761489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2133-2132,17:44:02.798,24.763466 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2134,17:44:02.799,24.763938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2135-2134,17:44:02.799,24.764465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2136,17:44:02.799,24.764489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2137-2136,17:44:02.801,24.766465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2138,17:44:02.802,24.766938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2139-2138,17:44:02.802,24.767466 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2140,17:44:02.802,24.767489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2141-2140,17:44:02.804,24.769465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2142,17:44:02.805,24.769941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2143-2142,17:44:02.805,24.770464 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2144,17:44:02.805,24.770489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2145-2144,17:44:02.807,24.772465 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2146,17:44:02.808,24.772940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2147-2146,17:44:02.808,24.773464 s,524 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2148,17:44:02.808,24.773487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2149-2148,17:44:02.810,24.775466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2150,17:44:02.811,24.775939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2151-2150,17:44:02.811,24.776465 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2152,17:44:02.811,24.776488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2153-2152,17:44:02.813,24.778466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2154,17:44:02.814,24.778939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2155-2154,17:44:02.814,24.779464 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2156,17:44:02.814,24.779488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2157-2156,17:44:02.816,24.781465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2158,17:44:02.817,24.781952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2159-2158,17:44:02.817,24.782476 s,524 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2160,17:44:02.817,24.782505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2161-2160,17:44:02.819,24.784463 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2162,17:44:02.820,24.784938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2163-2162,17:44:02.820,24.785458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2164,17:44:02.820,24.785480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2165-2164,17:44:02.822,24.787457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2166,17:44:02.823,24.787937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2167-2166,17:44:02.823,24.788458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2168,17:44:02.823,24.788480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2169-2168,17:44:02.824,24.789461 s,980 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2170,17:44:02.825,24.789939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2171-2170,17:44:02.825,24.790459 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2172,17:44:02.825,24.790482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2173-2172,17:44:02.827,24.792457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2174,17:44:02.828,24.792937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2175-2174,17:44:02.828,24.793458 s,521 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2176,17:44:02.828,24.793481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2177-2176,17:44:02.830,24.795457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2178,17:44:02.831,24.795938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2179-2178,17:44:02.831,24.796457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2180,17:44:02.831,24.796479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2181-2180,17:44:02.832,24.797458 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2182,17:44:02.833,24.797937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2183-2182,17:44:02.833,24.798458 s,521 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2184,17:44:02.833,24.798487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2185-2184,17:44:02.835,24.800457 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2186,17:44:02.836,24.800937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2187-2186,17:44:02.836,24.801458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2188,17:44:02.836,24.801480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2189-2188,17:44:02.838,24.803457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2190,17:44:02.839,24.803937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2191-2190,17:44:02.839,24.804458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2192,17:44:02.839,24.804480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2193-2192,17:44:02.840,24.805457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2194,17:44:02.841,24.805937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2195-2194,17:44:02.841,24.806458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2196,17:44:02.841,24.806480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2197-2196,17:44:02.843,24.808458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2198,17:44:02.844,24.808938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2199-2198,17:44:02.844,24.809457 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2200,17:44:02.844,24.809480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2201-2200,17:44:02.846,24.811456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2202,17:44:02.847,24.811937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2203-2202,17:44:02.847,24.812457 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2204,17:44:02.847,24.812479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2205-2204,17:44:02.848,24.813457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2206,17:44:02.849,24.813938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2207-2206,17:44:02.849,24.814457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2208,17:44:02.849,24.814479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2209-2208,17:44:02.851,24.816457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2210,17:44:02.852,24.816938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2211-2210,17:44:02.852,24.817457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2212,17:44:02.852,24.817479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2213-2212,17:44:02.854,24.819457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2214,17:44:02.855,24.819938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2215-2214,17:44:02.855,24.820457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2216,17:44:02.855,24.820479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2217-2216,17:44:02.856,24.821457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2218,17:44:02.857,24.821945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2219-2218,17:44:02.857,24.822457 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2220,17:44:02.857,24.822479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2221-2220,17:44:02.859,24.824457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2222,17:44:02.860,24.824939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2223-2222,17:44:02.860,24.825457 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2224,17:44:02.860,24.825480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2225-2224,17:44:02.862,24.827457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2226,17:44:02.863,24.827939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2227-2226,17:44:02.863,24.828457 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2228,17:44:02.863,24.828479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2229-2228,17:44:02.864,24.829471 s,992 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2230,17:44:02.865,24.829943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2231-2230,17:44:02.865,24.830468 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2232,17:44:02.865,24.830494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2233-2232,17:44:02.867,24.832464 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2234,17:44:02.868,24.832941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2235-2234,17:44:02.868,24.833463 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2236,17:44:02.868,24.833487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2237-2236,17:44:02.870,24.835464 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2238,17:44:02.871,24.835940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2239-2238,17:44:02.871,24.836463 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2240,17:44:02.871,24.836487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2241-2240,17:44:02.873,24.838467 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2242,17:44:02.874,24.838942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2243-2242,17:44:02.874,24.839464 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2244,17:44:02.874,24.839488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2245-2244,17:44:02.876,24.841464 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2246,17:44:02.877,24.841941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2247-2246,17:44:02.877,24.842464 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2248,17:44:02.877,24.842487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2249-2248,17:44:02.879,24.844463 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2250,17:44:02.880,24.844942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2251-2250,17:44:02.880,24.845464 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2252,17:44:02.880,24.845487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2253-2252,17:44:02.882,24.847464 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2254,17:44:02.883,24.847941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2255-2254,17:44:02.883,24.848463 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2256,17:44:02.883,24.848487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2257-2256,17:44:02.885,24.850463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2258,17:44:02.886,24.850944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2259-2258,17:44:02.886,24.851463 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2260,17:44:02.886,24.851487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2261-2260,17:44:02.888,24.853464 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2262,17:44:02.889,24.853946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2263-2262,17:44:02.889,24.854464 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2264,17:44:02.889,24.854489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2265-2264,17:44:02.891,24.856463 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2266,17:44:02.892,24.856943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2267-2266,17:44:02.892,24.857463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2268,17:44:02.892,24.857488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2269-2268,17:44:02.894,24.859463 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2270,17:44:02.895,24.859945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2271-2270,17:44:02.895,24.860463 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2272,17:44:02.895,24.860487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2273-2272,17:44:02.897,24.862463 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2274,17:44:02.898,24.862942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2275-2274,17:44:02.898,24.863463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2276,17:44:02.898,24.863486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2277-2276,17:44:02.900,24.865463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2278,17:44:02.901,24.865942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2279-2278,17:44:02.901,24.866463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2280,17:44:02.901,24.866486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2281-2280,17:44:02.903,24.868463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2282,17:44:02.904,24.868945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2283-2282,17:44:02.904,24.869466 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2284,17:44:02.904,24.869491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2285-2284,17:44:02.906,24.871465 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2286,17:44:02.907,24.871943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2287-2286,17:44:02.907,24.872466 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2288,17:44:02.907,24.872489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2289-2288,17:44:02.909,24.874463 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2290,17:44:02.910,24.874943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2291-2290,17:44:02.910,24.875463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2292,17:44:02.910,24.875486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2293-2292,17:44:02.912,24.877463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2294,17:44:02.913,24.877943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2295-2294,17:44:02.913,24.878463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2296,17:44:02.913,24.878486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2297-2296,17:44:02.915,24.880463 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2298,17:44:02.916,24.880943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2299-2298,17:44:02.916,24.881462 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2300,17:44:02.916,24.881486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2301-2300,17:44:02.918,24.883463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2302,17:44:02.919,24.883942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2303-2302,17:44:02.919,24.884508 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2304,17:44:02.919,24.884533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2305-2304,17:44:02.921,24.886508 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2306,17:44:02.922,24.886959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2307-2306,17:44:02.922,24.887468 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2308,17:44:02.922,24.887499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2309-2308,17:44:02.924,24.889493 s,1.994 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2310,17:44:02.925,24.889959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2311-2310,17:44:02.925,24.890469 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2312,17:44:02.925,24.890498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2313-2312,17:44:02.927,24.892498 s,2.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2314,17:44:02.928,24.892966 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2315-2314,17:44:02.928,24.893481 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2316,17:44:02.928,24.893517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2317-2316,17:44:02.930,24.895471 s,1.953 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2318,17:44:02.931,24.895955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2319-2318,17:44:02.931,24.896468 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2320,17:44:02.931,24.896498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2321-2320,17:44:02.933,24.898463 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2322,17:44:02.934,24.899023 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2323-2322,17:44:02.934,24.899463 s,440 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2324,17:44:02.934,24.899495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2325-2324,17:44:02.936,24.901462 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2326,17:44:02.937,24.901953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2327-2326,17:44:02.937,24.902499 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2328,17:44:02.937,24.902545 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2329-2328,17:44:02.939,24.904556 s,2.011 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2330,17:44:02.940,24.904949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2331-2330,17:44:02.940,24.905466 s,517 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2332,17:44:02.940,24.905494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2333-2332,17:44:02.942,24.907461 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2334,17:44:02.943,24.907946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2335-2334,17:44:02.943,24.908461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2336,17:44:02.943,24.908486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2337-2336,17:44:02.945,24.910463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2338,17:44:02.946,24.910959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2339-2338,17:44:02.946,24.911462 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2340,17:44:02.946,24.911491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2341-2340,17:44:02.948,24.913462 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2342,17:44:02.949,24.913948 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2343-2342,17:44:02.949,24.914462 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2344,17:44:02.949,24.914486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2345-2344,17:44:02.951,24.916462 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2346,17:44:02.952,24.916946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2347-2346,17:44:02.952,24.917464 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2348,17:44:02.952,24.917489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2349-2348,17:44:02.954,24.919462 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2350,17:44:02.955,24.919946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2351-2350,17:44:02.955,24.920463 s,517 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2352,17:44:02.955,24.920487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2353-2352,17:44:02.957,24.922462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2354,17:44:02.958,24.922951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2355-2354,17:44:02.958,24.923464 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2356,17:44:02.958,24.923488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2357-2356,17:44:02.960,24.925461 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2358,17:44:02.961,24.925946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2359-2358,17:44:02.961,24.926465 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2360,17:44:02.961,24.926489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2361-2360,17:44:02.963,24.928461 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2362,17:44:02.964,24.928949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2363-2362,17:44:02.964,24.929469 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2364,17:44:02.964,24.929496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2365-2364,17:44:02.966,24.931462 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2366,17:44:02.967,24.931947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2367-2366,17:44:02.967,24.932461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2368,17:44:02.967,24.932487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2369-2368,17:44:02.969,24.934462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2370,17:44:02.970,24.934947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2371-2370,17:44:02.970,24.935462 s,516 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2372,17:44:02.970,24.935487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2373-2372,17:44:02.972,24.937473 s,1.986 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2374,17:44:02.973,24.938041 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2375-2374,17:44:02.973,24.938475 s,434 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2376,17:44:02.973,24.938541 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2377-2376,17:44:02.975,24.940483 s,1.942 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2378,17:44:02.976,24.941008 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2379-2378,17:44:02.976,24.941483 s,475 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2380,17:44:02.976,24.941540 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2381-2380,17:44:02.978,24.943485 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2382,17:44:02.979,24.943980 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2383-2382,17:44:02.979,24.944464 s,484 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2384,17:44:02.979,24.944496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2385-2384,17:44:02.981,24.946472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2386,17:44:02.982,24.946974 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2387-2386,17:44:02.982,24.947470 s,496 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2388,17:44:02.982,24.947518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2389-2388,17:44:02.984,24.949461 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2390,17:44:02.985,24.949987 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2391-2390,17:44:02.985,24.950462 s,475 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2392,17:44:02.985,24.950491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2393-2392,17:44:02.987,24.952462 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2394,17:44:02.988,24.952952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2395-2394,17:44:02.988,24.953461 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2396,17:44:02.988,24.953488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2397-2396,17:44:02.990,24.955468 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2398,17:44:02.991,24.956003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2399-2398,17:44:02.991,24.956462 s,459 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2400,17:44:02.991,24.956494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2401-2400,17:44:02.993,24.958459 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2402,17:44:02.994,24.958944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2403-2402,17:44:02.994,24.959458 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2404,17:44:02.994,24.959481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2405-2404,17:44:02.996,24.961477 s,1.996 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2406,17:44:02.997,24.962161 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2407-2406,17:44:02.997,24.962468 s,308 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success)\r
+URB,2408,17:44:02.997,24.962638 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2409-2408,17:44:02.999,24.964468 s,1.830 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2410,17:44:03.000,24.964956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2411-2410,17:44:03.000,24.965487 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2412,17:44:03.000,24.965525 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2413-2412,17:44:03.002,24.967484 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2414,17:44:03.003,24.967949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2415-2414,17:44:03.003,24.968469 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2416,17:44:03.003,24.968497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2417-2416,17:44:03.005,24.970464 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2418,17:44:03.006,24.970950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2419-2418,17:44:03.006,24.971462 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2420,17:44:03.006,24.971488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2421-2420,17:44:03.008,24.973462 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2422,17:44:03.009,24.973947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2423-2422,17:44:03.009,24.974461 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2424,17:44:03.009,24.974486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2425-2424,17:44:03.011,24.976462 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2426,17:44:03.012,24.976947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2427-2426,17:44:03.012,24.977461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2428,17:44:03.012,24.977485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2429-2428,17:44:03.014,24.979475 s,1.990 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2430,17:44:03.015,24.979996 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2431-2430,17:44:03.015,24.980474 s,478 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2432,17:44:03.015,24.980708 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2433-2432,17:44:03.017,24.982459 s,1.751 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2434,17:44:03.018,24.982953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2435-2434,17:44:03.018,24.983462 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2436,17:44:03.018,24.983486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2437-2436,17:44:03.020,24.985461 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2438,17:44:03.021,24.985947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2439-2438,17:44:03.021,24.986460 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2440,17:44:03.021,24.986484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2441-2440,17:44:03.023,24.988461 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2442,17:44:03.024,24.988950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2443-2442,17:44:03.024,24.989460 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2444,17:44:03.024,24.989485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2445-2444,17:44:03.026,24.991461 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2446,17:44:03.027,24.991947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2447-2446,17:44:03.027,24.992461 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2448,17:44:03.027,24.992484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2449-2448,17:44:03.029,24.994467 s,1.983 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2450,17:44:03.030,24.994956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2451-2450,17:44:03.030,24.995461 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2452,17:44:03.030,24.995488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2453-2452,17:44:03.032,24.997459 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2454,17:44:03.033,24.997953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2455-2454,17:44:03.033,24.998461 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2456,17:44:03.033,24.998485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2457-2456,17:44:03.035,25.000461 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2458,17:44:03.036,25.000949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2459-2458,17:44:03.036,25.001472 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2460,17:44:03.036,25.001502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2461-2460,17:44:03.038,25.003463 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2462,17:44:03.039,25.003954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2463-2462,17:44:03.039,25.004465 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2464,17:44:03.039,25.004495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2465-2464,17:44:03.041,25.006472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2466,17:44:03.042,25.007032 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2467-2466,17:44:03.042,25.007461 s,428 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2468,17:44:03.042,25.007495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2469-2468,17:44:03.044,25.009462 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2470,17:44:03.045,25.009969 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2471-2470,17:44:03.045,25.010462 s,492 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2472,17:44:03.045,25.010491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2473-2472,17:44:03.047,25.012459 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2474,17:44:03.048,25.012950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2475-2474,17:44:03.048,25.013460 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2476,17:44:03.048,25.013485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2477-2476,17:44:03.050,25.015464 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2478,17:44:03.051,25.015967 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2479-2478,17:44:03.051,25.016460 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2480,17:44:03.051,25.016487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2481-2480,17:44:03.053,25.018462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2482,17:44:03.054,25.018950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2483-2482,17:44:03.054,25.019459 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2484,17:44:03.054,25.019484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2485-2484,17:44:03.056,25.021460 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2486,17:44:03.057,25.021951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2487-2486,17:44:03.057,25.022460 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2488,17:44:03.057,25.022485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2489-2488,17:44:03.059,25.024461 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2490,17:44:03.060,25.024963 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2491-2490,17:44:03.060,25.025461 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2492,17:44:03.060,25.025489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2493-2492,17:44:03.062,25.027460 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2494,17:44:03.063,25.027950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2495-2494,17:44:03.063,25.028460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2496,17:44:03.063,25.028485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2497-2496,17:44:03.065,25.030460 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2498,17:44:03.066,25.030962 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2499-2498,17:44:03.066,25.031460 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2500,17:44:03.066,25.031488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2501-2500,17:44:03.068,25.033460 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2502,17:44:03.069,25.033953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2503-2502,17:44:03.069,25.034459 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2504,17:44:03.069,25.034484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2505-2504,17:44:03.071,25.036459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2506,17:44:03.072,25.036950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2507-2506,17:44:03.072,25.037460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2508,17:44:03.072,25.037485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2509-2508,17:44:03.074,25.039466 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2510,17:44:03.075,25.039951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2511-2510,17:44:03.075,25.040463 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2512,17:44:03.075,25.040489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2513-2512,17:44:03.077,25.042464 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2514,17:44:03.078,25.042954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2515-2514,17:44:03.078,25.043464 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2516,17:44:03.078,25.043493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2517-2516,17:44:03.080,25.045471 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2518,17:44:03.081,25.045956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2519-2518,17:44:03.081,25.046482 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2520,17:44:03.081,25.046520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2521-2520,17:44:03.083,25.048513 s,1.993 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2522,17:44:03.084,25.048960 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2523-2522,17:44:03.084,25.049488 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2524,17:44:03.084,25.049533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2525-2524,17:44:03.086,25.051467 s,1.933 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2526,17:44:03.087,25.051951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2527-2526,17:44:03.087,25.052461 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2528,17:44:03.087,25.052486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2529-2528,17:44:03.089,25.054461 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2530,17:44:03.090,25.054950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2531-2530,17:44:03.090,25.055460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2532,17:44:03.090,25.055484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2533-2532,17:44:03.092,25.057459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2534,17:44:03.093,25.057950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2535-2534,17:44:03.093,25.058460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2536,17:44:03.093,25.058484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2537-2536,17:44:03.095,25.060459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2538,17:44:03.096,25.060950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2539-2538,17:44:03.096,25.061460 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2540,17:44:03.096,25.061484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2541-2540,17:44:03.098,25.063462 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2542,17:44:03.099,25.063950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2543-2542,17:44:03.099,25.064459 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2544,17:44:03.099,25.064483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2545-2544,17:44:03.101,25.066470 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2546,17:44:03.102,25.067003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2547-2546,17:44:03.102,25.067459 s,456 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success)\r
+URB,2548,17:44:03.102,25.067490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2549-2548,17:44:03.104,25.069485 s,1.995 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2550,17:44:03.105,25.070003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2551-2550,17:44:03.105,25.070458 s,454 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2552,17:44:03.105,25.070489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2553-2552,17:44:03.107,25.072462 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2554,17:44:03.108,25.072954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2555-2554,17:44:03.108,25.073459 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2556,17:44:03.108,25.073484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2557-2556,17:44:03.110,25.075458 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2558,17:44:03.111,25.075950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2559-2558,17:44:03.111,25.076458 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2560,17:44:03.111,25.076483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2561-2560,17:44:03.113,25.078459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2562,17:44:03.114,25.078952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2563-2562,17:44:03.114,25.079459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2564,17:44:03.114,25.079483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2565-2564,17:44:03.116,25.081459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2566,17:44:03.117,25.081950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2567-2566,17:44:03.117,25.082458 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2568,17:44:03.117,25.082482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2569-2568,17:44:03.119,25.084459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2570,17:44:03.120,25.084952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2571-2570,17:44:03.120,25.085459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2572,17:44:03.120,25.085483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2573-2572,17:44:03.122,25.087460 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2574,17:44:03.123,25.087951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2575-2574,17:44:03.123,25.088459 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2576,17:44:03.123,25.088483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2577-2576,17:44:03.125,25.090459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2578,17:44:03.126,25.090954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2579-2578,17:44:03.126,25.091458 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2580,17:44:03.126,25.091483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2581-2580,17:44:03.128,25.093459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2582,17:44:03.129,25.093951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2583-2582,17:44:03.129,25.094459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2584,17:44:03.129,25.094482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2585-2584,17:44:03.131,25.096459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2586,17:44:03.132,25.096951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2587-2586,17:44:03.132,25.097458 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2588,17:44:03.132,25.097482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2589-2588,17:44:03.134,25.099459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2590,17:44:03.135,25.099954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2591-2590,17:44:03.135,25.100470 s,516 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2592,17:44:03.135,25.100505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2593-2592,17:44:03.137,25.102463 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2594,17:44:03.138,25.102964 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2595-2594,17:44:03.138,25.103458 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2596,17:44:03.138,25.103484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2597-2596,17:44:03.140,25.105459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2598,17:44:03.141,25.105951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2599-2598,17:44:03.141,25.106459 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2600,17:44:03.141,25.106483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2601-2600,17:44:03.143,25.108458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2602,17:44:03.144,25.108955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2603-2602,17:44:03.144,25.109458 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2604,17:44:03.144,25.109482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2605-2604,17:44:03.146,25.111458 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2606,17:44:03.147,25.111952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2607-2606,17:44:03.147,25.112458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2608,17:44:03.147,25.112482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2609-2608,17:44:03.149,25.114462 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2610,17:44:03.150,25.114952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2611-2610,17:44:03.150,25.115458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2612,17:44:03.150,25.115481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2613-2612,17:44:03.152,25.117461 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2614,17:44:03.153,25.117960 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2615-2614,17:44:03.153,25.118459 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2616,17:44:03.153,25.118486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2617-2616,17:44:03.155,25.120458 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2618,17:44:03.156,25.120953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2619-2618,17:44:03.156,25.121459 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2620,17:44:03.156,25.121482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2621-2620,17:44:03.158,25.123457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2622,17:44:03.159,25.123952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2623-2622,17:44:03.159,25.124457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2624,17:44:03.159,25.124481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2625-2624,17:44:03.161,25.126458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2626,17:44:03.162,25.126952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2627-2626,17:44:03.162,25.127458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2628,17:44:03.162,25.127481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2629-2628,17:44:03.164,25.129458 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2630,17:44:03.165,25.129955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2631-2630,17:44:03.165,25.130458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2632,17:44:03.165,25.130482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2633-2632,17:44:03.167,25.132458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2634,17:44:03.168,25.132953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2635-2634,17:44:03.168,25.133458 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2636,17:44:03.168,25.133482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2637-2636,17:44:03.170,25.135458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2638,17:44:03.171,25.135953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2639-2638,17:44:03.171,25.136458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2640,17:44:03.171,25.136482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2641-2640,17:44:03.173,25.138458 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2642,17:44:03.174,25.138957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2643-2642,17:44:03.174,25.139458 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2644,17:44:03.174,25.139482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2645-2644,17:44:03.176,25.141457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2646,17:44:03.177,25.141953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2647-2646,17:44:03.177,25.142457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2648,17:44:03.177,25.142481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2649-2648,17:44:03.179,25.144459 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2650,17:44:03.180,25.144952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2651-2650,17:44:03.180,25.145457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2652,17:44:03.180,25.145481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2653-2652,17:44:03.182,25.147457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2654,17:44:03.183,25.147953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2655-2654,17:44:03.183,25.148460 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2656,17:44:03.183,25.148484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2657-2656,17:44:03.185,25.150458 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2658,17:44:03.186,25.150956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2659-2658,17:44:03.186,25.151458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2660,17:44:03.186,25.151482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2661-2660,17:44:03.188,25.153457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2662,17:44:03.189,25.153953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2663-2662,17:44:03.189,25.154457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2664,17:44:03.189,25.154482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2665-2664,17:44:03.191,25.156457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2666,17:44:03.192,25.156953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2667-2666,17:44:03.192,25.157457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2668,17:44:03.192,25.157480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2669-2668,17:44:03.194,25.159457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2670,17:44:03.195,25.159953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2671-2670,17:44:03.195,25.160457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2672,17:44:03.195,25.160480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2673-2672,17:44:03.197,25.162460 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2674,17:44:03.198,25.162953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2675-2674,17:44:03.198,25.163457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2676,17:44:03.198,25.163480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2677-2676,17:44:03.200,25.165457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2678,17:44:03.201,25.165953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2679-2678,17:44:03.201,25.166457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2680,17:44:03.201,25.166481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2681-2680,17:44:03.203,25.168457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2682,17:44:03.204,25.168956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2683-2682,17:44:03.204,25.169458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2684,17:44:03.204,25.169482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2685-2684,17:44:03.206,25.171457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2686,17:44:03.207,25.171955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2687-2686,17:44:03.207,25.172456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2688,17:44:03.207,25.172480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2689-2688,17:44:03.209,25.174458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2690,17:44:03.210,25.174954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2691-2690,17:44:03.210,25.175457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2692,17:44:03.210,25.175482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2693-2692,17:44:03.212,25.177458 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2694,17:44:03.213,25.177957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2695-2694,17:44:03.213,25.178458 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2696,17:44:03.213,25.178481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2697-2696,17:44:03.215,25.180459 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2698,17:44:03.216,25.180956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2699-2698,17:44:03.216,25.181457 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2700,17:44:03.216,25.181481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2701-2700,17:44:03.218,25.183457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2702,17:44:03.219,25.183955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2703-2702,17:44:03.219,25.184457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2704,17:44:03.219,25.184481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2705-2704,17:44:03.221,25.186457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2706,17:44:03.222,25.186954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2707-2706,17:44:03.222,25.187456 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2708,17:44:03.222,25.187480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2709-2708,17:44:03.224,25.189457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2710,17:44:03.225,25.189958 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2711-2710,17:44:03.225,25.190456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2712,17:44:03.225,25.190481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2713-2712,17:44:03.227,25.192457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2714,17:44:03.228,25.192955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2715-2714,17:44:03.228,25.193456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2716,17:44:03.228,25.193480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2717-2716,17:44:03.230,25.195456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2718,17:44:03.231,25.195955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2719-2718,17:44:03.231,25.196459 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2720,17:44:03.231,25.196483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2721-2720,17:44:03.233,25.198457 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2722,17:44:03.234,25.198955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2723-2722,17:44:03.234,25.199457 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2724,17:44:03.234,25.199481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2725-2724,17:44:03.236,25.201456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2726,17:44:03.237,25.201954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2727-2726,17:44:03.237,25.202456 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2728,17:44:03.237,25.202481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2729-2728,17:44:03.239,25.204456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2730,17:44:03.240,25.204956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2731-2730,17:44:03.240,25.205456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2732,17:44:03.240,25.205479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2733-2732,17:44:03.242,25.207457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2734,17:44:03.243,25.207955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2735-2734,17:44:03.243,25.208456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2736,17:44:03.243,25.208479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2737-2736,17:44:03.245,25.210459 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2738,17:44:03.246,25.210958 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2739-2738,17:44:03.246,25.211456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2740,17:44:03.246,25.211480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2741-2740,17:44:03.248,25.213456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2742,17:44:03.249,25.213955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2743-2742,17:44:03.249,25.214457 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2744,17:44:03.249,25.214480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2745-2744,17:44:03.251,25.216456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2746,17:44:03.252,25.216957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2747-2746,17:44:03.252,25.217456 s,499 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2748,17:44:03.252,25.217480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2749-2748,17:44:03.254,25.219456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2750,17:44:03.255,25.219955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2751-2750,17:44:03.255,25.220455 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2752,17:44:03.255,25.220479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2753-2752,17:44:03.257,25.222457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2754,17:44:03.258,25.222957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2755-2754,17:44:03.258,25.223456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2756,17:44:03.258,25.223479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2757-2756,17:44:03.260,25.225457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2758,17:44:03.261,25.225955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2759-2758,17:44:03.261,25.226456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2760,17:44:03.261,25.226479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2761-2760,17:44:03.263,25.228456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2762,17:44:03.264,25.228957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2763-2762,17:44:03.264,25.229456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2764,17:44:03.264,25.229480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2765-2764,17:44:03.266,25.231456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2766,17:44:03.267,25.231956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2767-2766,17:44:03.267,25.232494 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2768,17:44:03.267,25.232518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2769-2768,17:44:03.269,25.234456 s,1.938 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2770,17:44:03.270,25.234955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2771-2770,17:44:03.270,25.235455 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2772,17:44:03.270,25.235478 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2773-2772,17:44:03.272,25.237456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2774,17:44:03.273,25.237956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2775-2774,17:44:03.273,25.238456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2776,17:44:03.273,25.238479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2777-2776,17:44:03.275,25.240457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2778,17:44:03.276,25.240956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2779-2778,17:44:03.276,25.241456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2780,17:44:03.276,25.241479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2781-2780,17:44:03.278,25.243459 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2782,17:44:03.279,25.243965 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2783-2782,17:44:03.279,25.244458 s,492 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2784,17:44:03.279,25.244483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2785-2784,17:44:03.281,25.246455 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2786,17:44:03.282,25.246957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2787-2786,17:44:03.282,25.247456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2788,17:44:03.282,25.247480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2789-2788,17:44:03.284,25.249456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2790,17:44:03.285,25.249961 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2791-2790,17:44:03.285,25.250455 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2792,17:44:03.285,25.250480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2793-2792,17:44:03.287,25.252455 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2794,17:44:03.288,25.252957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2795-2794,17:44:03.288,25.253455 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2796,17:44:03.288,25.253479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2797-2796,17:44:03.290,25.255456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2798,17:44:03.291,25.255961 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2799-2798,17:44:03.291,25.256455 s,495 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2800,17:44:03.291,25.256479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2801-2800,17:44:03.293,25.258459 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2802,17:44:03.493,25.457998 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2803-2802,17:44:03.494,25.459467 s,1.469 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2804,17:44:03.494,25.459504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2805-2804,17:44:03.496,25.461453 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2806,17:44:03.696,25.661009 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2807-2806,17:44:03.696,25.661459 s,450 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2808,17:44:03.696,25.661497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2809-2808,17:44:03.698,25.663451 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2810,17:44:03.898,25.863006 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2811-2810,17:44:03.899,25.864456 s,1.450 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2812,17:44:03.899,25.864490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2813-2812,17:44:03.901,25.866445 s,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2814,17:44:04.101,26.066042 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2815-2814,17:44:04.102,26.067440 s,1.397 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2816,17:44:04.102,26.067484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2817-2816,17:44:04.104,26.069440 s,1.957 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2818,17:44:04.304,26.269024 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2819-2818,17:44:04.305,26.270456 s,1.432 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2820,17:44:04.305,26.270494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2821-2820,17:44:04.307,26.272438 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2822,17:44:04.507,26.472043 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2823-2822,17:44:04.508,26.473433 s,1.390 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2824,17:44:04.508,26.473470 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2825-2824,17:44:04.510,26.475432 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2826,17:44:04.710,26.675053 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2827-2826,17:44:04.711,26.676426 s,1.373 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2828,17:44:04.711,26.676465 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2829-2828,17:44:04.713,26.678449 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2830,17:44:04.913,26.878041 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2831-2830,17:44:04.914,26.879423 s,1.382 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2832,17:44:04.914,26.879458 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2833-2832,17:44:04.916,26.881424 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2834,17:44:05.116,27.081075 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2835-2834,17:44:05.117,27.082449 s,1.373 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2836,17:44:05.117,27.082493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2837-2836,17:44:05.119,27.084422 s,1.929 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2838,17:44:05.319,27.284059 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2839-2838,17:44:05.319,27.284430 s,371 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2840,17:44:05.319,27.284465 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2841-2840,17:44:05.321,27.286417 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2842,17:44:05.521,27.486126 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2843-2842,17:44:05.522,27.487435 s,1.309 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2844,17:44:05.522,27.487488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2845-2844,17:44:05.524,27.489414 s,1.926 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2846,17:44:05.724,27.689111 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2847-2846,17:44:05.725,27.690425 s,1.314 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2848,17:44:05.725,27.690467 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2849-2848,17:44:05.727,27.692411 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2850,17:44:05.927,27.892084 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2851-2850,17:44:05.928,27.893411 s,1.327 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2852,17:44:05.928,27.893445 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2853-2852,17:44:05.930,27.895406 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2854,17:44:06.131,28.095131 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2855-2854,17:44:06.132,28.096402 s,1.271 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2856,17:44:06.132,28.096451 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2857-2856,17:44:06.134,28.098399 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2858,17:44:06.334,28.298115 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2859-2858,17:44:06.335,28.299412 s,1.297 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2860,17:44:06.335,28.299450 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2861-2860,17:44:06.337,28.301397 s,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2862,17:44:06.537,28.501282 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2863-2862,17:44:06.538,28.502510 s,1.228 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2864,17:44:06.538,28.502566 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2865-2864,17:44:06.540,28.504400 s,1.834 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2866,17:44:06.740,28.704127 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2867-2866,17:44:06.741,28.705415 s,1.288 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2868,17:44:06.741,28.705457 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2869-2868,17:44:06.743,28.707391 s,1.934 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2870,17:44:06.943,28.907119 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2871-2870,17:44:06.944,28.908393 s,1.273 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2872,17:44:06.944,28.908424 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2873-2872,17:44:06.946,28.910386 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2874,17:44:07.146,29.110143 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2875-2874,17:44:07.147,29.111401 s,1.257 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2876,17:44:07.147,29.111438 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2877-2876,17:44:07.149,29.113382 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2878,17:44:07.349,29.313134 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2879-2878,17:44:07.350,29.314382 s,1.248 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2880,17:44:07.350,29.314413 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2881-2880,17:44:07.352,29.316383 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2882,17:44:07.552,29.516148 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2883-2882,17:44:07.552,29.516414 s,266 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2884,17:44:07.552,29.516463 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2885-2884,17:44:07.554,29.518450 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2886,17:44:07.754,29.718162 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2887-2886,17:44:07.755,29.719393 s,1.231 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success)\r
+URB,2888,17:44:07.755,29.719435 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2889-2888,17:44:07.757,29.721372 s,1.937 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2890,17:44:07.957,29.921162 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2891-2890,17:44:07.958,29.922380 s,1.217 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,2892,17:44:07.958,29.922416 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2893-2892,17:44:07.960,29.924364 s,1.948 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2894,17:44:08.160,30.124182 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2895-2894,17:44:08.160,30.124382 s,200 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success)\r
+URB,2896,17:44:08.160,30.124421 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2897-2896,17:44:08.162,30.126362 s,1.941 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2898,17:44:08.362,30.326171 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2899-2898,17:44:08.363,30.327364 s,1.193 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success)\r
+URB,2900,17:44:08.363,30.327396 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2901-2900,17:44:08.365,30.329357 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2902,17:44:08.565,30.529243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2903-2902,17:44:08.566,30.530370 s,1.128 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success)\r
+URB,2904,17:44:08.566,30.530416 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2905-2904,17:44:08.568,30.532354 s,1.939 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2906,17:44:08.768,30.732226 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2907-2906,17:44:08.769,30.733354 s,1.128 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,2908,17:44:08.769,30.733390 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2909-2908,17:44:08.771,30.735349 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2910,17:44:08.971,30.935204 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2911-2910,17:44:08.972,30.936358 s,1.153 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,2912,17:44:08.972,30.936394 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2913-2912,17:44:08.974,30.938344 s,1.951 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2914,17:44:09.174,31.138386 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2915-2914,17:44:09.176,31.140614 s,2.228 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2916,17:44:09.176,31.141138 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2917-2916,17:44:09.178,31.142377 s,1.239 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2918,17:44:09.378,31.342234 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2919-2918,17:44:09.379,31.343364 s,1.130 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2920,17:44:09.379,31.343409 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2921-2920,17:44:09.381,31.345338 s,1.929 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2922,17:44:09.581,31.545238 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2923-2922,17:44:09.582,31.546405 s,1.167 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2924,17:44:09.582,31.546476 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2925-2924,17:44:09.584,31.548397 s,1.921 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2926,17:44:09.784,31.748253 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2927-2926,17:44:09.785,31.749373 s,1.120 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2928,17:44:09.785,31.749432 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2929-2928,17:44:09.787,31.751333 s,1.901 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2930,17:44:09.987,31.951274 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2931-2930,17:44:09.989,31.953326 s,2.052 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2932,17:44:09.989,31.953367 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2933-2932,17:44:09.991,31.955325 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2934,17:44:10.191,32.155260 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2935-2934,17:44:10.192,32.156329 s,1.070 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2936,17:44:10.192,32.156369 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2937-2936,17:44:10.194,32.158322 s,1.953 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2938,17:44:10.394,32.358247 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2939-2938,17:44:10.395,32.359313 s,1.066 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2940,17:44:10.395,32.359348 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2941-2940,17:44:10.397,32.361314 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2942,17:44:10.597,32.561287 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2943-2942,17:44:10.599,32.563314 s,2.027 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2944,17:44:10.599,32.563356 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2945-2944,17:44:10.601,32.565313 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2946,17:44:10.801,32.765267 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2947-2946,17:44:10.802,32.766328 s,1.061 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2948,17:44:10.802,32.766362 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2949-2948,17:44:10.804,32.768308 s,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2950,17:44:11.004,32.968270 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2951-2950,17:44:11.006,32.970303 s,2.033 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2952,17:44:11.006,32.970338 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2953-2952,17:44:11.008,32.972304 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2954,17:44:11.208,33.172295 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2955-2954,17:44:11.210,33.174324 s,2.029 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2956,17:44:11.210,33.174368 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2957-2956,17:44:11.212,33.176304 s,1.936 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2958,17:44:11.412,33.376288 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2959-2958,17:44:11.414,33.378296 s,2.008 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2960,17:44:11.414,33.378329 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2961-2960,17:44:11.416,33.380306 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2962,17:44:11.616,33.580321 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2963-2962,17:44:11.618,33.582321 s,2.000 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2964,17:44:11.618,33.582364 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2965-2964,17:44:11.620,33.584295 s,1.931 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2966,17:44:11.820,33.784305 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2967-2966,17:44:11.822,33.786293 s,1.988 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2968,17:44:11.822,33.786326 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2969-2968,17:44:11.824,33.788296 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2970,17:44:12.024,33.988313 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2971-2970,17:44:12.026,33.990287 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2972,17:44:12.026,33.990323 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2973-2972,17:44:12.028,33.992287 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2974,17:44:12.228,34.192334 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2975-2974,17:44:12.230,34.194289 s,1.955 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2976,17:44:12.230,34.194328 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2977-2976,17:44:12.232,34.196282 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2978,17:44:12.432,34.396337 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2979-2978,17:44:12.433,34.398278 s,1.941 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2980,17:44:12.434,34.398314 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2981-2980,17:44:12.435,34.400277 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2982,17:44:12.636,34.600355 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2983-2982,17:44:12.637,34.602271 s,1.917 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2984,17:44:12.638,34.602318 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2985-2984,17:44:12.639,34.604272 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2986,17:44:12.840,34.804346 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2987-2986,17:44:12.841,34.806287 s,1.941 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2988,17:44:12.842,34.806326 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2989-2988,17:44:12.843,34.808271 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2990,17:44:13.043,35.007405 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2991-2990,17:44:13.044,35.009268 s,1.863 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success)\r
+URB,2992,17:44:13.045,35.009318 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2993-2992,17:44:13.046,35.011270 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2994,17:44:13.247,35.211376 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2995-2994,17:44:13.248,35.213259 s,1.883 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,2996,17:44:13.248,35.213297 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,2997-2996,17:44:13.249,35.214282 s,985 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,2998,17:44:13.449,35.413373 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,2999-2998,17:44:13.450,35.415252 s,1.879 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,3000,17:44:13.450,35.415287 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3001-3000,17:44:13.452,35.417254 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3002,17:44:13.652,35.616388 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3003-3002,17:44:13.653,35.618251 s,1.864 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,3004,17:44:13.653,35.618291 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3005-3004,17:44:13.655,35.620252 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3006,17:44:13.855,35.819381 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3007-3006,17:44:13.856,35.821251 s,1.869 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,3008,17:44:13.856,35.821283 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3009-3008,17:44:13.858,35.823249 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3010,17:44:14.058,36.022442 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3011-3010,17:44:14.059,36.024267 s,1.826 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,3012,17:44:14.059,36.024319 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3013-3012,17:44:14.061,36.026260 s,1.941 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3014,17:44:14.261,36.225411 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3015-3014,17:44:14.262,36.227242 s,1.831 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,3016,17:44:14.262,36.227285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3017-3016,17:44:14.264,36.229241 s,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3018,17:44:14.464,36.428427 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3019-3018,17:44:14.465,36.430249 s,1.822 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,3020,17:44:14.465,36.430285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3021-3020,17:44:14.467,36.432237 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3022,17:44:14.667,36.631483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3023-3022,17:44:14.668,36.633340 s,1.857 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success)\r
+URB,3024,17:44:14.669,36.633598 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3025-3024,17:44:14.670,36.635238 s,1.640 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3026,17:44:14.870,36.834453 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3027-3026,17:44:14.871,36.836267 s,1.814 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3028,17:44:14.871,36.836320 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3029-3028,17:44:14.873,36.838287 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3030,17:44:15.073,37.037457 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3031-3030,17:44:15.074,37.039228 s,1.772 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3032,17:44:15.074,37.039285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3033-3032,17:44:15.076,37.041226 s,1.942 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3034,17:44:15.276,37.240460 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3035-3034,17:44:15.277,37.242230 s,1.770 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3036,17:44:15.277,37.242280 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3037-3036,17:44:15.279,37.244225 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3038,17:44:15.479,37.443460 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3039-3038,17:44:15.480,37.445219 s,1.759 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3040,17:44:15.480,37.445264 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3041-3040,17:44:15.482,37.447218 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3042,17:44:15.682,37.646461 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3043-3042,17:44:15.683,37.648213 s,1.752 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3044,17:44:15.683,37.648253 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3045-3044,17:44:15.685,37.650214 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3046,17:44:15.885,37.849462 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3047-3046,17:44:15.886,37.851209 s,1.746 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3048,17:44:15.886,37.851247 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3049-3048,17:44:15.888,37.853208 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3050,17:44:16.088,38.052541 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3051-3050,17:44:16.089,38.054228 s,1.688 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3052,17:44:16.089,38.054373 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3053-3052,17:44:16.091,38.056220 s,1.847 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3054,17:44:16.291,38.255483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3055-3054,17:44:16.292,38.257199 s,1.717 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3056,17:44:16.292,38.257234 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3057-3056,17:44:16.294,38.259200 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3058,17:44:16.494,38.458488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3059-3058,17:44:16.495,38.460196 s,1.708 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3060,17:44:16.495,38.460231 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3061-3060,17:44:16.497,38.462220 s,1.989 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3062,17:44:16.697,38.661501 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3063-3062,17:44:16.698,38.663191 s,1.690 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3064,17:44:16.698,38.663232 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3065-3064,17:44:16.700,38.665190 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+URB,3066,17:44:16.900,38.864494 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,3067-3066,17:44:16.901,38.866188 s,1.694 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success)\r
+URB,3068,17:44:16.901,38.866223 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,3069-3068,17:44:16.903,38.868189 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01\r
+\r
+This report was generated by USBlyzer http://www.usblyzer.com/\r
--- /dev/null
+. tools used for reversing under windows (all free or eval version)
+ . ST set tools package contains a working programmer (stvp)
+ . http://www.st.com/internet/com/SOFTWARE_RESOURCES/TOOL/TOOLSET/sttoolset.zip
+ . IAR latest version contains a working debugger
+ . http://www.iar.com/website1/1.0.1.0/68/1/
+ . usblyzer to snif the corresponding usb frames
+ . http://www.usblyzer.com/
+
+. Linux
+ . usb kernel module compiled with debugging enabled
+ . usbmon
+ . libusb
+
+. stm32l chip
+ . http://www.st.com/internet/mcu/product/248820.jsp
\ No newline at end of file
--- /dev/null
+USBlyzer Report\r
+\r
+Capture List\r
+\r
+Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
+START,0001,15:09:38.756,,,,,,,,,,,,\r
+Create,0002,15:12:32.934,174.174733 s,,Create,stvp.exe,,,,FFFFFA80074F4960h,,WinUsb,FFFFFA8006FD8320h,\r
+Create,0003-0002,15:12:32.935,174.174759 s,26 us,Create,stvp.exe,,,,FFFFFA80074F4960h,,WinUsb,FFFFFA8006FD8320h,Success\r
+URB,0004,15:12:32.935,174.174880 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0005-0004,15:12:32.936,174.176236 s,1.356 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0006,15:12:32.936,174.176269 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0007-0006,15:12:32.938,174.178222 s,1.953 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),23 80 83 04 48 37\r
+URB,0008,15:12:32.938,174.178249 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0009-0008,15:12:32.939,174.179221 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0010,15:12:32.939,174.179239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0011-0010,15:12:32.941,174.181221 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 01\r
+URB,0012,15:12:32.941,174.181243 s,,Bulk or Interrupt Transfer,16 bytes data,F3 07 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F3 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0013-0012,15:12:32.942,174.182221 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0014,15:12:32.943,174.182760 s,,Bulk or Interrupt Transfer,16 bytes data,F2 30 A3 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 30 A3 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0015-0014,15:12:32.944,174.184221 s,1.462 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0016,15:12:32.944,174.184238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0017-0016,15:12:32.945,174.185221 s,982 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0018,15:12:32.945,174.185242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 32 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0019-0018,15:12:32.946,174.186221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0020,15:12:32.946,174.186239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0021-0020,15:12:32.948,174.188221 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0022,15:12:32.948,174.188240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00\r
+URB,0023-0022,15:12:32.949,174.189220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0024,15:12:32.949,174.189237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0025-0024,15:12:32.951,174.191221 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0026,15:12:32.951,174.191240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0027-0026,15:12:32.952,174.192221 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0028,15:12:32.952,174.192237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0029-0028,15:12:32.953,174.193222 s,985 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 03,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 03\r
+URB,0030,15:12:32.953,174.193242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00\r
+URB,0031-0030,15:12:32.954,174.194221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0032,15:12:32.954,174.194239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0033-0032,15:12:32.956,174.196221 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0034,15:12:32.956,174.196241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0035-0034,15:12:32.957,174.197221 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0036,15:12:32.957,174.197240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0037-0036,15:12:32.959,174.199220 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 00\r
+URB,0038,15:12:32.959,174.199240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 FC ED 00 E0 01 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 FC ED 00 E0 01 00 00 00 00 00 00 00 00 00\r
+URB,0039-0038,15:12:32.960,174.200220 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0040,15:12:32.960,174.200237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0041-0040,15:12:32.961,174.201221 s,984 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0042,15:12:32.961,174.201241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 0C ED 00 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 0C ED 00 E0 04 00 FA 05 00 00 00 00 00 00\r
+URB,0043-0042,15:12:32.962,174.202220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0044,15:12:32.962,174.202237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0045-0044,15:12:32.964,174.204220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0046,15:12:32.964,174.204243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 0C ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 0C ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0047-0046,15:12:32.965,174.205221 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0048,15:12:32.965,174.205238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0049-0048,15:12:32.967,174.207220 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 00 00 05 FA,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 00 00 05 FA\r
+URB,0050,15:12:32.967,174.207239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0051-0050,15:12:32.968,174.208219 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0052,15:12:32.968,174.208236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0053-0052,15:12:32.969,174.209220 s,984 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 02,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 02\r
+URB,0054,15:12:32.969,174.209241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0055-0054,15:12:32.970,174.210220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0056,15:12:32.970,174.210237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0057-0056,15:12:32.972,174.212221 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 00\r
+URB,0058,15:12:32.972,174.212240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 FC ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 FC ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0059-0058,15:12:32.973,174.213220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0060,15:12:32.973,174.213237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0061-0060,15:12:32.975,174.215220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0062,15:12:32.975,174.215241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 31 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0063-0062,15:12:32.976,174.216220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0064,15:12:32.976,174.216238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0065-0064,15:12:32.977,174.217220 s,983 us,Bulk or Interrupt Transfer,12 bytes data,80 00 00 00 77 14 A0 2B...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 77 14 A0 2B 00 00 00 00\r
+URB,0066,15:12:32.977,174.217240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 04 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 04 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0067-0066,15:12:32.978,174.218220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0068,15:12:32.978,174.218237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0069-0068,15:12:32.980,174.220220 s,1.983 ms,Bulk or Interrupt Transfer,4 bytes data,16 64 18 10,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),16 64 18 10\r
+URB,0070,15:12:32.980,174.220240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0071-0070,15:12:32.981,174.221220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0072,15:12:32.981,174.221237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0073-0072,15:12:32.983,174.223220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0074,15:12:32.983,174.223243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 0F 00 00 00 20 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 0F 00 00 00 20 00 00 00 00 00 00 00 00 00\r
+URB,0075-0074,15:12:32.984,174.224222 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0076,15:12:32.984,174.224239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0077-0076,15:12:32.985,174.225220 s,981 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0078,15:12:32.985,174.225239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 11 00 40 00 20 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 11 00 40 00 20 00 00 00 00 00 00 00 00 00\r
+URB,0079-0078,15:12:32.986,174.226221 s,981 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0080,15:12:32.986,174.226238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0081-0080,15:12:32.988,174.228225 s,1.987 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0082,15:12:32.988,174.228257 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 10 00 00 00 01 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 10 00 00 00 01 00 00 00 00 00 00 00 00 00\r
+URB,0083-0082,15:12:32.989,174.229225 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0084,15:12:32.989,174.229243 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0085-0084,15:12:32.991,174.231221 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0086,15:12:32.991,174.231244 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 00 00 00 20 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 08 00 00 00 20 04 00 00 00 00 00 00 00 00 00\r
+URB,0087-0086,15:12:32.992,174.232221 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0088,15:12:32.992,174.232239 s,,Bulk or Interrupt Transfer,4 bytes data,55 AA 88 00,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,55 AA 88 00\r
+URB,0089-0088,15:12:32.993,174.233221 s,982 us,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0090,15:12:32.993,174.233239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0091-0090,15:12:32.994,174.234222 s,983 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0092,15:12:32.994,174.234242 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0093-0092,15:12:32.996,174.236221 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0094,15:12:32.996,174.236242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 00 00 20 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 00 00 20 04 00 00 00 00 00 00 00 00 00\r
+URB,0095-0094,15:12:32.997,174.237221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0096,15:12:32.997,174.237238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0097-0096,15:12:32.999,174.239222 s,1.984 ms,Bulk or Interrupt Transfer,4 bytes data,55 AA 88 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),55 AA 88 00\r
+URB,0098,15:12:32.999,174.239260 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0099-0098,15:12:33.000,174.240228 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0100,15:12:33.000,174.240266 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0101-0100,15:12:33.002,174.242226 s,1.960 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0102,15:12:33.002,174.242263 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 04 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 04 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0103-0102,15:12:33.003,174.243226 s,964 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0104,15:12:33.003,174.243245 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0105-0104,15:12:33.005,174.245219 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,16 64 18 10,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),16 64 18 10\r
+URB,0106,15:12:33.005,174.245240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0107-0106,15:12:33.006,174.246220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0108,15:12:33.006,174.246237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0109-0108,15:12:33.008,174.248219 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0110,15:12:33.008,174.248242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 1C 3C 02 40 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 1C 3C 02 40 04 00 00 00 00 00 00 00 00 00\r
+URB,0111-0110,15:12:33.009,174.249219 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0112,15:12:33.009,174.249236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0113-0112,15:12:33.010,174.250220 s,984 us,Bulk or Interrupt Transfer,4 bytes data,AA 00 78 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),AA 00 78 00\r
+URB,0114,15:12:33.010,174.250239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0115-0114,15:12:33.011,174.251219 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0116,15:12:33.011,174.251236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0117-0116,15:12:33.013,174.253220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0118,15:12:33.013,174.253240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 20 3C 02 40 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 20 3C 02 40 04 00 00 00 00 00 00 00 00 00\r
+URB,0119-0118,15:12:33.014,174.254220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0120,15:12:33.014,174.254239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0121-0120,15:12:33.016,174.256221 s,1.982 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00\r
+URB,0122,15:12:33.016,174.256241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0123-0122,15:12:33.017,174.257219 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0124,15:12:33.017,174.257236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0125-0124,15:12:33.018,174.258220 s,984 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0126,15:12:33.018,174.258252 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 00 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 00 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0127-0126,15:12:33.019,174.259220 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0128,15:12:33.019,174.259241 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0129-0128,15:12:33.097,174.337240 s,77.999 ms,Bulk or Interrupt Transfer,4096 bytes data,28 06 00 20 69 58 00 08...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),28 06 00 20 69 58 00 08 91 54 00 08 93 54 00 08 95 54 00 08 97 54 00 08 99 54 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9B 54 00 08 9D 54 00 08 00 00 00 00 9F 54 00 08 A1 54 00 08 B1 58 00 08 B5 58 00 08 B9 58 00 08 75 56 00 08 C1 58 00 08 C5 58 00 08 27 56 00 08 CD 58 00 08 D1 58 00 08 D5 58 00 08 D9 58 00 08 DD 58 00 08 E1 58 00 08 E5 58 00 08 E9 58 00 08 ED 58 00 08 F1 58 00 08 F5 58 00 08 F9 58 00 08 FD 58 00 08 01 59 00 08 05 59 00 08 09 59 00 08 0D 59 00 08 11 59 00 08 15 59 00 08 19 59 00 08 1D 59 00 08 21 59 00 08 25 59 00 08 29 59 00 08 2D 59 00 08 31 59 00 08 35 59 00 08 39 59 00 08 3D 59 00 08 41 59 00 08 45 59 00 08 49 59 00 08 4D 59 00 08 51 59 00 08 55 59 00 08 59 59 00 08 5D 59 00 08 61 59 00 08 10 B5 84 B0 20 20 AD F8 00 00 AD F8\r
+URB,0130,15:12:33.097,174.337275 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0131-0130,15:12:33.099,174.339219 s,1.944 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0132,15:12:33.099,174.339238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0133-0132,15:12:33.101,174.341218 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0134,15:12:33.103,174.343580 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 10 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 10 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0135-0134,15:12:33.105,174.345221 s,1.641 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0136,15:12:33.105,174.345247 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0137-0136,15:12:33.183,174.423249 s,78.002 ms,Bulk or Interrupt Transfer,4096 bytes data,01 01 43 EA 81 31 11 43...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),01 01 43 EA 81 31 11 43 81 61 FF F7 CC FD 01 F0 A4 FD 31 BD 38 B5 04 46 01 25 07 E0 2B 46 00 22 11 46 20 46 FF F7 44 FE 64 1C 6D 1C 20 78 00 28 02 D0 ED B2 08 2D F1 D3 31 BD 38 B5 04 46 01 25 06 E0 00 22 11 46 00 A8 FF F7 32 FE A4 1C 6D 1C 20 88 00 28 1B D0 ED B2 08 2D 18 D2 8D F8 00 00 20 88 00 F4 70 40 B0 F5 80 4F 09 D0 B0 F5 00 4F 2B 46 E6 D1 00 22 01 21 00 A8 FF F7 19 FE E5 E7 2B 46 01 22 00 21 00 A8 FF F7 12 FE DE E7 31 BD 80 B5 04 20 01 F0 65 FD 00 28 FA D1 00 20 3F 49 02 46 02 E0 41 F8 20 20 40 1C 10 28 FA D3 BD E8 01 40 01 F0 52 BD 2D E9 F0 43 83 B0 05 46 0E 46 14 46 00 A8 07 21 01 F0 BB FD 00 2D 5E D0 28 46 00 27 02 E0 7F 1C FF B2 40 1C 01 78 00 29 F9 D1 28 46 FF F7 97 FF 20 46 00 F0 87 FB 4F F0 00 08 0A E0 20 46 00 F0 81 FB 09 F1 01 09 5F FA 89 F9\r
+URB,0138,15:12:33.183,174.423297 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0139-0138,15:12:33.185,174.425217 s,1.920 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0140,15:12:33.185,174.425240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0141-0140,15:12:33.187,174.427221 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0142,15:12:33.189,174.428964 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0143-0142,15:12:33.190,174.430218 s,1.254 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0144,15:12:33.190,174.430240 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0145-0144,15:12:33.268,174.508249 s,78.008 ms,Bulk or Interrupt Transfer,4096 bytes data,0A 98 78 60 0C 98 F8 60...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),0A 98 78 60 0C 98 F8 60 0E 98 78 61 0D 98 38 61 FF F7 B1 FA 4F F4 00 60 00 F0 6F FE 00 20 00 F0 86 FE 00 20 00 F0 5B FE 00 20 00 F0 6D F8 FF F7 7F FD 01 20 00 F0 1D FF 01 20 00 F0 16 FE FE F7 7D FD 01 20 20 70 40 46 10 B0 BD E8 F0 81 00 00 18 ED 00 E0 00 E4 00 E0 10 E0 00 E0 34 01 00 20 00 00 02 40 00 04 02 40 00 08 02 40 00 0C 02 40 00 10 02 40 00 14 02 40 00 24 01 40 1C 38 02 40 22 02 00 20 23 02 00 20 10 B5 04 00 06 D0 01 2C 04 D0 B5 21 0F F2 00 20 FF F7 DC FB DF F8 C0 01 01 68 49 08 54 EA 41 01 01 60 10 BD 10 B5 04 00 06 D0 01 2C 04 D0 CB 21 0F F2 DC 10 FF F7 CA FB DF F8 9C 01 00 2C 01 68 03 D0 41 F0 02 01 01 60 10 BD 21 F0 02 01 01 60 10 BD 10 B5 04 00 06 D0 01 2C 04 D0 E6 21 0F F2 B0 10 FF F7 B3 FB DF F8 70 01 00 2C 01 68 03 D0 41 F0 04 01 01 60 10 BD\r
+URB,0146,15:12:33.268,174.508317 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0147-0146,15:12:33.270,174.510218 s,1.900 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0148,15:12:33.270,174.510240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0149-0148,15:12:33.272,174.512259 s,2.019 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0150,15:12:33.274,174.514519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 30 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 30 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0151-0150,15:12:33.275,174.515232 s,712 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0152,15:12:33.275,174.515266 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0153-0152,15:12:33.353,174.593260 s,77.994 ms,Bulk or Interrupt Transfer,4096 bytes data,04 60 10 BD 10 B5 04 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),04 60 10 BD 10 B5 04 00 09 D0 01 2C 07 D0 05 2C 05 D0 40 F2 BD 11 0F F2 78 40 FE F7 1B FC DF F8 28 04 00 21 01 70 04 70 10 BD 10 B5 04 00 07 D0 01 2C 05 D0 40 F2 D5 11 0F F2 54 40 FE F7 0A FC DF F8 08 04 04 60 10 BD 10 B5 04 00 0B D0 01 2C 09 D0 02 2C 07 D0 03 2C 05 D0 40 F2 B7 21 0F F2 30 40 FE F7 F7 FB DF F8 E8 03 01 68 89 08 54 EA 81 01 01 60 10 BD DF F8 D8 03 00 68 00 F0 0C 00 70 47 10 B5 04 00 15 D0 80 2C 13 D0 90 2C 11 D0 A0 2C 0F D0 B0 2C 0D D0 C0 2C 0B D0 D0 2C 09 D0 E0 2C 07 D0 F0 2C 05 D0 40 F2 ED 21 0F F2 E0 30 FE F7 D0 FB DF F8 98 03 01 68 21 F0 F0 01 21 43 01 60 10 BD 10 B5 04 00 11 D0 B4 F5 80 6F 0E D0 B4 F5 A0 6F 0B D0 B4 F5 C0 6F 08 D0 B4 F5 E0 6F 05 D0 4F F4 43 71 0F F2 A8 30 FE F7 B3 FB DF F8 60 03 01 68 21 F4 E0 61 21 43 01 60 10 BD 10 B5\r
+URB,0154,15:12:33.353,174.593333 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0155-0154,15:12:33.355,174.595215 s,1.882 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0156,15:12:33.355,174.595238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0157-0156,15:12:33.357,174.597214 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0158,15:12:33.359,174.599172 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 40 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 40 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0159-0158,15:12:33.360,174.600219 s,1.047 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0160,15:12:33.360,174.600245 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0161-0160,15:12:33.438,174.678234 s,77.989 ms,Bulk or Interrupt Transfer,4096 bytes data,B8 F1 04 0F 0E D0 B8 F1...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),B8 F1 04 0F 0E D0 B8 F1 05 0F 0B D0 B8 F1 06 0F 08 D0 B8 F1 07 0F 05 D0 40 F2 FF 21 0F F2 8C 10 FD F7 18 FC 07 21 14 2D 0B D3 E0 68 A5 F1 14 02 02 EB 42 02 91 40 88 43 08 FA 02 F1 08 43 E0 60 16 E0 0A 2D 0B D3 20 69 A5 F1 0A 02 02 EB 42 02 91 40 88 43 08 FA 02 F1 08 43 20 61 08 E0 60 69 05 EB 45 02 91 40 88 43 08 FA 02 F1 08 43 60 61 1F 21 07 2E 09 D2 20 6C 07 EB 87 02 91 40 88 43 05 FA 02 F1 08 43 20 64 33 E0 0D 2E 0A D2 E0 6B F2 1F 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 E0 63 26 E0 13 2E 0B D2 A0 6B A6 F1 0D 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 A0 63 18 E0 19 2E 0B D2 60 6B A6 F1 13 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 60 63 0A E0 20 6B A6 F1 19 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 20 63 BD E8 F0 81 10 B5 04 46 DF F8 3C 00 84 42\r
+URB,0162,15:12:33.438,174.678274 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0163-0162,15:12:33.440,174.680211 s,1.937 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0164,15:12:33.440,174.680231 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0165-0164,15:12:33.441,174.681211 s,980 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0166,15:12:33.443,174.682929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 50 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 50 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0167-0166,15:12:33.443,174.683214 s,285 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0168,15:12:33.443,174.683237 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0169-0168,15:12:33.521,174.761232 s,77.994 ms,Bulk or Interrupt Transfer,4096 bytes data,41 02 08 4B 1B 68 03 EB...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),41 02 08 4B 1B 68 03 EB 42 02 52 89 96 3A 41 F2 F3 23 92 B2 9A 42 ED D3 FF 20 70 47 00 20 70 47 95 01 00 20 10 02 00 20 B8 01 00 20 24 02 00 20 30 01 00 20 F8 01 00 20 58 58 00 08 60 58 00 08 B0 01 00 20 A8 01 00 20 18 02 00 20 97 01 00 20 98 01 00 20 1A 02 00 20 1C 02 00 20 1E 02 00 20 84 58 00 08 00 01 00 08 00 02 00 00 00 00 A0 FF A0 00 20 00 00 00 60 FF 20 FF 60 00 00 00 00 00 10 B5 08 4C 00 20 20 83 01 20 00 F0 D8 F8 01 00 02 D0 20 8B 08 43 20 83 20 8B 00 28 01 D0 FF F7 61 FA 10 BD DC 01 00 20 2D E9 F8 4F 01 20 80 F3 10 88 DF F8 84 03 DF F8 84 13 02 68 0A 60 00 21 01 60 08 46 80 F3 10 88 DF F8 74 43 DF F8 74 B3 DF F8 74 63 DF F8 64 03 00 68 41 1E DF F8 5C 23 11 60 00 28 00 F0 A9 80 DF F8 60 73 38 78 40 1E 38 70 DF F8 5C 03 01 78 49 1E 01 70 C9 B2 00 29\r
+URB,0170,15:12:33.521,174.761271 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0171-0170,15:12:33.523,174.763211 s,1.940 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0172,15:12:33.523,174.763233 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0173-0172,15:12:33.525,174.765209 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0174,15:12:33.527,174.766919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 60 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 60 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0175-0174,15:12:33.528,174.768211 s,1.291 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0176,15:12:33.528,174.768234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0177-0176,15:12:33.604,174.844240 s,76.007 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0178,15:12:33.604,174.844301 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0179-0178,15:12:33.606,174.846214 s,1.913 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0180,15:12:33.606,174.846234 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0181-0180,15:12:33.608,174.848208 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0182,15:12:33.610,174.849977 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 70 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 70 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0183-0182,15:12:33.610,174.850213 s,236 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0184,15:12:33.610,174.850235 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0185-0184,15:12:33.687,174.927228 s,76.993 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0186,15:12:33.687,174.927268 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0187-0186,15:12:33.689,174.929206 s,1.939 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0188,15:12:33.689,174.929226 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0189-0188,15:12:33.690,174.930206 s,980 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0190,15:12:33.692,174.932148 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 80 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 80 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0191-0190,15:12:33.693,174.933211 s,1.062 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0192,15:12:33.693,174.933237 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0193-0192,15:12:33.769,175.009241 s,76.004 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0194,15:12:33.769,175.009307 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0195-0194,15:12:33.771,175.011249 s,1.942 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0196,15:12:33.771,175.011349 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0197-0196,15:12:33.773,175.013221 s,1.872 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0198,15:12:33.775,175.015272 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 90 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 90 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0199-0198,15:12:33.777,175.017218 s,1.946 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0200,15:12:33.777,175.017254 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0201-0200,15:12:33.853,175.093245 s,75.991 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0202,15:12:33.853,175.093309 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0203-0202,15:12:33.855,175.095204 s,1.895 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0204,15:12:33.855,175.095227 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0205-0204,15:12:33.857,175.097203 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0206,15:12:33.859,175.098972 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 A0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 A0 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0207-0206,15:12:33.859,175.099209 s,237 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0208,15:12:33.859,175.099233 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0209-0208,15:12:33.936,175.176223 s,76.990 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0210,15:12:33.936,175.176266 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0211-0210,15:12:33.938,175.178203 s,1.937 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0212,15:12:33.938,175.178223 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0213-0212,15:12:33.940,175.180202 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0214,15:12:33.942,175.181915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 B0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 B0 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0215-0214,15:12:33.943,175.183205 s,1.291 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0216,15:12:33.943,175.183234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0217-0216,15:12:34.019,175.259226 s,75.993 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0218,15:12:34.019,175.259275 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0219-0218,15:12:34.021,175.261201 s,1.926 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0220,15:12:34.021,175.261221 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0221-0220,15:12:34.023,175.263200 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0222,15:12:34.025,175.265126 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 C0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 C0 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0223-0222,15:12:34.026,175.266209 s,1.083 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0224,15:12:34.026,175.266234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0225-0224,15:12:34.102,175.342223 s,75.989 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0226,15:12:34.102,175.342270 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0227-0226,15:12:34.104,175.344199 s,1.929 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0228,15:12:34.104,175.344219 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0229-0228,15:12:34.105,175.345202 s,983 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0230,15:12:34.107,175.346917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 D0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 D0 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0231-0230,15:12:34.107,175.347202 s,285 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0232,15:12:34.107,175.347225 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0233-0232,15:12:34.184,175.424221 s,76.996 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0234,15:12:34.184,175.424272 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0235-0234,15:12:34.186,175.426198 s,1.926 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0236,15:12:34.186,175.426219 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0237-0236,15:12:34.188,175.428197 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0238,15:12:34.190,175.429912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 E0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 E0 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0239-0238,15:12:34.191,175.431198 s,1.286 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0240,15:12:34.191,175.431220 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0241-0240,15:12:34.267,175.507225 s,76.005 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0242,15:12:34.267,175.507282 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0243-0242,15:12:34.269,175.509198 s,1.916 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success)\r
+URB,0244,15:12:34.269,175.509228 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0245-0244,15:12:34.271,175.511235 s,2.007 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+URB,0246,15:12:34.274,175.513803 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 F0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,,F2 07 00 F0 00 08 00 10 00 00 00 00 00 00 00 00\r
+URB,0247-0246,15:12:34.274,175.514220 s,417 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,Success (Success)\r
+URB,0248,15:12:34.274,175.514296 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0249-0248,15:12:34.351,175.591234 s,76.938 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0250,15:12:34.351,175.591304 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0251-0250,15:12:34.353,175.593195 s,1.891 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,Success (Success)\r
+URB,0252,15:12:34.353,175.593216 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,\r
+URB,0253-0252,15:12:34.354,175.594194 s,978 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00\r
+\r
+This report was generated by USBlyzer http://www.usblyzer.com/\r
--- /dev/null
+USBlyzer Report\r
+\r
+Capture List\r
+\r
+Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status\r
+START,0001,17:41:03.981,,,,,,,,,,,,\r
+URB,0002,17:41:09.226,5.245187 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0003-0002,17:41:09.227,5.246467 s,1.280 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0004,17:41:09.227,5.246524 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0005-0004,17:41:09.229,5.248463 s,1.939 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
+URB,0006,17:41:09.229,5.248519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0007-0006,17:41:09.230,5.249462 s,943 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0008,17:41:09.230,5.249491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0009-0008,17:41:09.232,5.251472 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0010,17:41:09.232,5.251514 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0011-0010,17:41:09.233,5.252465 s,951 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0012,17:41:09.233,5.252495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0013-0012,17:41:09.235,5.254462 s,1.967 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
+URB,0014,17:41:09.235,5.254493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0015-0014,17:41:09.236,5.255462 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0016,17:41:09.236,5.255498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0017-0016,17:41:09.238,5.257465 s,1.967 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0018,17:41:09.238,5.257575 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 36 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 36 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0019-0018,17:41:09.239,5.258462 s,887 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0020,17:41:09.239,5.258490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0021-0020,17:41:09.241,5.260462 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,05 4A,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),05 4A\r
+URB,0022,17:41:09.241,5.260493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0023-0022,17:41:09.242,5.261461 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0024,17:41:09.242,5.261486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0025-0024,17:41:09.244,5.263461 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0026,17:41:09.244,5.263495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0027-0026,17:41:09.245,5.264470 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0028,17:41:09.245,5.264534 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0029-0028,17:41:09.247,5.266457 s,1.923 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
+URB,0030,17:41:09.247,5.266509 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0031-0030,17:41:09.248,5.267458 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0032,17:41:09.248,5.267484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0033-0032,17:41:09.250,5.269465 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0034,17:41:09.250,5.269495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0035-0034,17:41:09.251,5.270461 s,966 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0036,17:41:09.251,5.270485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 01\r
+URB,0037-0036,17:41:09.253,5.272462 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0038,17:41:09.253,5.272486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0039-0038,17:41:09.255,5.274460 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0040,17:41:09.255,5.274484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0041-0040,17:41:09.257,5.276460 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0042,17:41:09.257,5.276493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0043-0042,17:41:09.258,5.277460 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0044,17:41:09.258,5.277485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0045-0044,17:41:09.260,5.279461 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0046,17:41:09.260,5.279486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0047-0046,17:41:09.262,5.281461 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0048,17:41:09.262,5.281488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0049-0048,17:41:09.264,5.283461 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0050,17:41:09.264,5.283491 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0051-0050,17:41:09.265,5.284460 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0052,17:41:09.265,5.284484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0053-0052,17:41:09.267,5.286461 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0054,17:41:09.267,5.286485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0055-0054,17:41:09.269,5.288460 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0056,17:41:09.269,5.288485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0057-0056,17:41:09.271,5.290460 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0058,17:41:09.271,5.290487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0059-0058,17:41:09.272,5.291462 s,976 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0060,17:41:09.272,5.291486 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0061-0060,17:41:09.274,5.293460 s,1.974 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0062,17:41:09.274,5.293485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0063-0062,17:41:09.276,5.295460 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0064,17:41:09.276,5.295487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0065-0064,17:41:09.278,5.297460 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0066,17:41:09.278,5.297488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0067-0066,17:41:09.279,5.298460 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0068,17:41:09.279,5.298485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0069-0068,17:41:09.281,5.300460 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0070,17:41:09.281,5.300484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0071-0070,17:41:09.283,5.302461 s,1.976 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0072,17:41:09.283,5.302485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0073-0072,17:41:09.285,5.304460 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0074,17:41:09.285,5.304502 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0075-0074,17:41:09.286,5.305459 s,957 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0076,17:41:09.286,5.305483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0077-0076,17:41:09.288,5.307460 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
+URB,0078,17:41:09.288,5.307486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0079-0078,17:41:09.289,5.308460 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0080,17:41:09.289,5.308484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0081-0080,17:41:09.291,5.310459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0082,17:41:09.291,5.310485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0D 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0D 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0083-0082,17:41:09.292,5.311460 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0084,17:41:09.292,5.311483 s,,Bulk or Interrupt Transfer,2 bytes data,BE BE,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,BE BE\r
+URB,0085-0084,17:41:09.294,5.313462 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0086,17:41:09.294,5.313486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0087-0086,17:41:09.296,5.315460 s,1.973 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0088,17:41:09.296,5.315487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0089-0088,17:41:09.298,5.317461 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0090,17:41:09.298,5.317488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 01 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 35 F0 ED 00 E0 01 00 5F A0 00 00 00 00 00 00\r
+URB,0091-0090,17:41:09.299,5.318460 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0092,17:41:09.299,5.318484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0093-0092,17:41:09.301,5.320459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0094,17:41:09.302,5.321032 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00\r
+URB,0095-0094,17:41:09.302,5.321463 s,431 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0096,17:41:09.302,5.321490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0097-0096,17:41:09.304,5.323462 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 01\r
+URB,0098,17:41:09.304,5.323500 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0D 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0D 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0099-0098,17:41:09.305,5.324460 s,960 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0100,17:41:09.305,5.324491 s,,Bulk or Interrupt Transfer,2 bytes data,70 47,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,70 47\r
+URB,0101-0100,17:41:09.307,5.326459 s,1.968 ms,Bulk or Interrupt Transfer,2 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0102,17:41:09.307,5.326489 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0103-0102,17:41:09.309,5.328461 s,1.972 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0104,17:41:09.309,5.328488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0105-0104,17:41:09.311,5.330458 s,1.971 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0106,17:41:09.311,5.330495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 41 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0107-0106,17:41:09.312,5.331460 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0108,17:41:09.312,5.331487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0109-0108,17:41:09.314,5.333460 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0110,17:41:09.314,5.333511 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0111-0110,17:41:09.315,5.334459 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0112,17:41:09.315,5.334485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0113-0112,17:41:09.317,5.336460 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01\r
+URB,0114,17:41:09.317,5.336490 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0115-0114,17:41:09.318,5.337458 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0116,17:41:09.318,5.337484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0117-0116,17:41:09.320,5.339459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0118,17:41:09.320,5.339487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0119-0118,17:41:09.321,5.340459 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0120,17:41:09.321,5.340484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 01\r
+URB,0121-0120,17:41:09.323,5.342460 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0122,17:41:09.323,5.342484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0123-0122,17:41:09.325,5.344459 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0124,17:41:09.325,5.344483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0125-0124,17:41:09.327,5.346460 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0126,17:41:09.327,5.346487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0127-0126,17:41:09.328,5.347459 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0128,17:41:09.328,5.347483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0129-0128,17:41:09.330,5.349459 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0130,17:41:09.330,5.349484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0131-0130,17:41:09.332,5.351459 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0132,17:41:09.332,5.351482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0133-0132,17:41:09.334,5.353460 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0134,17:41:09.334,5.353486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0135-0134,17:41:09.335,5.354459 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0136,17:41:09.335,5.354484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0137-0136,17:41:09.337,5.356459 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0138,17:41:09.337,5.356487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0139-0138,17:41:09.339,5.358460 s,1.972 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0140,17:41:09.339,5.358485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0141-0140,17:41:09.341,5.360459 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0142,17:41:09.341,5.360486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0143-0142,17:41:09.342,5.361458 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0144,17:41:09.342,5.361483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0145-0144,17:41:09.344,5.363461 s,1.979 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0146,17:41:09.344,5.363486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0147-0146,17:41:09.346,5.365459 s,1.973 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0148,17:41:09.346,5.365483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0149-0148,17:41:09.348,5.367459 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0150,17:41:09.348,5.367485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0151-0150,17:41:09.349,5.368459 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0152,17:41:09.349,5.368483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00\r
+URB,0153-0152,17:41:09.351,5.370458 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0154,17:41:09.351,5.370483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0155-0154,17:41:09.353,5.372460 s,1.976 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0156,17:41:09.353,5.372483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0157-0156,17:41:09.355,5.374458 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0158,17:41:09.355,5.374493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3A 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0159-0158,17:41:09.356,5.375459 s,966 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0160,17:41:09.356,5.375486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0161-0160,17:41:09.361,5.380459 s,4.973 ms,Bulk or Interrupt Transfer,64 bytes data,80 00 00 01 00 00 00 20...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 00 00 00 20 08 ED 00 E0 80 FF FF 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 19 00 20 6B 0E 00 20\r
+URB,0162,17:41:09.361,5.380468 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0163-0162,17:41:09.363,5.382453 s,1.984 ms,Bulk or Interrupt Transfer,24 bytes data,40 11 00 20 00 00 00 01...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),40 11 00 20 00 00 00 01 A0 19 00 20 00 00 00 00 00 00 00 00 01 00 00 00\r
+URB,0164,17:41:09.363,5.382485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00\r
+URB,0165-0164,17:41:09.364,5.383456 s,970 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0166,17:41:09.364,5.383480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0167-0166,17:41:09.366,5.385458 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47\r
+URB,0168,17:41:09.366,5.385484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0169-0168,17:41:09.367,5.386458 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0170,17:41:09.367,5.386482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0171-0170,17:41:09.369,5.388460 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0172,17:41:09.369,5.388623 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 04 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 04 10 00 E0 04 00 00 00 00 00 00 00 00 00\r
+URB,0173-0172,17:41:09.370,5.389462 s,839 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0174,17:41:09.370,5.389487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0175-0174,17:41:09.372,5.391459 s,1.972 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 00\r
+URB,0176,17:41:09.372,5.391485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0177-0176,17:41:09.373,5.392459 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success)\r
+URB,0178,17:41:09.373,5.392482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0179-0178,17:41:09.375,5.394458 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+URB,0180,17:41:09.386,5.405429 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 E4 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,,F2 07 E4 19 00 20 04 00 00 00 00 00 00 00 00 00\r
+URB,0181-0180,17:41:09.387,5.406464 s,1.035 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,Success (Success)\r
+URB,0182,17:41:09.387,5.406495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0183-0182,17:41:09.389,5.408458 s,1.963 ms,Bulk or Interrupt Transfer,4 bytes data,67 14 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),67 14 00 20\r
+URB,0184,17:41:09.389,5.408487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00\r
+URB,0185-0184,17:41:09.390,5.409458 s,971 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,Success (Success)\r
+URB,0186,17:41:09.390,5.409483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,\r
+URB,0187-0186,17:41:09.392,5.411458 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00\r
+\r
+This report was generated by USBlyzer http://www.usblyzer.com/\r
projects / fw / stlink / commitdiff