arm_disassembler: bugfix, MRRC instruction not recognized

A copy-and-paste error in the arm_disassembler opcode evaluation
disabled the recognition of MRRC instructions.
According to the arm architecture ref. manual issue E or later, MRRC and MCRR
instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5.
Error found by static code analysis using a semantic pattern to
detect duplicated tests xand.cocci, see coccinellery.org

Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3363
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 65086c2fdd4752d8dd5c2080b5043c0c3a29cc2a..5cec6d67aad7335f0bbac196b800bd50392f86d2 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -278,7 +278,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
        uint8_t cp_num = (opcode & 0xf00) >> 8;
 
        /* MCRR or MRRC */
-       if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000)) {
+       if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c500000)) {
                uint8_t cp_opcode, Rd, Rn, CRm;
                char *mnemonic;