There are ~900 Yoda conditions to be aligned to the coding style.
For recurrent Yoda conditions it's preferable using a trivial
script in order to minimize the review effort.
E.g. comparison of uppercase macro/enum with lowercase variable:
- ...(ERROR_OK == retval)...
+ ...(retval == ERROR_OK)...
Patch generated automatically with the command:
sed -i \
's/(\([A-Z][A-Z0-9_]*\) \([=!]=\) \([a-z][a-z0-9_]*\))/(\3 \2 \1)/g' \
$(find src/ -type f)
While there, remove the braces {} around a single statement block
to prevent warning from checkpatch.
Change-Id: If585b0a4b4578879c87b2dd74d9e0025e275ec6b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6354
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
unsigned requested;
int retval = parse_uint(name_index + 1, &requested);
/* detect parsing error by forcing past end of bank list */
- return (ERROR_OK == retval) ? requested : ~0U;
+ return (retval == ERROR_OK) ? requested : ~0U;
}
bool flash_driver_name_matches(const char *name, const char *expected)
uint32_t status;
retval = at91sam9_ecc_init(target, info);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data) {
retval = nand_read_data_page(nand, data, data_size);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
uint32_t parity, nparity;
retval = at91sam9_ecc_init(target, info);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data) {
retval = nand_write_data_page(nand, data, data_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write data to NAND device");
return retval;
}
if (!oob)
free(oob_data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write OOB data to NAND");
return retval;
}
nand->controller->address(nand, (page >> 16) & 0xff);
/* large page devices need a start command if reading */
- if (NAND_CMD_READ0 == cmd)
+ if (cmd == NAND_CMD_READ0)
nand->controller->command(nand, NAND_CMD_READSTART);
}
if (nand->controller->read_block_data != NULL)
retval = (nand->controller->read_block_data)(nand, data, size);
- if (ERROR_NAND_NO_BUFFER == retval) {
+ if (retval == ERROR_NAND_NO_BUFFER) {
uint32_t i;
int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1;
int retval;
retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data)
if (nand->controller->write_block_data != NULL)
retval = (nand->controller->write_block_data)(nand, data, size);
- if (ERROR_NAND_NO_BUFFER == retval) {
+ if (retval == ERROR_NAND_NO_BUFFER) {
bool is16bit = nand->device->options & NAND_BUSWIDTH_16;
uint32_t incr = is16bit ? 2 : 1;
uint16_t write_data;
write_data = *data;
retval = nand->controller->write_data(nand, write_data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
break;
data += incr;
return ERROR_NAND_OPERATION_TIMEOUT;
retval = nand_read_status(nand, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
int retval;
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data) {
retval = nand_write_data_page(nand, data, data_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write data to NAND device");
return retval;
}
if (oob) {
retval = nand_write_data_page(nand, oob, oob_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write OOB data to NAND device");
return retval;
}
{
for (unsigned i = 0; nand_flash_controllers[i]; i++) {
int retval = (*f)(nand_flash_controllers[i], x);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
if (NULL != filename) {
int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
- if (ERROR_OK != retval) {
- const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
+ if (retval != ERROR_OK) {
+ const char *msg = (filemode == FILEIO_READ) ? "read" : "write";
command_print(cmd, "failed to open '%s' for %s access",
filename, msg);
return retval;
struct nand_device *nand;
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (NULL == nand->device) {
}
retval = nand_fileio_start(CMD, nand, CMD_ARGV[1], filemode, state);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (!need_size) {
oob_size);
}
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* allocate a working area */
/* read always the data and also oob areas*/
retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* allocate a working area */
/* determine current SYSCLK (13'MHz or main oscillator) */
retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SYSCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* determine selected HCLK source */
retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read HCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
hclk = sysclk;
else {
retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read HCLKPLL_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read CLKDIV_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
retval = target_write_u32(target, 0x400040c8, 0x22);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set FLASHCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CEH = 0x0 (Force nCE assert) */
retval = target_write_u32(target, 0x200b804c, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CEH");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_LOCK = 0xa25e (unlock protected registers) */
retval = target_write_u32(target, 0x200b8044, 0xa25e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_LOCK");
return ERROR_NAND_OPERATION_FAILED;
}
if (bus_width == 16)
mlc_icr_value |= 0x1;
retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ICR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_LOCK = 0xa25e (unlock protected registers) */
retval = target_write_u32(target, 0x200b8044, 0xa25e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_LOCK");
return ERROR_NAND_OPERATION_FAILED;
}
| ((trhz & 0x7) << 16)
| ((trbwb & 0x1f) << 19)
| ((tcea & 0x3) << 24));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_TIME_REG");
return ERROR_NAND_OPERATION_FAILED;
}
retval = lpc32xx_reset(nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
float cycle;
/* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
retval = target_write_u32(target, 0x400040c8, 0x05);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set FLASHCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
* so reset calling is here at the beginning
*/
retval = lpc32xx_reset(nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_NAND_OPERATION_FAILED;
/* SLC_CFG =
*/
retval = target_write_u32(target, 0x20020014,
0x3e | ((bus_width == 16) ? 1 : 0));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CFG");
return ERROR_NAND_OPERATION_FAILED;
}
/* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
retval = target_write_u32(target, 0x20020020, 0x03);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_IEN");
return ERROR_NAND_OPERATION_FAILED;
}
/* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
retval = target_write_u32(target, 0x400040e8, 0x01);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set DMACLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* DMACConfig = DMA enabled*/
retval = target_write_u32(target, 0x31000030, 0x01);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set DMACConfig");
return ERROR_NAND_OPERATION_FAILED;
}
| ((w_hold & 0xf) << 20)
| ((w_width & 0xf) << 24)
| ((w_rdy & 0xf) << 28));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_TAC");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = 0xff (reset controller and NAND device) */
retval = target_write_u32(target, 0x200b8000, 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
retval = target_write_u32(target, 0x20020010, 0x6);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = command */
retval = target_write_u32(target, 0x200b8000, command);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CMD = command */
retval = target_write_u32(target, 0x20020008, command);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_ADDR = address */
retval = target_write_u32(target, 0x200b8004, address);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_ADDR = address */
retval = target_write_u32(target, 0x20020004, address);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_DATA = data */
retval = target_write_u32(target, 0x200b0000, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_DATA = data */
retval = target_write_u32(target, 0x20020000, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
return ERROR_NAND_OPERATION_FAILED;
}
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
/* data = SLC_DATA, must use 32-bit access */
retval = target_read_u32(target, 0x20020000, &data32);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CMD = sequential input */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
if (nand->page_size == 512) {
/* MLC_ADDR = 0x0 (one column cycle) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
(page >> 16) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
} else {
/* MLC_ADDR = 0x0 (two column cycles) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* write MLC_ECC_ENC_REG to start encode cycle */
retval = target_write_u32(target, 0x200b8008, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_ENC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_memory(target, 0x200a8000,
4, 128, page_buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_BUF (data)");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_memory(target, 0x200a8000,
1, 6, oob_buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_BUF (oob)");
return ERROR_NAND_OPERATION_FAILED;
}
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
retval = target_write_u32(target, 0x200b8010, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CMD = auto program command */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
/* DMACIntTCClear = ch0 */
retval = target_write_u32(target, 0x31000008, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntTCClear");
return retval;
}
/* DMACIntErrClear = ch0 */
retval = target_write_u32(target, 0x31000010, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntErrClear");
return retval;
}
retval = target_write_u32(target, 0x31000110,
1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
| 0<<15 | 0<<16 | 0<<18);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACC0Config");
return retval;
}
/* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
retval = target_write_u32(target, 0x20020010, 0x3);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_CTRL");
return retval;
}
/* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
retval = target_write_u32(target, 0x20020028, 2);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_ICR");
return retval;
}
/* SLC_TC */
retval = target_write_u32(target, 0x20020030, count);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
return retval;
}
/* Read DMACRawIntTCStat */
retval = target_read_u32(target, 0x31000014, &tc_stat);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DMACRawIntTCStat");
return 0;
}
/* Read DMACRawIntErrStat */
retval = target_read_u32(target, 0x31000018, &err_stat);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DMACRawIntErrStat");
return 0;
}
retval = target_write_memory(target, target_mem_base, 4,
nll * sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptors to IRAM");
return retval;
}
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("NAND_CMD_SEQIN failed");
return retval;
}
WIDTH = bus_width
*/
retval = target_write_u32(target, 0x20020014, 0x3c);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_CFG");
return retval;
}
retval = target_write_memory(target,
target_mem_base + DATA_OFFS,
4, nand->page_size/4, fdata);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write data to IRAM");
return retval;
}
retval = target_write_memory(target, 0x31000100, 4,
sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptor to DMAC");
return retval;
}
int tot_size = nand->page_size;
tot_size += tot_size == 2048 ? 64 : 16;
retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("DMA failed");
return retval;
}
static uint32_t hw_ecc[8];
retval = target_read_memory(target, target_mem_base + ECC_OFFS,
4, ecc_count, (uint8_t *)hw_ecc);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Reading hw generated ECC from IRAM failed");
return retval;
}
}
retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
foob_size / 4, foob);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Writing OOB to IRAM failed");
return retval;
}
retval = target_write_memory(target, 0x31000100, 4,
sizeof(struct dmac_ll) / 4,
(uint8_t *)(&dmalist[nll-1]));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
return retval;
}
/* DMACIntTCClear = ch0 */
retval = target_write_u32(target, 0x31000008, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntTCClear");
return retval;
}
retval = target_write_u32(target, 0x31000110,
1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
| 0<<15 | 0<<16 | 0<<18);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACC0Config");
return retval;
}
} else {
/* Start xfer of data from iram to flash using DMA */
retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("DMA OOB failed");
return retval;
}
/* Let NAND start actual writing */
retval = nand_write_finish(nand);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("nand_write_finish failed");
return retval;
}
/* MLC_CMD = Read0 */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
}
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
/* small page device
* MLC_ADDR = 0x0 (one column cycle) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
(page >> 16) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* large page device
* MLC_ADDR = 0x0 (two column cycles) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CMD = Read Start */
retval = target_write_u32(target, 0x200b8000,
NAND_CMD_READSTART);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
while (page_bytes_done < (uint32_t)nand->page_size) {
/* MLC_ECC_AUTO_DEC_REG = dummy */
retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
}
retval = target_read_u32(target, 0x200b8048, &mlc_isr);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_ISR");
return ERROR_NAND_OPERATION_FAILED;
}
if (data) {
retval = target_read_memory(target, 0x200a8000, 4, 128,
page_buffer + page_bytes_done);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_BUF (data)");
return ERROR_NAND_OPERATION_FAILED;
}
if (oob) {
retval = target_read_memory(target, 0x200a8000, 4, 4,
oob_buffer + oob_bytes_done);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_BUF (oob)");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_memory(target, target_mem_base, 4,
nll * sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptors to IRAM");
return retval;
}
retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
return retval;
}
WIDTH = bus_width
*/
retval = target_write_u32(target, 0x20020014, 0x3e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
return retval;
}
/* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptor to DMAC");
return retval;
}
int tot_size = nand->page_size;
tot_size += nand->page_size == 2048 ? 64 : 16;
retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
return retval;
}
if (data) {
retval = target_read_memory(target, target_mem_base + DATA_OFFS,
4, data_size/4, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read data from IRAM");
return retval;
}
retval = target_read_memory(target,
target_mem_base + SPARE_OFFS, 4,
oob_size/4, oob);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read OOB from IRAM");
return retval;
}
retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
4, nand->page_size == 2048 ? 16 : 4, foob);
lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read OOB from IRAM");
return retval;
}
static uint32_t hw_ecc[8]; /* max size */
retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
ecc_count, (uint8_t *)hw_ecc);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read hw generated ECC from IRAM");
return retval;
}
/* Read MLC_ISR, wait for controller to become ready */
retval = target_read_u8(target, 0x200b8048, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_STAT");
return ERROR_NAND_OPERATION_FAILED;
}
/* Read SLC_STAT and check READY bit */
retval = target_read_u32(target, 0x20020018, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_STAT");
return ERROR_NAND_OPERATION_FAILED;
}
/* Read MLC_ISR, wait for NAND flash device to
* become ready */
retval = target_read_u8(target, 0x200b8048, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_ISR");
return ERROR_NAND_OPERATION_FAILED;
}
/* Read SLC_STAT and check READY bit */
retval = target_read_u32(target, 0x20020018, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SLC_STAT");
return ERROR_NAND_OPERATION_FAILED;
}
int retval;
/* Read SLC_INT_STAT and check INT_TC_STAT bit */
retval = target_read_u32(target, 0x2002001c, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read SLC_INT_STAT");
return 0;
}
#define CALL_S3C24XX_DEVICE_COMMAND(d, i) \
do { \
int retval = CALL_COMMAND_HANDLER(s3c24xx_nand_device_command, d, i); \
- if (ERROR_OK != retval) \
+ if (retval != ERROR_OK) \
return retval; \
} while (0)
struct nand_device *p;
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (NULL == p->device) {
struct nand_device *p;
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = nand_probe(p);
struct nand_device *p;
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
unsigned long offset;
struct nand_device *p;
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (CMD_ARGC == 3) {
struct nand_fileio_state s;
int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
&s, &nand, FILEIO_READ, false, true);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
uint32_t total_bytes = s.size;
retval = nand_write_page(nand, s.address / nand->page_size,
s.page, s.page_size, s.oob, s.oob_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
command_print(CMD, "failed writing file %s "
"to NAND flash %s at offset 0x%8.8" PRIx32,
CMD_ARGV[1], CMD_ARGV[0], s.address);
struct nand_fileio_state file;
int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
&file, &nand, FILEIO_READ, false, true);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct nand_fileio_state dev;
dev.size = file.size;
dev.oob_format = file.oob_format;
retval = nand_fileio_start(CMD, nand, NULL, FILEIO_NONE, &dev);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
while (file.size > 0) {
retval = nand_read_page(nand, dev.address / dev.page_size,
dev.page, dev.page_size, dev.oob, dev.oob_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
command_print(CMD, "reading NAND flash page failed");
nand_fileio_cleanup(&dev);
nand_fileio_cleanup(&file);
struct nand_fileio_state s;
int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
&s, &nand, FILEIO_WRITE, true, false);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
while (s.size > 0) {
size_t size_written;
retval = nand_read_page(nand, s.address / nand->page_size,
s.page, s.page_size, s.oob, s.oob_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
command_print(CMD, "reading NAND flash page failed");
nand_fileio_cleanup(&s);
return retval;
struct nand_device *p;
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (NULL == p->device) {
if (NULL != controller->commands) {
retval = register_commands(CMD_CTX, NULL,
controller->commands);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
c = malloc(sizeof(struct nand_device));
c->next = NULL;
retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("'%s' driver rejected nand flash. Usage: %s",
controller->name,
controller->usage);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (ambiqmicro_mass_erase(bank) == ERROR_OK) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (ambiqmicro_erase(bank, first, last) == ERROR_OK)
struct samv_flash_bank *samv_info = bank->driver_priv;
if (!samv_info->probed) {
int r = samv_probe(bank);
- if (ERROR_OK != r)
+ if (r != ERROR_OK)
return r;
}
command_print_sameline(cmd, "Cortex-M7 detected with %" PRIu32 " kB flash\n",
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (avrf_mass_erase(bank) == ERROR_OK) {
int retval = ERROR_OK;
start_ms = timeval_ms();
- while (CC26XX_BUFFER_FULL == status) {
+ while (status == CC26XX_BUFFER_FULL) {
retval = target_read_u32(target, status_addr, &status);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
elapsed_ms = timeval_ms() - start_ms;
break;
};
- if (CC26XX_BUFFER_EMPTY != status) {
+ if (status != CC26XX_BUFFER_EMPTY) {
LOG_ERROR("%s: Flash operation failed", cc26xx_bank->family_name);
return ERROR_FAIL;
}
/* Make sure we've probed the flash to get the device and size */
retval = cc26xx_auto_probe(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Check for working area to use for flash helper algorithm */
target_free_working_area(target, cc26xx_bank->working_area);
retval = target_alloc_working_area(target, cc26xx_bank->algo_working_size,
&cc26xx_bank->working_area);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Confirm the defined working address is the area we need to use */
/* Write flash helper algorithm into target memory */
retval = target_write_buffer(target, CC26XX_ALGO_BASE_ADDRESS,
cc26xx_bank->algo_size, cc26xx_bank->algo_code);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("%s: Failed to load flash helper algorithm",
cc26xx_bank->family_name);
target_free_working_area(target, cc26xx_bank->working_area);
/* Begin executing the flash helper algorithm */
retval = target_start_algorithm(target, 0, NULL, 0, NULL,
CC26XX_ALGO_BASE_ADDRESS, 0, &cc26xx_bank->armv7m_info);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("%s: Failed to start flash helper algorithm",
cc26xx_bank->family_name);
target_free_working_area(target, cc26xx_bank->working_area);
}
retval = cc26xx_init(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Initialize algorithm parameters */
sizeof(algo_params), (uint8_t *)&algo_params);
/* Wait for command to complete */
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[0]);
/* Regardless of errors, try to close down algo */
length = (last - first + 1) * cc26xx_bank->sector_length;
retval = cc26xx_init(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Set up algorithm parameters for erase command */
sizeof(algo_params), (uint8_t *)&algo_params);
/* If no error, wait for erase to finish */
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[0]);
/* Regardless of errors, try to close down algo */
}
retval = cc26xx_init(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Initialize algorithm parameters to default values */
/* Put next block of data to flash into buffer */
retval = target_write_buffer(target, cc26xx_bank->buffer_addr[index],
size, buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write data to target memory");
break;
}
/* Issue flash helper algorithm parameters for block write */
retval = target_write_buffer(target, cc26xx_bank->params_addr[index],
sizeof(algo_params[index]), (uint8_t *)&algo_params[index]);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
break;
/* Wait for next ping pong buffer to be ready */
index ^= 1;
retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[index]);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
break;
count -= size;
}
/* If no error yet, wait for last buffer to finish */
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
index ^= 1;
retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[index]);
}
int retval;
retval = target_read_u32(target, FCFG1_ICEPICK_ID, &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
cc26xx_bank->icepick_id = value;
retval = target_read_u32(target, FCFG1_USER_ID, &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
cc26xx_bank->user_id = value;
}
retval = target_read_u32(target, CC26XX_FLASH_SIZE_INFO, &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
num_sectors = value & 0xff;
if (num_sectors > max_sectors)
/* Set starting address to erase to zero */
retval = target_write_u32(target, FMA_REGISTER_ADDR, 0);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Write the MERASE bit of the FMC register */
retval = target_write_u32(target, FMC_REGISTER_ADDR, FMC_MERASE_VALUE);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Poll the MERASE bit until the mass erase is complete */
start_ms = timeval_ms();
while (!done) {
retval = target_read_u32(target, FMC_REGISTER_ADDR, &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if ((value & FMC_MERASE_BIT) == 0) {
/* Set starting address to erase */
retval = target_write_u32(target, FMA_REGISTER_ADDR, address);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Write the ERASE bit of the FMC register */
retval = target_write_u32(target, FMC_REGISTER_ADDR, FMC_ERASE_VALUE);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Poll the ERASE bit until the erase is complete */
start_ms = timeval_ms();
while (!done) {
retval = target_read_u32(target, FMC_REGISTER_ADDR, &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if ((value & FMC_ERASE_BIT) == 0) {
/* Obtain working area to use for flash helper algorithm */
retval = target_alloc_working_area(target, sizeof(cc3220sf_algo),
&algo_working_area);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Obtain working area to use for flash buffer */
retval = target_alloc_working_area(target,
target_get_working_area_avail(target), &buffer_working_area);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
target_free_working_area(target, algo_working_area);
return retval;
}
/* Write flash helper algorithm into target memory */
retval = target_write_buffer(target, algo_base_address,
sizeof(cc3220sf_algo), cc3220sf_algo);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
target_free_working_area(target, algo_working_area);
target_free_working_area(target, buffer_working_area);
return retval;
/* Retrieve what is already in flash at the head address */
retval = target_read_buffer(target, head_address, sizeof(head), head);
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
/* Substitute in the new data to write */
while ((remaining > 0) && (head_offset < 4)) {
head[head_offset] = *buffer;
}
}
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
/* Helper parameters are passed in registers R0-R2 */
/* Set start of data buffer, address to write to, and word count */
buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address);
sizeof(head), head);
}
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
/* Execute the flash helper algorithm */
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
algo_base_address, 0, FLASH_TIMEOUT,
&cc3220sf_bank->armv7m_info);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
LOG_ERROR("cc3220sf: Flash algorithm failed to run");
/* Check that the head value was written to flash */
/* Adjust remaining so it is a multiple of whole words */
remaining -= tail_count;
- while ((ERROR_OK == retval) && (remaining > 0)) {
+ while ((retval == ERROR_OK) && (remaining > 0)) {
/* Set start of data buffer and address to write to */
buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address);
buf_set_u32(reg_params[1].value, 0, 32, address);
/* Fill up buffer with data to flash */
retval = target_write_buffer(target, algo_buffer_address,
algo_buffer_size, buffer);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
break;
/* Count to write is in 32-bit words */
/* Fill buffer with what's left of the data */
retval = target_write_buffer(target, algo_buffer_address,
remaining, buffer);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
break;
/* Calculate the final word count to write */
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
algo_base_address, 0, FLASH_TIMEOUT,
&cc3220sf_bank->armv7m_info);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("cc3220sf: Flash algorithm failed to run");
break;
}
}
/* Do one word write for any final bytes less than a full word */
- if ((ERROR_OK == retval) && (0 != tail_count)) {
+ if ((retval == ERROR_OK) && (0 != tail_count)) {
uint8_t tail[4];
/* Set starting byte offset for data to write */
/* Retrieve what is already in flash at the tail address */
retval = target_read_buffer(target, address, sizeof(tail), tail);
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
/* Substitute in the new data to write */
while (tail_count > 0) {
tail[tail_offset] = *buffer;
}
}
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
/* Set start of data buffer, address to write to, and word count */
buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address);
buf_set_u32(reg_params[1].value, 0, 32, address);
sizeof(tail), tail);
}
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
/* Execute the flash helper algorithm */
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
algo_base_address, 0, FLASH_TIMEOUT,
&cc3220sf_bank->armv7m_info);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
LOG_ERROR("cc3220sf: Flash algorithm failed to run");
/* Check that the tail was written to flash */
memset(efm32_info, 0, sizeof(struct efm32_info));
ret = target_read_u32(bank->target, CPUID, &cpuid);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
if (((cpuid >> 4) & 0xfff) == 0xc23) {
}
ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
uint8_t pg_size = 0;
ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
&pg_size);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
uint32_t reg_val = 0;
ret = efm32x_read_reg_u32(bank, reg, ®_val);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
if (set)
while (1) {
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
break;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_DEBUG("status 0x%" PRIx32, status);
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
efm32x_msc_lock(bank, 0);
ret = efm32x_set_wren(bank, 1);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to enable MSC write");
return ret;
}
for (unsigned int i = first; i <= last; i++) {
ret = efm32x_erase_page(bank, bank->sectors[i].offset);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
LOG_ERROR("Failed to erase page %d", i);
}
for (int i = 0; i < data_size; i++, ptr++) {
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read PLW %d", i);
return ret;
}
/* ULW, word 126 */
ptr = efm32x_info->lb_page + 126;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read ULW");
return ret;
}
/* DLW, word 127 */
ptr = efm32x_info->lb_page + 127;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read DLW");
return ret;
}
/* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
ptr = efm32x_info->lb_page + 125;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read MLW");
return ret;
}
/* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
ptr = efm32x_info->lb_page + 124;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read ALW");
return ret;
}
/* CLW1, word 123, present in EFR32 */
ptr = efm32x_info->lb_page + 123;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read CLW1");
return ret;
}
/* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
ptr = efm32x_info->lb_page + 122;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read CLW0");
return ret;
}
int ret = 0;
ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to erase LB page");
return ret;
}
for (unsigned int i = first; i <= last; i++) {
ret = efm32x_set_page_lock(bank, i, set);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to set lock on page %d", i);
return ret;
}
}
ret = efm32x_write_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to write LB page");
return ret;
}
keep_alive();
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_DEBUG("status 0x%" PRIx32, status);
ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Wait for WDATAREADY failed");
return ret;
}
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("WDATA write failed");
return ret;
}
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_WRITEONCE_MASK);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("WRITECMD write failed");
return ret;
}
ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
EFM32_MSC_STATUS_BUSY_MASK, 0);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Wait for BUSY failed");
return ret;
}
memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
ret = efm32x_read_info(bank, &efm32_mcu_info);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_INFO("detected part: %s Gecko, rev %d",
bank->num_sectors = num_pages;
ret = efm32x_read_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read LB data");
return ret;
}
}
ret = efm32x_read_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read LB data");
return ret;
}
int ret;
ret = efm32x_read_info(bank, &info);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read EFM32 info");
return ret;
}
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
*ptr = 0;
retval = efm32x_write_lock_data(bank);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Failed to write LB page");
return retval;
}
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
em357_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = em357_mass_erase(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (fm3_chip_erase(bank) == ERROR_OK) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (bank->target->state != TARGET_HALTED) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (bank->target->state != TARGET_HALTED) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
/* Get the bank descriptor */
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
/* Get the bank descriptor */
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
return ERROR_OK;
}
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (max32xxx_mass_erase(bank) == ERROR_OK) {
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
info = bank->driver_priv;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
info = bank->driver_priv;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
info = bank->driver_priv;
/* Update the protection array */
retval = max32xxx_protect_check(bank);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_WARNING("Error updating the protection array");
return retval;
}
{
int device_type = MSP432_NO_TYPE;
- if (MSP432E4 == family_type) {
+ if (family_type == MSP432E4) {
/* MSP432E4 device family */
if (device_id == 0x180C0002) {
/* Write out parameters to target memory */
retval = target_write_buffer(target, ALGO_PARAMS_BASE_ADDR,
sizeof(struct msp432_algo_params), (uint8_t *)algo_params);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Write out command to target memory */
int retval = ERROR_OK;
start_ms = timeval_ms();
- while ((0 == return_code) || (FLASH_BUSY == return_code)) {
+ while ((0 == return_code) || (return_code == FLASH_BUSY)) {
retval = target_read_u32(target, ALGO_RETURN_CODE_ADDR, &return_code);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
elapsed_ms = timeval_ms() - start_ms;
break;
};
- if (FLASH_SUCCESS != return_code) {
+ if (return_code != FLASH_SUCCESS) {
LOG_ERROR("msp432: Flash operation failed: %s",
msp432_return_text(return_code));
return ERROR_FAIL;
}
start_ms = timeval_ms();
- while (BUFFER_INACTIVE != status_code) {
+ while (status_code != BUFFER_INACTIVE) {
retval = target_read_u32(target, status_addr, &status_code);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
elapsed_ms = timeval_ms() - start_ms;
break;
};
- if (BUFFER_INACTIVE != status_code) {
+ if (status_code != BUFFER_INACTIVE) {
LOG_ERROR(
"msp432: Flash operation failed: buffer not written to flash");
return ERROR_FAIL;
/* Make sure we've probed the flash to get the device and size */
retval = msp432_auto_probe(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Choose appropriate flash helper algorithm */
target_free_working_area(target, msp432_bank->working_area);
retval = target_alloc_working_area(target, ALGO_WORKING_SIZE,
&msp432_bank->working_area);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Confirm the defined working address is the area we need to use */
/* Write flash helper algorithm into target memory */
retval = target_write_buffer(target, ALGO_BASE_ADDR, loader_size,
loader_code);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Initialize the ARMv7 specific info to run the algorithm */
/* Write out parameters to target memory */
retval = target_write_buffer(target, ALGO_PARAMS_BASE_ADDR,
sizeof(algo_params), (uint8_t *)&algo_params);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Initialize stack pointer for flash helper algorithm */
retval = target_start_algorithm(target, 0, 0, 1, reg_params,
algo_entry_addr, 0, &msp432_bank->armv7m_info);
destroy_reg_param(®_params[0]);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("msp432: Failed to start flash helper algorithm");
return retval;
}
/* Issue the init command to the flash helper algorithm */
retval = msp432_exec_cmd(target, &algo_params, FLASH_INIT);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = msp432_wait_return_code(target);
/* Issue the exit command to the flash helper algorithm */
retval = msp432_exec_cmd(target, &algo_params, FLASH_EXIT);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
(void)msp432_wait_return_code(target);
}
retval = msp432_init(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Initialize algorithm parameters to default values */
/* Issue the mass erase command to the flash helper algorithm */
retval = msp432_exec_cmd(target, &algo_params, FLASH_MASS_ERASE);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return retval;
}
retval = msp432_wait_return_code(target);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return retval;
}
retval = msp432_quit(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return retval;
}
retval = msp432_mass_erase(bank, all);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (MSP432E4 == msp432_bank->family_type) {
}
retval = msp432_init(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Initialize algorithm parameters to default values */
/* Issue the sector erase command to the flash helper algorithm */
retval = msp432_exec_cmd(target, &algo_params, FLASH_SECTOR_ERASE);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return retval;
}
retval = msp432_wait_return_code(target);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return retval;
}
}
retval = msp432_quit(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return retval;
if (offset < start) {
uint32_t start_count = MIN(start - offset, count);
retval = msp432_write(bank, buffer, offset, start_count);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
/* Send a request for anything after read-only sectors */
}
retval = msp432_init(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Initialize algorithm parameters to default values */
/* Set up flash helper algorithm to continuous flash mode */
retval = msp432_exec_cmd(target, &algo_params, FLASH_CONTINUOUS);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return retval;
}
/* Put next block of data to flash into buffer */
retval = target_write_buffer(target, ALGO_BUFFER1_ADDR, size, buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write data to target memory");
(void)msp432_quit(bank);
return ERROR_FLASH_OPERATION_FAILED;
/* Signal the flash helper algorithm that data is ready to flash */
retval = target_write_u32(target, ALGO_BUFFER1_STATUS_ADDR,
data_ready);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return ERROR_FLASH_OPERATION_FAILED;
}
retval = msp432_wait_inactive(target, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return retval;
}
/* Confirm that the flash helper algorithm is finished */
retval = msp432_wait_return_code(target);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
(void)msp432_quit(bank);
return retval;
}
retval = msp432_quit(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return retval;
/* Read the flash size register to determine this is a P4 or not */
/* MSP432P4s will return the size of flash. MSP432E4s will return zero */
retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (0 == size) {
msp432_bank->family_type = MSP432E4;
retval = target_read_u32(target, E4_DID0_REG, &device_id);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
msp432_bank->device_id = device_id;
retval = target_read_u32(target, E4_DID1_REG, &hardware_rev);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
msp432_bank->hardware_rev = hardware_rev;
msp432_bank->family_type = MSP432P4;
retval = target_read_u32(target, P4_DEVICE_ID_REG, &device_id);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
msp432_bank->device_id = device_id & 0xFFFF;
retval = target_read_u32(target, P4_HARDWARE_REV_REG, &hardware_rev);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
msp432_bank->hardware_rev = hardware_rev & 0xFF;
/* Set up MSP432P4 specific flash parameters */
if (is_main) {
retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
sector_length = P4_SECTOR_LENGTH;
msp432_bank->device_type == MSP432P411X_GUESS) {
/* MSP432P411x has an info size register, use that for size */
retval = target_read_u32(target, P4_FLASH_INFO_SIZE_REG, &size);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
} else {
/* All other MSP432P401x devices have fixed info region size */
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (address < bank->base || address >= (bank->base + bank->size)) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = psoc4_mass_erase(bank);
return retval;
ret = sim3x_flash_write(bank, lock_word, LOCK_WORD_ADDRESS, 4);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_INFO("Target is successfully locked");
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stellaris_mass_erase(bank) == ERROR_OK) {
uint32_t protection;
int retval = stm32x_check_operation_supported(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* medium density - each bit refers to a 4 sector protection block
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
}
retval = stm32x_check_operation_supported(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stm32x_erase_options(bank) != ERROR_OK) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
}
retval = stm32x_check_operation_supported(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stm32x_erase_options(bank) != ERROR_OK) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
}
retval = stm32x_check_operation_supported(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
}
retval = stm32x_check_operation_supported(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_read_options(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* start with current options */
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
}
retval = stm32x_check_operation_supported(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* unlock option flash registers */
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_mass_erase(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_mass_erase(bank);
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_read_options(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_read_options(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stm32x_info = bank->driver_priv;
" finally unlock it. Clears PCROP and mass erases flash.");
retval = stm32x_read_options(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stm32x_is_otp(bank)) {
if (strcmp(CMD_ARGV[1], "enable") == 0) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_set_rdp(bank, OPT_RDP_L1);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_set_rdp(bank, OPT_RDP_L0);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32x_mass_erase(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
uint32_t reg_offset, value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
retval = stm32x_read_flash_reg(bank, reg_offset, &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32,
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
uint32_t reg_offset, value, mask = 0xffffffff;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32l4_mass_erase(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
uint32_t reg_offset, reg_addr;
reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
uint32_t reg_offset;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32l4_unlock_reg(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32l4_unlock_option_reg(bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stm32l4_is_otp(bank)) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stm32l4_is_otp(bank)) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (stm32l4_is_otp(bank)) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (!stm32l4_is_otp(bank)) {
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32lx_mass_erase(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32lx_lock(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = stm32lx_unlock(bank);
return ERROR_COMMAND_SYNTAX_ERROR;
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stmqspi_info = bank->driver_priv;
return ERROR_COMMAND_SYNTAX_ERROR;
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, index++, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str7x_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
uint32_t bbsr, nbbsr, bbadr, nbbadr;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
status = str9xpec_write_options(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
status = str9xpec_lock_device(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
status = str9xpec_unlock_device(bank);
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
str9xpec_info = bank->driver_priv;
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = swm050_mass_erase(bank);
struct flash_bank *p;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = p->driver->erase_check(p);
if (retval == ERROR_OK)
retval = flash_erase_address_range(target, do_pad, address, length);
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "erased address " TARGET_ADDR_FMT " (length %" PRIu32 ")"
" in %fs (%0.3f KiB/s)", address, length,
duration_elapsed(&bench), duration_kbps(&bench, length));
retval = flash_driver_erase(p, first, last);
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "erased sectors %" PRIu32 " "
"through %" PRIu32 " on flash bank %u "
"in %fs", first, last, p->bank_number, duration_elapsed(&bench));
return retval;
}
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "wrote %" PRIu32 " bytes from file %s "
"in %fs (%0.3f KiB/s)", written, CMD_ARGV[0],
duration_elapsed(&bench), duration_kbps(&bench, written));
return retval;
}
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "verified %" PRIu32 " bytes from file %s "
"in %fs (%0.3f KiB/s)", verified, CMD_ARGV[0],
duration_elapsed(&bench), duration_kbps(&bench, verified));
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
offset = 0;
free(buffer);
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "wrote %zu bytes from file %s to flash bank %u"
" at offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)",
length, CMD_ARGV[1], bank->bank_number, offset,
struct flash_bank *p;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
offset = 0;
struct flash_bank *p;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
offset = 0;
struct flash_bank *p;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], p->default_padded_value);
if (NULL != driver->commands) {
int retval = register_commands(CMD_CTX, NULL,
driver->commands);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("couldn't register '%s' commands",
driver_name);
return ERROR_FAIL;
int retval;
retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
"; usage: %s", driver_name, c->base, driver->usage);
free(c);
w_buffer += len;
sector_bytes -= len;
ret = isc_program_data_page(bank, page_buf);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
else {
LOG_DEBUG("written %d bytes from %d", dbg_written, dbg_count);
if (write_flag) {
for (unsigned int i = 0; i < bank->num_sectors; i++) {
ret = isc_set_data_done(bank, i);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
}
}
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
uint16_t ccb = 0xFFFF;
sector = gucr_num(bank);
isc_clear_protect(bank, sector, sector);
int ret = isc_erase_sectors(bank, sector, sector);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
ret = isc_program_ccb(bank, ccb);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
ret = isc_program_single_revision_btc(bank);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
ret = isc_set_data_done(bank, sector);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
/* SUCR sector */
sector = sucr_num(bank);
isc_clear_protect(bank, sector, sector);
ret = isc_erase_sectors(bank, sector, sector);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
ret = isc_program_singe_revision_sucr(bank);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
ret = isc_set_data_done(bank, sector);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
goto EXIT;
EXIT:
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return fpga_configure(bank);
{
const char *sep, *name;
int retval = CALL_COMMAND_HANDLER(handle_hello_args, &sep, &name);
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
command_print(CMD, "Greetings%s%s!", sep, name);
return retval;
}
} else {
retval = __register_commands(cmd_ctx, cmd_prefix, cr->chain, data, override_target);
}
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
break;
}
}
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
for (unsigned j = 0; j < i; j++)
unregister_command(cmd_ctx, cmd_prefix, cmds[j].name);
}
unsigned long duration = 0;
int retval = parse_ulong(CMD_ARGV[0], &duration);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (!busy) {
LOG_ERROR("Invalid command argument"); \
return ERROR_COMMAND_ARGUMENT_INVALID; \
} \
- if ((max == *ul) && (ERANGE == errno)) { \
+ if ((max == *ul) && (errno == ERANGE)) { \
LOG_ERROR("Argument overflow"); \
return ERROR_COMMAND_ARGUMENT_OVERFLOW; \
} \
- if (min && (min == *ul) && (ERANGE == errno)) { \
+ if (min && (min == *ul) && (errno == ERANGE)) { \
LOG_ERROR("Argument underflow"); \
return ERROR_COMMAND_ARGUMENT_UNDERFLOW; \
} \
{ \
functype n; \
int retval = parse ## funcname(str, &n); \
- if (ERROR_OK != retval) \
+ if (retval != ERROR_OK) \
return retval; \
if (n > max) \
return ERROR_COMMAND_ARGUMENT_OVERFLOW; \
#define COMMAND_PARSE_NUMBER(type, in, out) \
do { \
int retval_macro_tmp = parse_ ## type(in, &(out)); \
- if (ERROR_OK != retval_macro_tmp) { \
+ if (retval_macro_tmp != ERROR_OK) { \
command_print(CMD, stringify(out) \
" option value ('%s') is not valid", in); \
return retval_macro_tmp; \
do { \
bool value; \
int retval_macro_tmp = command_parse_bool_arg(in, &value); \
- if (ERROR_OK != retval_macro_tmp) { \
+ if (retval_macro_tmp != ERROR_OK) { \
command_print(CMD, stringify(out) \
" option value ('%s') is not valid", in); \
command_print(CMD, " choices are '%s' or '%s'", \
if (ERROR_OK == retval && sizeof(uint32_t) != size_read)
retval = -EIO;
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
*data = be_to_h_u32(buf);
return retval;
if (NULL != adapter_drivers[i]->commands) {
retval = register_commands(CMD_CTX, NULL,
adapter_drivers[i]->commands);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz);
retval = jtag_config_khz(khz);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
int cur_speed = jtag_get_speed_khz();
retval = jtag_get_speed_readable(&cur_speed);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (cur_speed)
switch (n->value) {
case NTAP_OPT_EXPECTED_ID:
e = jim_newtap_expected_id(n, goi, tap);
- if (JIM_OK != e) {
+ if (e != JIM_OK) {
free(cp);
free(tap);
return e;
int result, ret;
ret = f(dev, ep, bytes + count, size - count, timeout, &result);
- if (ERROR_OK == ret)
+ if (ret == ERROR_OK)
count += result;
- else if ((ERROR_TIMEOUT_REACHED != ret) || !--tries)
+ else if ((ret != ERROR_TIMEOUT_REACHED) || !--tries)
return ret;
}
if (usb_out_packets_buffer_length == 0)
return 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)");
if (aice_usb_write(usb_out_packets_buffer,
usb_out_packets_buffer_length = 0;
usb_in_packets_buffer_length = 0;
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)");
/* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
{
uint32_t max_packet_size = AICE_OUT_PACKETS_BUFFER_SIZE;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
max_packet_size = AICE_OUT_PACK_COMMAND_SIZE;
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
max_packet_size = AICE_OUT_BATCH_COMMAND_SIZE;
} else {
/* AICE_COMMAND_MODE_NORMAL */
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
/** TODO: modify receive length */
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA);
- if (AICE_FORMAT_DTHA != result) {
+ if (result != AICE_FORMAT_DTHA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHA, result);
return ERROR_FAIL;
int aice_read_ctrl(uint32_t address, uint32_t *data)
{
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
aice_pack_htda(AICE_CMD_READ_CTRL, 0, address);
LOG_DEBUG("READ_CTRL, address: 0x%" PRIx32, address);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA);
- if (AICE_FORMAT_DTHA != result) {
+ if (result != AICE_FORMAT_DTHA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHA, result);
return ERROR_FAIL;
int aice_write_ctrl(uint32_t address, uint32_t data)
{
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDC,
AICE_FORMAT_DTHB);
LOG_DEBUG("WRITE_CTRL, address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, data);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHB);
- if (AICE_FORMAT_DTHB != result) {
+ if (result != AICE_FORMAT_DTHB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHB, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
LOG_DEBUG("READ_DTR, COREID: %" PRIu8, target_id);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
- if (AICE_FORMAT_DTHMA != result) {
+ if (result != AICE_FORMAT_DTHMA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMA, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA,
AICE_FORMAT_DTHMB);
LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %" PRIu8, target_id);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
}
{
int retry_times = 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
AICE_FORMAT_DTHMB);
LOG_DEBUG("WRITE_DTR, COREID: %" PRIu8 ", data: 0x%" PRIx32, target_id, data);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
}
{
int retry_times = 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA,
AICE_FORMAT_DTHMB);
LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %" PRIu8 "", target_id);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
}
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
LOG_DEBUG("READ_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
- if (AICE_FORMAT_DTHMA != result) {
+ if (result != AICE_FORMAT_DTHMA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMA, result);
return ERROR_AICE_DISCONNECT;
{
int retry_times = 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address, data,
AICE_LITTLE_ENDIAN);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
target_id, address, data);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
LOG_DEBUG("READ_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
- if (AICE_FORMAT_DTHMA != result) {
+ if (result != AICE_FORMAT_DTHMA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMA, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address, data,
AICE_LITTLE_ENDIAN);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
target_id, address, data);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
memcpy(big_endian_word, word, sizeof(big_endian_word));
aice_switch_to_big_endian(big_endian_word, num_of_words);
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id,
num_of_words - 1, 0, big_endian_word, num_of_words,
AICE_LITTLE_ENDIAN);
big_endian_word[3]);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
}
{
int retry_times = 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN);
return aice_usb_packet_append(usb_out_buffer,
AICE_FORMAT_HTDMC,
LOG_DEBUG("EXECUTE, COREID: %" PRIu8 "", target_id);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
address,
data);
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH)) {
aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0, address,
data & 0x000000FF, data_endian);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
}
address,
data);
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH)) {
aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0,
(address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
address,
data);
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH)) {
aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0,
(address >> 2) & 0x3FFFFFFF, data, data_endian);
return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
{
int retry_times = 0;
- if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
+ if (aice_command_mode == AICE_COMMAND_MODE_PACK) {
aice_usb_packet_flush();
- } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
+ } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) {
aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id,
num_of_words - 1, 0, word, data_endian);
return aice_usb_packet_append(usb_out_buffer,
target_id, num_of_words);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
LOG_DEBUG("READ_MEM_B, COREID: %" PRIu8 "", target_id);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
- if (AICE_FORMAT_DTHMA != result) {
+ if (result != AICE_FORMAT_DTHMA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMA, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
LOG_DEBUG("READ_MEM_H, CORE_ID: %" PRIu8 "", target_id);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
- if (AICE_FORMAT_DTHMA != result) {
+ if (result != AICE_FORMAT_DTHMA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMA, result);
return ERROR_FAIL;
{
int retry_times = 0;
- if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
- (AICE_COMMAND_MODE_BATCH == aice_command_mode))
+ if ((aice_command_mode == AICE_COMMAND_MODE_PACK) ||
+ (aice_command_mode == AICE_COMMAND_MODE_BATCH))
aice_usb_packet_flush();
do {
LOG_DEBUG("READ_MEM, COREID: %" PRIu8 "", target_id);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
- if (AICE_FORMAT_DTHMA != result) {
+ if (result != AICE_FORMAT_DTHMA) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMA, result);
return ERROR_FAIL;
LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32, num_of_words);
int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
- if (AICE_FORMAT_DTHMB != result) {
+ if (result != AICE_FORMAT_DTHMB) {
LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
AICE_FORMAT_DTHMB, result);
return ERROR_FAIL;
instructions[3] = BEQ_MINUS_12;
}
} else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */
- if (FPCSR == num) {
+ if (num == FPCSR) {
instructions[0] = FMFCSR;
instructions[1] = MTSR_DTR(0);
instructions[2] = DSB;
instructions[3] = BEQ_MINUS_12;
- } else if (FPCFG == num) {
+ } else if (num == FPCFG) {
instructions[0] = FMFCFG;
instructions[1] = MTSR_DTR(0);
instructions[2] = DSB;
instructions[3] = BEQ_MINUS_12;
}
} else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */
- if (FPCSR == num) {
+ if (num == FPCSR) {
instructions[0] = MFSR_DTR(0);
instructions[1] = FMTCSR;
instructions[2] = DSB;
instructions[3] = BEQ_MINUS_12;
- } else if (FPCFG == num) {
+ } else if (num == FPCFG) {
/* FPCFG is readonly */
} else {
if (FS0 <= num && num <= FS31) { /* single precision */
if (!timeout)
break;
}
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_FAIL;
#endif
int retval;
retval = aice_scan_chain(idcode, num_of_idcode);
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
for (int i = 0; i < *num_of_idcode; i++) {
aice_core_init(i);
aice_edm_init(i);
int result = aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger_value);
- if (ERROR_AICE_TIMEOUT == result) {
+ if (result == ERROR_AICE_TIMEOUT) {
if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &ice_state) != ERROR_OK) {
LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
return ERROR_FAIL;
} else {
return ERROR_FAIL;
}
- } else if (ERROR_AICE_DISCONNECT == result) {
+ } else if (result == ERROR_AICE_DISCONNECT) {
LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
return ERROR_FAIL;
}
static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst)
{
- if ((AICE_SRST != srst) && (AICE_RESET_HOLD != srst))
+ if ((srst != AICE_SRST) && (srst != AICE_RESET_HOLD))
return ERROR_FAIL;
/* clear DBGER */
return ERROR_FAIL;
int result = ERROR_OK;
- if (AICE_SRST == srst)
+ if (srst == AICE_SRST)
result = aice_issue_srst(coreid);
else {
if (1 == total_num_of_core)
if (aice_usb_state(coreid, &state) != ERROR_OK)
return ERROR_FAIL;
- if (AICE_TARGET_HALTED == state)
+ if (state == AICE_TARGET_HALTED)
break;
int64_t then = 0;
static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val)
{
if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
- if (NDS_EDM_SR_EDMSW == addr) {
+ if (addr == NDS_EDM_SR_EDMSW) {
*val = core_info[coreid].edmsw_backup;
- } else if (NDS_EDM_SR_EDM_DTR == addr) {
+ } else if (addr == NDS_EDM_SR_EDM_DTR) {
if (core_info[coreid].target_dtr_valid) {
/* if EDM_DTR has read out, clear it. */
*val = core_info[coreid].target_dtr_backup;
static int aice_usb_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val)
{
if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
- if (NDS_EDM_SR_EDM_DTR == addr) {
+ if (addr == NDS_EDM_SR_EDM_DTR) {
core_info[coreid].host_dtr_backup = val;
core_info[coreid].edmsw_backup |= 0x2;
core_info[coreid].host_dtr_valid = true;
/* flush usb_packets_buffer as users change mode */
retval = aice_usb_packet_flush();
- if (AICE_COMMAND_MODE_BATCH == command_mode) {
+ if (command_mode == AICE_COMMAND_MODE_BATCH) {
/* reset batch buffer */
aice_command_mode = AICE_COMMAND_MODE_NORMAL;
retval = aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL, 0x40000);
return ERROR_OK;
}
- if (CLOCK_MODE_UNSELECTED == clock_mode) {
+ if (clock_mode == CLOCK_MODE_UNSELECTED) {
LOG_ERROR("An adapter speed is not selected in the init script."
" Insert a call to \"adapter speed\" or \"jtag_rclk\" to proceed.");
return ERROR_JTAG_INIT_FAILED;
if (retval != ERROR_OK)
return retval;
retval = jtag_get_speed_readable(&actual_khz);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
LOG_INFO("adapter-specific clock speed value %d", jtag_speed_var);
else if (actual_khz) {
/* Adaptive clocking -- JTAG-specific */
- if ((CLOCK_MODE_RCLK == clock_mode)
- || ((CLOCK_MODE_KHZ == clock_mode) && !requested_khz)) {
+ if ((clock_mode == CLOCK_MODE_RCLK)
+ || ((clock_mode == CLOCK_MODE_KHZ) && !requested_khz)) {
LOG_INFO("RCLK (adaptive clock speed) not supported - fallback to %d kHz"
, actual_khz);
} else
if (jtag && jtag->quit) {
/* close the JTAG interface */
int result = jtag->quit();
- if (ERROR_OK != result)
+ if (result != ERROR_OK)
LOG_ERROR("failed: %d", result);
}
}
int speed_div1;
int retval = jtag->khz(jtag_get_speed_khz(), &speed_div1);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
*speed = speed_div1;
return ERROR_OK;
static int jtag_rclk_to_speed(unsigned fallback_speed_khz, int *speed)
{
int retval = adapter_khz_to_speed(0, speed);
- if ((ERROR_OK != retval) && fallback_speed_khz) {
+ if ((retval != ERROR_OK) && fallback_speed_khz) {
LOG_DEBUG("trying fallback speed...");
retval = adapter_khz_to_speed(fallback_speed_khz, speed);
}
clock_mode = CLOCK_MODE_KHZ;
int speed = 0;
int retval = adapter_khz_to_speed(khz, &speed);
- return (ERROR_OK != retval) ? retval : jtag_set_speed(speed);
+ return (retval != ERROR_OK) ? retval : jtag_set_speed(speed);
}
int jtag_config_rclk(unsigned fallback_speed_khz)
rclk_fallback_speed_khz = fallback_speed_khz;
int speed = 0;
int retval = jtag_rclk_to_speed(fallback_speed_khz, &speed);
- return (ERROR_OK != retval) ? retval : jtag_set_speed(speed);
+ return (retval != ERROR_OK) ? retval : jtag_set_speed(speed);
}
int jtag_get_speed(int *speed)
uint32_t ns;
int retval = parse_u32(CMD_ARGV[0], &ns);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (ns == 0) {
break;
}
versaloon_usb_to = timeout_tmp;
- if (VERSALOON_RETRY_CNT == retry) {
+ if (retry == VERSALOON_RETRY_CNT) {
versaloon_fini();
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "communicate with versaloon");
return ERRCODE_FAILURE_OPERATION;
static int vsllink_init(void)
{
int retval = vsllink_interface_init();
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
versaloon_interface.adaptors.gpio.init(0);
continue;
retval = vsllink_check_usb_strings(usb_device_handle, &usb_desc);
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
break;
libusb_close(usb_device_handle);
/* Extract error code from return packet */
error = (int)xds110_get_u32(&xds110.read_payload[0]);
done = true;
- if (SC_ERR_NONE != error)
+ if (error != SC_ERR_NONE)
LOG_DEBUG("XDS110: command 0x%02x returned error %d",
xds110.write_payload[0], error);
}
if (!is_read_request)
return false;
- if (DAP_AP == type) {
+ if (type == DAP_AP) {
/* Add bank address to register address for CMAPI call */
address |= bank;
}
/* Invalidate the RDBUFF cache */
xds110.use_rdbuff = false;
- if (DAP_AP == type) {
+ if (type == DAP_AP) {
/* Add bank address to register address for CMAPI call */
address |= bank;
/* Any write to an AP register invalidates the firmware's cache */
xds110.is_ap_dirty = true;
- } else if (DAP_DP_SELECT == address) {
+ } else if (address == DAP_DP_SELECT) {
/* Any write to the SELECT register invalidates the firmware's cache */
xds110.is_ap_dirty = true;
}
* If the debugger wrote to SELECT, cache the value
* to use to build the apNum and address values above
*/
- if ((DAP_DP == type) && (DAP_DP_SELECT == address))
+ if ((type == DAP_DP) && (address == DAP_DP_SELECT))
xds110.select = value;
}
switch (n->value) {
case NTAP_OPT_EXPECTED_ID:
e = jim_newtap_expected_id(n, goi, tap);
- if (JIM_OK != e) {
+ if (e != JIM_OK) {
free(cp);
free(tap);
return e;
break;
case NTAP_OPT_EXPECTED_ID:
e = jim_newtap_expected_id(n, goi, tap);
- if (JIM_OK != e) {
+ if (e != JIM_OK) {
free(cp);
free(tap);
return e;
case NTAP_OPT_IRMASK:
case NTAP_OPT_IRCAPTURE:
e = jim_newtap_ir_param(n, goi, tap);
- if (JIM_OK != e) {
+ if (e != JIM_OK) {
free(cp);
free(tap);
return e;
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz);
retval = jtag_config_rclk(khz);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
int cur_khz = jtag_get_speed_khz();
retval = jtag_get_speed_readable(&cur_khz);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (cur_khz)
}
uint64_t value;
retval = parse_u64(CMD_ARGV[i * 2 + 1], &value);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
goto error_return;
int field_size = tap->ir_length;
initialized = 1;
retval = command_run_line(CMD_CTX, "target init");
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_FAIL;
retval = adapter_init(CMD_CTX);
command_context_mode(CMD_CTX, COMMAND_EXEC);
retval = command_run_line(CMD_CTX, "transport init");
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_FAIL;
retval = command_run_line(CMD_CTX, "dap init");
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("Examining targets...");
};
for (unsigned i = 0; NULL != command_registrants[i]; i++) {
int retval = (*command_registrants[i])(cmd_ctx);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
command_done(cmd_ctx);
return NULL;
}
}
ret = server_init(cmd_ctx);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ERROR_FAIL;
if (init_at_startup) {
ret = command_run_line(cmd_ctx, "init");
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
server_quit();
return ERROR_FAIL;
}
rtt_exit();
free_config();
- if (ERROR_FAIL == ret)
+ if (ret == ERROR_FAIL)
return EXIT_FAILURE;
- else if (ERROR_OK != ret)
+ else if (ret != ERROR_OK)
exit_on_signal(ret);
return ret;
if (pld_drivers[i]->commands) {
retval = register_commands(CMD_CTX, NULL,
pld_drivers[i]->commands);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("couldn't register '%s' commands", CMD_ARGV[0]);
return ERROR_FAIL;
}
retval = CALL_COMMAND_HANDLER(
pld_drivers[i]->pld_device_command, c);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("'%s' driver rejected pld device",
CMD_ARGV[0]);
free(c);
{
int ret = os_alloc(target, ostype);
- if (JIM_OK == ret) {
+ if (ret == JIM_OK) {
ret = target->rtos->type->create(target);
if (ret != JIM_OK)
os_free(target);
while (NULL != target) {
int retval = gdb_target_add_one(target);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = target->next;
COMMAND_HANDLER(handle_gdb_port_command)
{
int retval = CALL_COMMAND_HANDLER(server_pipe_command, &gdb_port);
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
free(gdb_port_next);
gdb_port_next = strdup(gdb_port);
}
int server_register_commands(struct command_context *cmd_ctx)
{
int retval = telnet_register_commands(cmd_ctx);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = tcl_register_commands(cmd_ctx);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = jsp_register_commands(cmd_ctx);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return register_commands(cmd_ctx, NULL, server_command_handlers);
svf_free_xxd_para(&svf_para.sdr_para);
svf_free_xxd_para(&svf_para.sir_para);
- if (ERROR_OK == ret)
+ if (ret == ERROR_OK)
command_print(CMD,
"svf file programmed %s for %d commands with %d errors",
(svf_ignore_error > 1) ? "unsuccessfully" : "successfully",
bool svf_tap_state_is_stable(tap_state_t state)
{
- return (TAP_RESET == state) || (TAP_IDLE == state)
- || (TAP_DRPAUSE == state) || (TAP_IRPAUSE == state);
+ return (state == TAP_RESET) || (state == TAP_IDLE)
+ || (state == TAP_DRPAUSE) || (state == TAP_IRPAUSE);
}
static int svf_find_string_in_array(char *str, char **strs, int num_of_element)
memset(xxr_para_tmp->mask, 0, (xxr_para_tmp->len + 7) >> 3);
}
/* do scan if necessary */
- if (SDR == command) {
+ if (command == SDR) {
/* check buffer size first, reallocate if necessary */
i = svf_para.hdr_para.len + svf_para.sdr_para.len +
svf_para.tdr_para.len;
}
svf_buffer_index += (i + 7) >> 3;
- } else if (SIR == command) {
+ } else if (command == SIR) {
/* check buffer size first, reallocate if necessary */
i = svf_para.hir_para.len + svf_para.sir_para.len +
svf_para.tir_para.len;
return ERROR_FAIL;
/* output debug info */
- if ((SIR == command) || (SDR == command)) {
+ if ((command == SIR) || (command == SDR))
SVF_BUF_LOG(DEBUG, svf_tdi_buffer, svf_check_tdo_para[0].bit_len, "TDO read");
- }
}
} else {
/* for fast executing, execute tap if necessary */
/* Read data from target. */
if (core_cnt > 0) {
retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Attempt to read core registers failed.");
retval = ERROR_FAIL;
goto exit;
}
if (aux_cnt > 0) {
retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Attempt to read aux registers failed.");
retval = ERROR_FAIL;
goto exit;
* Check before write, if aux and core count is greater than 0. */
if (core_cnt > 0) {
retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Attempt to write to core registers failed.");
retval = ERROR_FAIL;
goto exit;
if (aux_cnt > 0) {
retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Attempt to write to aux registers failed.");
retval = ERROR_FAIL;
goto exit;
/* arc_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
/* endianness, but byte array should represent target endianness */
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
switch (size) {
case 4:
target_buffer_set_u32_array(target, buffer, count,
/* Read register */
int retval = mem_ap_read_atomic_u32(ap, self->spot.base + reg, &tmp);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* clear bitfield */
COMMAND_REGISTRATION_DONE
};
e = register_commands_with_data(cmd_ctx, NULL, cti_commands, cti);
- if (ERROR_OK != e)
+ if (e != ERROR_OK)
return JIM_ERR;
list_add_tail(&cti->lh, &all_cti);
dap_commands[0].chain = NULL;
e = register_commands_with_data(cmd_ctx, NULL, dap_commands, dap);
- if (ERROR_OK != e)
+ if (e != ERROR_OK)
return JIM_ERR;
list_add_tail(&dap->lh, &all_dap);
COMMAND_REGISTRATION_DONE
};
e = register_commands_with_data(cmd_ctx, NULL, obj_commands, obj);
- if (ERROR_OK != e)
+ if (e != ERROR_OK)
return JIM_ERR;
list_add_tail(&obj->lh, &all_tpiu_swo);
}
unsigned int cmd_idx = 0;
- if (CMD_ARGC == cmd_idx)
+ if (cmd_idx == CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
if (!strcmp(CMD_ARGV[cmd_idx], "disable")) {
const char *pin_clk = NULL;
if (!strcmp(CMD_ARGV[cmd_idx], "internal")) {
cmd_idx++;
- if (CMD_ARGC == cmd_idx)
+ if (cmd_idx == CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
output = CMD_ARGV[cmd_idx];
} else if (strcmp(CMD_ARGV[cmd_idx], "external"))
return ERROR_COMMAND_SYNTAX_ERROR;
cmd_idx++;
- if (CMD_ARGC == cmd_idx)
+ if (cmd_idx == CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
if (!strcmp(CMD_ARGV[cmd_idx], "sync")) {
protocol = CMD_ARGV[cmd_idx];
cmd_idx++;
- if (CMD_ARGC == cmd_idx)
+ if (cmd_idx == CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
port_width = CMD_ARGV[cmd_idx];
} else {
return ERROR_COMMAND_SYNTAX_ERROR;
protocol = CMD_ARGV[cmd_idx];
cmd_idx++;
- if (CMD_ARGC == cmd_idx)
+ if (cmd_idx == CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
formatter = CMD_ARGV[cmd_idx];
}
cmd_idx++;
- if (CMD_ARGC == cmd_idx)
+ if (cmd_idx == CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
trace_clk = CMD_ARGV[cmd_idx];
cmd_idx++;
- if (CMD_ARGC != cmd_idx) {
+ if (cmd_idx != CMD_ARGC) {
pin_clk = CMD_ARGV[cmd_idx];
cmd_idx++;
}
- if (CMD_ARGC != cmd_idx)
+ if (cmd_idx != CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
LOG_INFO(MSG "Running: \'%s configure -protocol %s -traceclk %s" "%s%s" "%s%s" "%s%s" "%s%s\'",
/* Read register */
int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + reg, &tmp);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* clear bitfield */
/* Read DSCR */
int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* clear bitfield */
/* Disable interrupts during single step if requested */
if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, DSCR_INT_DIS);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
/* Re-enable interrupts if they were disabled */
if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, 0);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) {
int retval = register_commands(CMD_CTX, NULL,
etm_capture_drivers[i]->commands);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
free(etm_ctx);
return retval;
}
/* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
/* endianness, but byte array should represent target endianness */
- if (ERROR_OK == retval) {
+ if (retval == ERROR_OK) {
switch (size) {
case 4:
target_buffer_set_u32_array(target, buffer, count, t);
free(t);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return ERROR_OK;
retval = mips64_pracc_read_mem(ejtag_info, address, size, count,
(void *)t);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("mips64_pracc_read_mem filed");
goto read_done;
}
reg->dirty = false;
/* update registers to take effect right now */
- if (IR0 == mapped_regnum) {
+ if (mapped_regnum == IR0) {
nds32_update_psw(nds32);
- } else if (MR0 == mapped_regnum) {
+ } else if (mapped_regnum == MR0) {
nds32_update_mmu_info(nds32);
- } else if ((MR6 == mapped_regnum) || (MR7 == mapped_regnum)) {
+ } else if ((mapped_regnum == MR6) || (mapped_regnum == MR7)) {
/* update lm information */
nds32_update_lm_info(nds32);
- } else if (MR8 == mapped_regnum) {
+ } else if (mapped_regnum == MR8) {
nds32_update_cache_info(nds32);
- } else if (FUCPR == mapped_regnum) {
+ } else if (mapped_regnum == FUCPR) {
/* update audio/fpu setting */
nds32_check_extension(nds32);
}
nds32_step_without_watchpoint(nds32);
/* before single_step, save exception address */
- if (ERROR_OK != result)
+ if (result != ERROR_OK)
return ERROR_FAIL;
target->debug_reason = DBG_REASON_WATCHPOINT;
if (nds32_target_state(nds32, &state) != ERROR_OK)
return ERROR_FAIL;
- if (TARGET_HALTED != state)
+ if (state != TARGET_HALTED)
/* TODO: if state == TARGET_HALTED, check ETYPE is DBGI or not */
if (ERROR_OK != aice_halt(aice))
return ERROR_FAIL;
uint32_t cur_level = nds32->current_interrupt_level;
if ((1 <= cur_level) && (cur_level < max_level)) {
- if (IR0 == reg_no) {
+ if (reg_no == IR0) {
LOG_DEBUG("Map PSW to IPSW");
return IR1;
- } else if (PC == reg_no) {
+ } else if (reg_no == PC) {
LOG_DEBUG("Map PC to IPC");
return IR9;
}
} else if ((2 <= cur_level) && (cur_level < max_level)) {
- if (R26 == reg_no) {
+ if (reg_no == R26) {
LOG_DEBUG("Mapping P0 to P_P0");
return IR12;
- } else if (R27 == reg_no) {
+ } else if (reg_no == R27) {
LOG_DEBUG("Mapping P1 to P_P1");
return IR13;
- } else if (IR1 == reg_no) {
+ } else if (reg_no == IR1) {
LOG_DEBUG("Mapping IPSW to P_IPSW");
return IR2;
- } else if (IR4 == reg_no) {
+ } else if (reg_no == IR4) {
LOG_DEBUG("Mapping EVA to P_EVA");
return IR5;
- } else if (IR6 == reg_no) {
+ } else if (reg_no == IR6) {
LOG_DEBUG("Mapping ITYPE to P_ITYPE");
return IR7;
- } else if (IR9 == reg_no) {
+ } else if (reg_no == IR9) {
LOG_DEBUG("Mapping IPC to P_IPC");
return IR10;
}
} else if (cur_level == max_level) {
- if (PC == reg_no) {
+ if (reg_no == PC) {
LOG_DEBUG("Mapping PC to O_IPC");
return IR11;
}
return ERROR_OK;
} else if (breakpoint->type == BKPT_SOFT) {
result = nds32_add_software_breakpoint(target, breakpoint);
- if (ERROR_OK != result) {
+ if (result != ERROR_OK) {
/* auto convert to hardware breakpoint if failed */
if (nds32->auto_convert_hw_bp) {
/* convert to hardware breakpoint */
return ERROR_OK;
} else if (breakpoint->type == BKPT_SOFT) {
result = nds32_add_software_breakpoint(target, breakpoint);
- if (ERROR_OK != result) {
+ if (result != ERROR_OK) {
/* auto convert to hardware breakpoint if failed */
if (nds32->auto_convert_hw_bp) {
/* convert to hardware breakpoint */
nds32_get_mapped_reg(nds32, PC, &val_pc);
- if ((NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE == reason) ||
- (NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE == reason)) {
+ if ((reason == NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE) ||
+ (reason == NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE)) {
if (edmsw & 0x4) /* check EDMSW.IS_16BIT */
val_pc -= 2;
else
return ERROR_FAIL;
} else if (match_count == 0) {
/* global stop is precise exception */
- if ((NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP == reason) && nds32->global_stop) {
+ if ((reason == NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP) && nds32->global_stop) {
/* parse instruction to get correct access address */
uint32_t val_pc;
uint32_t opcode;
int result;
result = nds32_gdb_fileio_write_memory(nds32, address, size, buffer);
- if (NDS_MEMORY_ACC_CPU == origin_access_channel) {
+ if (origin_access_channel == NDS_MEMORY_ACC_CPU) {
memory->access_channel = NDS_MEMORY_ACC_CPU;
aice_memory_access(aice, NDS_MEMORY_ACC_CPU);
}
return ERROR_OK;
} else if (breakpoint->type == BKPT_SOFT) {
result = nds32_add_software_breakpoint(target, breakpoint);
- if (ERROR_OK != result) {
+ if (result != ERROR_OK) {
/* auto convert to hardware breakpoint if failed */
if (nds32->auto_convert_hw_bp) {
/* convert to hardware breakpoint */
int retval = target_register_timer_callback(&jsp_poll_read, 1,
TARGET_TIMER_TYPE_PERIODIC, jsp_service);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return ERROR_OK;
struct jsp_service *jsp_service = connection->service->priv;
int retval = target_unregister_timer_callback(&jsp_poll_read, jsp_service);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
free(connection->priv);
if (CMD_ARGC == 1) {
int coreid = 0;
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target->gdb_service->core[1] = coreid;
assert(type->init_target != NULL);
int retval = type->init_target(cmd_ctx, target);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("target '%s' init failed", target_name(target));
return retval;
}
for (target = all_targets; target; target = target->next) {
retval = target_init_one(cmd_ctx, target);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
retval = target_register_user_commands(cmd_ctx);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = target_register_timer_callback(&handle_target,
polling_interval, TARGET_TIMER_TYPE_PERIODIC, cmd_ctx->interp);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
return ERROR_OK;
target_initialized = true;
retval = command_run_line(CMD_CTX, "init_targets");
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = command_run_line(CMD_CTX, "init_target_events");
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = command_run_line(CMD_CTX, "init_board");
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
LOG_DEBUG("Initializing targets...");
unsigned ms = DEFAULT_HALT_TIMEOUT;
if (1 == CMD_ARGC) {
int retval = parse_uint(CMD_ARGV[0], &ms);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_COMMAND_SYNTAX_ERROR;
}
target->verbose_halt_msg = true;
int retval = target_halt(target);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (CMD_ARGC == 1) {
unsigned wait_local;
retval = parse_uint(CMD_ARGV[0], &wait_local);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_COMMAND_SYNTAX_ERROR;
if (!wait_local)
return ERROR_OK;
struct target *target = get_current_target(CMD_CTX);
int retval = fn(target, address, size, count, buffer);
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
target_handle_md_output(CMD, target, address, size, count, buffer);
free(buffer);
int retval = CALL_COMMAND_HANDLER(parse_load_image_command_CMD_ARGV,
&image, &min_address, &max_address);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct target *target = get_current_target(CMD_CTX);
free(buffer);
}
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "downloaded %" PRIu32 " bytes "
"in %fs (%0.3f KiB/s)", image_size,
duration_elapsed(&bench), duration_kbps(&bench, image_size));
free(buffer);
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
size_t filesize;
retval = fileio_size(fileio, &filesize);
if (retval != ERROR_OK)
done:
if (diffs > 0)
retval = ERROR_FAIL;
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "verified %" PRIu32 " bytes "
"in %fs (%0.3f KiB/s)", image_size,
duration_elapsed(&bench), duration_kbps(&bench, image_size));
if (asid == 0) {
retval = breakpoint_add(target, addr, length, hw);
/* error is always logged in breakpoint_add(), do not print it again */
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
command_print(cmd, "breakpoint set at " TARGET_ADDR_FMT "", addr);
} else if (addr == 0) {
}
retval = context_breakpoint_add(target, asid, length, hw);
/* error is always logged in context_breakpoint_add(), do not print it again */
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
command_print(cmd, "Context breakpoint set at 0x%8.8" PRIx32 "", asid);
} else {
}
retval = hybrid_breakpoint_add(target, addr, asid, length, hw);
/* error is always logged in hybrid_breakpoint_add(), do not print it again */
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
command_print(cmd, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid);
}
return retval;
int retval = watchpoint_add(target, addr, length, type,
data_value, data_mask);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
LOG_ERROR("Failure setting watchpoints");
return retval;
/* create the target specific commands */
if (target->type->commands) {
e = register_commands(cmd_ctx, NULL, target->type->commands);
- if (ERROR_OK != e)
+ if (e != ERROR_OK)
LOG_ERROR("unable to register '%s' commands", cp);
}
int retval = CALL_COMMAND_HANDLER(parse_load_image_command_CMD_ARGV,
&image, &min_address, &max_address);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
struct duration bench;
free(buffer);
}
- if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD, "Loaded %" PRIu32 " bytes "
"in %fs (%0.3f KiB/s)", image_size,
duration_elapsed(&bench), duration_kbps(&bench, image_size));
uint8_t *buffer = calloc(count, size);
struct target *target = get_current_target(CMD_CTX);
int retval = x86_32_common_read_io(target, address, size, buffer);
- if (ERROR_OK == retval)
+ if (retval == ERROR_OK)
handle_iod_output(CMD, target, address, size, count, buffer);
free(buffer);
return retval;
projects / fw / openocd / commitdiff