David Brownell <david-b@pacbell.net> target config file for newish DM365 chip. Think...

an improved DM355, integrating much better HD video support,
Ethernet, and other goodies.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2351 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
new file mode 100644 (file)
index 0000000..f889432
--- /dev/null
+++ b/tcl/target/ti_dm365.cfg
@@ -0,0 +1,97 @@
+#\r
+# Texas Instruments DaVinci family:  TMS320DM365\r
+#\r
+if { [info exists CHIPNAME] } {\r
+   set  _CHIPNAME $CHIPNAME\r
+} else {\r
+   set  _CHIPNAME dm365\r
+}\r
+\r
+#\r
+# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB\r
+# are enabled without making ICEpick route ARM and ETB into the JTAG chain.\r
+#\r
+# Also note:  when running without RTCK before the PLLs are set up, you\r
+# may need to slow the JTAG clock down quite a lot (under 2 MHz).\r
+#\r
+source [find target/icepick.cfg]\r
+set EMU01 "-enable"\r
+#set EMU01 "-disable"\r
+\r
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\r
+if { [info exists ETB_TAPID ] } {\r
+   set _ETB_TAPID $ETB_TAPID\r
+} else {\r
+   set _ETB_TAPID 0x2b900f0f\r
+}\r
+jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \\r
+       -expected-id $_ETB_TAPID $EMU01\r
+jtag configure $_CHIPNAME.etb -event tap-enable \\r
+       "icepick_c_tapenable $_CHIPNAME.jrc 1"\r
+\r
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\r
+if { [info exists CPU_TAPID ] } {\r
+   set _CPU_TAPID $CPU_TAPID\r
+} else {\r
+   set _CPU_TAPID 0x0792602f\r
+}\r
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \\r
+       -expected-id $_CPU_TAPID $EMU01\r
+jtag configure $_CHIPNAME.arm -event tap-enable \\r
+       "icepick_c_tapenable $_CHIPNAME.jrc 0"\r
+\r
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan\r
+if { [info exists JRC_TAPID ] } {\r
+   set _JRC_TAPID $JRC_TAPID\r
+} else {\r
+   set _JRC_TAPID 0x0b83e02f\r
+}\r
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\r
+       -expected-id $_JRC_TAPID\r
+\r
+################\r
+\r
+# various symbol definitions, to avoid hard-wiring addresses\r
+# and enable some sharing of DaVinci-family utility code\r
+global dm365\r
+set dm365 [ dict create ]\r
+\r
+# Physical addresses for controllers and memory\r
+# (Some of these are valid for many DaVinci family chips)\r
+dict set dm365 sram0           0x00010000\r
+dict set dm365 sram1           0x00014000\r
+dict set dm365 sysbase         0x01c40000\r
+dict set dm365 pllc1           0x01c40800\r
+dict set dm365 pllc2           0x01c40c00\r
+dict set dm365 psc             0x01c41000\r
+dict set dm365 gpio            0x01c67000\r
+dict set dm365 a_emif          0x01d10000\r
+dict set dm365 a_emif_cs0      0x02000000\r
+dict set dm365 a_emif_cs1      0x04000000\r
+dict set dm365 ddr_emif                0x20000000\r
+dict set dm365 ddr             0x80000000\r
+\r
+source [find target/davinci.cfg]\r
+\r
+################\r
+# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)\r
+# and the ETB memory (4K) are other options, while trace is unused.\r
+set _TARGETNAME $_CHIPNAME.arm\r
+\r
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME\r
+\r
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,\r
+# and that the work area is used only with a kernel mmu context ...\r
+$_TARGETNAME configure \\r
+       -work-area-virt [expr 0xfffe0000 + 0x4000] \\r
+       -work-area-phys [dict get $dm365 sram1] \\r
+       -work-area-size 0x4000 \\r
+       -work-area-backup 0\r
+\r
+arm7_9 dbgrq enable\r
+arm7_9 fast_memory_access enable\r
+arm7_9 dcc_downloads enable\r
+\r
+# trace setup\r
+etm config $_TARGETNAME 16 normal full etb\r
+etb config $_TARGETNAME $_CHIPNAME.etb\r