* device/include/mcs51/c8051f410.h: new SiLabs mcu

* src/ds390/peeph.def: disabled 186.d and 227.a as fix for #1434401
* support/regression/tests/array.c: added parenthesis, made arrays unsigned

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4055 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/ChangeLog b/ChangeLog
index fc85b125478e19b163b734ca28c17ac687e94d34..dd69bc630ff822e60e2aac29cd127b995d715303 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2006-03-07 Maarten Brock <sourceforge.brock AT dse.nl>
+
+       * device/include/mcs51/c8051f410.h: new SiLabs mcu
+       * src/ds390/peeph.def: disabled 186.d and 227.a as fix for #1434401
+       * support/regression/tests/array.c: added parenthesis, made arrays unsigned
+
 2006-03-06 Borut Razem <borut.razem AT siol.net>
 
        * support/regression/ports/pic16/spec.mk: link with libm18f.lib,
@@ -28,7 +34,7 @@
        --extended or -y for Extended Instruction Support,
        * src/pic16/ralloc.c (pic16_decodeOp): added case for FUNCTION,
        (deassignLRs): *** perhaps the most important change, old 'for' code
-       (comented out for reference), didn't account for some registers which
+       (commented out for reference), didn't account for some registers which
        were left marked 'not free' after a pointer operation. The change
        reduces register usage a lot in some cases
 

diff --git a/device/include/mcs51/c8051f410.h b/device/include/mcs51/c8051f410.h
new file mode 100644 (file)
index 0000000..76db978
--- /dev/null
+++ b/device/include/mcs51/c8051f410.h
@@ -0,0 +1,363 @@
+/*-------------------------------------------------------------------------
+   Register Declarations for the SiLabs C8051F41x Processor Range
+
+   Copyright (C) 2006 - Maarten Brock, sourceforge.brock@dse.nl
+
+   This library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   This library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with this library; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+-------------------------------------------------------------------------*/
+
+#ifndef C8051F410_H
+#define C8051F410_H
+
+
+/*  BYTE Registers  */
+
+__sfr __at (0x80) P0           ;  /* PORT 0                                        */
+__sfr __at (0x81) SP           ;  /* STACK POINTER                                 */
+__sfr __at (0x82) DPL          ;  /* DATA POINTER - LOW BYTE                       */
+__sfr __at (0x83) DPH          ;  /* DATA POINTER - HIGH BYTE                      */
+__sfr __at (0x84) CRC0CN       ;  /* CRC 0 CONTROL                                 */
+__sfr __at (0x85) CRC0IN       ;  /* CRC 0 DATA INPUT                              */
+__sfr __at (0x86) CRC0DAT      ;  /* CRC 0 DATA OUTPUT                             */
+__sfr __at (0x87) PCON         ;  /* POWER CONTROL                                 */
+__sfr __at (0x88) TCON         ;  /* TIMER CONTROL                                 */
+__sfr __at (0x89) TMOD         ;  /* TIMER MODE                                    */
+__sfr __at (0x8A) TL0          ;  /* TIMER 0 - LOW BYTE                            */
+__sfr __at (0x8B) TL1          ;  /* TIMER 1 - LOW BYTE                            */
+__sfr __at (0x8C) TH0          ;  /* TIMER 0 - HIGH BYTE                           */
+__sfr __at (0x8D) TH1          ;  /* TIMER 1 - HIGH BYTE                           */
+__sfr __at (0x8E) CKCON        ;  /* CLOCK CONTROL                                 */
+__sfr __at (0x8F) PSCTL        ;  /* PROGRAM STORE R/W CONTROL                     */
+__sfr __at (0x90) P1           ;  /* PORT 1                                        */
+__sfr __at (0x91) TMR3CN       ;  /* TIMER 3 CONTROL                               */
+__sfr __at (0x92) TMR3RLL      ;  /* TIMER 3 CAPTURE REGISTER - LOW BYTE           */
+__sfr __at (0x93) TMR3RLH      ;  /* TIMER 3 CAPTURE REGISTER - HIGH BYTE          */
+__sfr __at (0x94) TMR3L        ;  /* TIMER 3 - LOW BYTE                            */
+__sfr __at (0x95) TMR3H        ;  /* TIMER 3 - HIGH BYTE                           */
+__sfr __at (0x96) IDA0L        ;  /* CURRENT MODE DAC 0 - LOW BYTE                 */
+__sfr __at (0x97) IDA0H        ;  /* CURRENT MODE DAC 0 - HIGH BYTE                */
+__sfr __at (0x98) SCON         ;  /* SERIAL PORT CONTROL                           */
+__sfr __at (0x98) SCON0        ;  /* SERIAL PORT CONTROL                           */
+__sfr __at (0x99) SBUF         ;  /* SERIAL PORT BUFFER                            */
+__sfr __at (0x99) SBUF0        ;  /* SERIAL PORT BUFFER                            */
+__sfr __at (0x9A) CPT1CN       ;  /* COMPARATOR 1 CONTROL                          */
+__sfr __at (0x9B) CPT0CN       ;  /* COMPARATOR 0 CONTROL                          */
+__sfr __at (0x9C) CPT1MD       ;  /* COMPARATOR 1 MODE SELECTION                   */
+__sfr __at (0x9D) CPT0MD       ;  /* COMPARATOR 0 MODE SELECTION                   */
+__sfr __at (0x9E) CPT1MX       ;  /* COMPARATOR 1 MUX SELECTION                    */
+__sfr __at (0x9F) CPT0MX       ;  /* COMPARATOR 0 MUX SELECTION                    */
+__sfr __at (0xA0) P2           ;  /* PORT 2                                        */
+__sfr __at (0xA1) SPI0CFG      ;  /* SPI0 CONFIGURATION                            */
+__sfr __at (0xA2) SPI0CKR      ;  /* SPI0 CLOCK RATE CONTROL                       */
+__sfr __at (0xA3) SPI0DAT      ;  /* SPI0 DATA                                     */
+__sfr __at (0xA4) P0MDOUT      ;  /* PORT 0 OUTPUT MODE CONFIGURATION              */
+__sfr __at (0xA5) P1MDOUT      ;  /* PORT 1 OUTPUT MODE CONFIGURATION              */
+__sfr __at (0xA6) P2MDOUT      ;  /* PORT 2 OUTPUT MODE CONFIGURATION              */
+__sfr __at (0xA8) IE           ;  /* INTERRUPT ENABLE                              */
+__sfr __at (0xA9) CLKSEL       ;  /* SYSTEM CLOCK SELECT                           */
+__sfr __at (0xAA) EMI0CN       ;  /* EXTERNAL MEMORY INTERFACE CONTROL             */
+__sfr __at (0xAA) _XPAGE       ;  /* XDATA/PDATA PAGE                              */
+__sfr __at (0xAB) CLKMUL       ;  /* CLOCK MULTIPLIER                              */
+__sfr __at (0xAC) RTC0ADR      ;  /* SMARTCLOCK ADDRESS                            */
+__sfr __at (0xAD) RTC0DAT      ;  /* SMARTCLOCK DATA                               */
+__sfr __at (0xAE) RTC0KEY      ;  /* SMARTCLOCK LOCK AND KEY                       */
+__sfr __at (0xAF) ONESHOT      ;  /* FLASH ONESHOT PERIOD                          */
+__sfr __at (0xB0) P0ODEN       ;  /* PORT 0 OVERDRIVE                              */
+__sfr __at (0xB1) OSCXCN       ;  /* EXTERNAL OSCILLATOR CONTROL                   */
+__sfr __at (0xB2) OSCICN       ;  /* INTERNAL OSCILLATOR CONTROL                   */
+__sfr __at (0xB3) OSCICL       ;  /* INTERNAL OSCILLATOR CALIBRATION               */
+__sfr __at (0xB5) IDA1CN       ;  /* CURRENT MODE DAC 1 - CONTROL                  */
+__sfr __at (0xB6) FLSCL        ;  /* FLASH MEMORY TIMING PRESCALER                 */
+__sfr __at (0xB7) FLKEY        ;  /* FLASH ACESS LIMIT                             */
+__sfr __at (0xB8) IP           ;  /* INTERRUPT PRIORITY                            */
+__sfr __at (0xB9) IDA0CN       ;  /* CURRENT MODE DAC 0 - CONTROL                  */
+__sfr __at (0xBA) ADC0TK       ;  /* ADC 0 TRACKING MODE SELECT                    */
+__sfr __at (0xBB) ADC0MX       ;  /* ADC 0 CHANNEL SELECT                          */
+__sfr __at (0xBC) ADC0CF       ;  /* ADC 0 CONFIGURATION                           */
+__sfr __at (0xBD) ADC0L        ;  /* ADC 0 DATA WORD LSB                           */
+__sfr __at (0xBE) ADC0H        ;  /* ADC 0 DATA WORD MSB                           */
+__sfr __at (0xBF) P1MASK       ;  /* PORT 1 MASK                                   */
+__sfr __at (0xC0) SMB0CN       ;  /* SMBUS CONTROL                                 */
+__sfr __at (0xC1) SMB0CF       ;  /* SMBUS CONFIGURATION                           */
+__sfr __at (0xC2) SMB0DAT      ;  /* SMBUS DATA                                    */
+__sfr __at (0xC3) ADC0GTL      ;  /* ADC 0 GREATER-THAN LOW BYTE                   */
+__sfr __at (0xC4) ADC0GTH      ;  /* ADC 0 GREATER-THAN HIGH BYTE                  */
+__sfr __at (0xC5) ADC0LTL      ;  /* ADC 0 LESS-THAN LOW BYTE                      */
+__sfr __at (0xC6) ADC0LTH      ;  /* ADC 0 LESS-THAN HIGH BYTE                     */
+__sfr __at (0xC7) P0MASK       ;  /* PORT 0 MASK                                   */
+__sfr __at (0xC8) T2CON        ;  /* TIMER 2 CONTROL                               */
+__sfr __at (0xC8) TMR2CN       ;  /* TIMER 2 CONTROL                               */
+__sfr __at (0xC9) REG0CN       ;  /* VOLTAGE REGULATOR CONTROL                     */
+__sfr __at (0xCA) RCAP2L       ;  /* TIMER 2 CAPTURE REGISTER - LOW BYTE           */
+__sfr __at (0xCA) TMR2RLL      ;  /* TIMER 2 CAPTURE REGISTER - LOW BYTE           */
+__sfr __at (0xCB) RCAP2H       ;  /* TIMER 2 CAPTURE REGISTER - HIGH BYTE          */
+__sfr __at (0xCB) TMR2RLH      ;  /* TIMER 2 CAPTURE REGISTER - HIGH BYTE          */
+__sfr __at (0xCC) TL2          ;  /* TIMER 2 - LOW BYTE                            */
+__sfr __at (0xCC) TMR2L        ;  /* TIMER 2 - LOW BYTE                            */
+__sfr __at (0xCD) TH2          ;  /* TIMER 2 - HIGH BYTE                           */
+__sfr __at (0xCD) TMR2H        ;  /* TIMER 2 - HIGH BYTE                           */
+__sfr __at (0xCE) PCA0CPM5     ;  /* PCA MODULE 5 MODE REGISTER                    */
+__sfr __at (0xCF) P1MAT        ;  /* PORT 1 MATCH                                  */
+__sfr __at (0xD0) PSW          ;  /* PROGRAM STATUS WORD                           */
+__sfr __at (0xD1) REF0CN       ;  /* VOLTAGE REFERENCE 0 CONTROL                   */
+__sfr __at (0xD2) PCA0CPL5     ;  /* PCA CAPTURE 5 LOW                             */
+__sfr __at (0xD3) PCA0CPH5     ;  /* PCA CAPTURE 5 HIGH                            */
+__sfr __at (0xD4) P0SKIP       ;  /* PORT 0 SKIP                                   */
+__sfr __at (0xD5) P1SKIP       ;  /* PORT 1 SKIP                                   */
+__sfr __at (0xD6) P2SKIP       ;  /* PORT 2 SKIP                                   */
+__sfr __at (0xD7) P0MAT        ;  /* PORT 0 MATCH                                  */
+__sfr __at (0xD8) PCA0CN       ;  /* PCA CONTROL                                   */
+__sfr __at (0xD9) PCA0MD       ;  /* PCA MODE                                      */
+__sfr __at (0xDA) PCA0CPM0     ;  /* PCA MODULE 0 MODE REGISTER                    */
+__sfr __at (0xDB) PCA0CPM1     ;  /* PCA MODULE 1 MODE REGISTER                    */
+__sfr __at (0xDC) PCA0CPM2     ;  /* PCA MODULE 2 MODE REGISTER                    */
+__sfr __at (0xDD) PCA0CPM3     ;  /* PCA MODULE 3 MODE REGISTER                    */
+__sfr __at (0xDE) PCA0CPM4     ;  /* PCA MODULE 4 MODE REGISTER                    */
+__sfr __at (0xDF) CRC0FLIP     ;  /* CRC 0 BIT FLIP                                */
+__sfr __at (0xE0) ACC          ;  /* ACCUMULATOR                                   */
+__sfr __at (0xE1) XBR0         ;  /* PORT MUX CONFIGURATION REGISTER 0             */
+__sfr __at (0xE2) XBR1         ;  /* PORT MUX CONFIGURATION REGISTER 1             */
+__sfr __at (0xE3) PFE0CN       ;  /* PREFETCH ENGINE CONTROL                       */
+__sfr __at (0xE4) IT01CF       ;  /* INT0/INT1 CONFIGURATION REGISTER              */
+__sfr __at (0xE4) INT01CF      ;  /* INT0/INT1 CONFIGURATION REGISTER              */
+__sfr __at (0xE6) EIE1         ;  /* EXTERNAL INTERRUPT ENABLE 1                   */
+__sfr __at (0xE7) EIE2         ;  /* EXTERNAL INTERRUPT ENABLE 2                   */
+__sfr __at (0xE8) ADC0CN       ;  /* ADC 0 CONTROL                                 */
+__sfr __at (0xE9) PCA0CPL1     ;  /* PCA CAPTURE 1 LOW                             */
+__sfr __at (0xEA) PCA0CPH1     ;  /* PCA CAPTURE 1 HIGH                            */
+__sfr __at (0xEB) PCA0CPL2     ;  /* PCA CAPTURE 2 LOW                             */
+__sfr __at (0xEC) PCA0CPH2     ;  /* PCA CAPTURE 2 HIGH                            */
+__sfr __at (0xED) PCA0CPL3     ;  /* PCA CAPTURE 3 LOW                             */
+__sfr __at (0xEE) PCA0CPH3     ;  /* PCA CAPTURE 3 HIGH                            */
+__sfr __at (0xEF) RSTSRC       ;  /* RESET SOURCE                                  */
+__sfr __at (0xF0) B            ;  /* B REGISTER                                    */
+__sfr __at (0xF1) P0MODE       ;  /* PORT 0 INPUT MODE CONFIGURATION               */
+__sfr __at (0xF1) P0MDIN       ;  /* PORT 0 INPUT MODE CONFIGURATION               */
+__sfr __at (0xF2) P1MODE       ;  /* PORT 1 INPUT MODE CONFIGURATION               */
+__sfr __at (0xF2) P1MDIN       ;  /* PORT 1 INPUT MODE CONFIGURATION               */
+__sfr __at (0xF3) P2MODE       ;  /* PORT 2 INPUT MODE CONFIGURATION               */
+__sfr __at (0xF3) P2MDIN       ;  /* PORT 2 INPUT MODE CONFIGURATION               */
+__sfr __at (0xF4) IDA1L        ;  /* CURRENT MODE DAC 1 - LOW BYTE                 */
+__sfr __at (0xF5) IDA1H        ;  /* CURRENT MODE DAC 1 - HIGH BYTE                */
+__sfr __at (0xF6) EIP1         ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 1        */
+__sfr __at (0xF7) EIP2         ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 2        */
+__sfr __at (0xF8) SPI0CN       ;  /* SPI0 CONTROL                                  */
+__sfr __at (0xF9) PCA0L        ;  /* PCA COUNTER LOW                               */
+__sfr __at (0xFA) PCA0H        ;  /* PCA COUNTER HIGH                              */
+__sfr __at (0xFB) PCA0CPL0     ;  /* PCA CAPTURE 0 LOW                             */
+__sfr __at (0xFC) PCA0CPH0     ;  /* PCA CAPTURE 0 HIGH                            */
+__sfr __at (0xFD) PCA0CPL4     ;  /* PCA CAPTURE 4 LOW                             */
+__sfr __at (0xFE) PCA0CPH4     ;  /* PCA CAPTURE 4 HIGH                            */
+__sfr __at (0xFF) VDM0CN       ;  /* VDD MONITOR CONTROL                           */
+
+
+/*  WORD/DWORD Registers  */
+
+__sfr16 __at (0x8C8A) TMR0     ;  /* TIMER 0 COUNTER                               */
+__sfr16 __at (0x8D8B) TMR1     ;  /* TIMER 1 COUNTER                               */
+__sfr16 __at (0xCDCC) TMR2     ;  /* TIMER 2 COUNTER                               */
+__sfr16 __at (0xCBCA) RCAP2    ;  /* TIMER 2 CAPTURE REGISTER WORD                 */
+__sfr16 __at (0xCBCA) TMR2RL   ;  /* TIMER 2 CAPTURE REGISTER WORD                 */
+__sfr16 __at (0x9594) TMR3     ;  /* TIMER 3 COUNTER                               */
+__sfr16 __at (0x9392) TMR3RL   ;  /* TIMER 3 CAPTURE REGISTER WORD                 */
+__sfr16 __at (0x9796) IDA0     ;  /* CURRENT MODE DAC 0 DATA WORD                  */
+__sfr16 __at (0xF5F4) IDA1     ;  /* CURRENT MODE DAC 1 DATA WORD                  */
+__sfr16 __at (0xBEBD) ADC0     ;  /* ADC 0 DATA WORD                               */
+__sfr16 __at (0xC4C3) ADC0GT   ;  /* ADC 0 GREATER-THAN REGISTER WORD              */
+__sfr16 __at (0xC6C5) ADC0LT   ;  /* ADC 0 LESS-THAN REGISTER WORD                 */
+__sfr16 __at (0xFAF9) PCA0     ;  /* PCA COUNTER                                   */
+__sfr16 __at (0xFCFB) PCA0CP0  ;  /* PCA CAPTURE 0 WORD                            */
+__sfr16 __at (0xEAE9) PCA0CP1  ;  /* PCA CAPTURE 1 WORD                            */
+__sfr16 __at (0xECEB) PCA0CP2  ;  /* PCA CAPTURE 2 WORD                            */
+__sfr16 __at (0xEEED) PCA0CP3  ;  /* PCA CAPTURE 3 WORD                            */
+__sfr16 __at (0xFEFD) PCA0CP4  ;  /* PCA CAPTURE 4 WORD                            */
+__sfr16 __at (0xD3D2) PCA0CP5  ;  /* PCA CAPTURE 5 WORD                            */
+
+
+/*  BIT Registers  */
+
+/*  P0  0x80 */
+__sbit __at (0x80) P0_0        ;
+__sbit __at (0x81) P0_1        ;
+__sbit __at (0x82) P0_2        ;
+__sbit __at (0x83) P0_3        ;
+__sbit __at (0x84) P0_4        ;
+__sbit __at (0x85) P0_5        ;
+__sbit __at (0x86) P0_6        ;
+__sbit __at (0x87) P0_7        ;
+
+/*  TCON  0x88 */
+__sbit __at (0x88) IT0         ;  /* TCON.0 - EXT. INTERRUPT 0 TYPE                */
+__sbit __at (0x89) IE0         ;  /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG           */
+__sbit __at (0x8A) IT1         ;  /* TCON.2 - EXT. INTERRUPT 1 TYPE                */
+__sbit __at (0x8B) IE1         ;  /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG           */
+__sbit __at (0x8C) TR0         ;  /* TCON.4 - TIMER 0 ON/OFF CONTROL               */
+__sbit __at (0x8D) TF0         ;  /* TCON.5 - TIMER 0 OVERFLOW FLAG                */
+__sbit __at (0x8E) TR1         ;  /* TCON.6 - TIMER 1 ON/OFF CONTROL               */
+__sbit __at (0x8F) TF1         ;  /* TCON.7 - TIMER 1 OVERFLOW FLAG                */
+
+/*  P1  0x90 */
+__sbit __at (0x90) P1_0        ;
+__sbit __at (0x91) P1_1        ;
+__sbit __at (0x92) P1_2        ;
+__sbit __at (0x93) P1_3        ;
+__sbit __at (0x94) P1_4        ;
+__sbit __at (0x95) P1_5        ;
+__sbit __at (0x96) P1_6        ;
+__sbit __at (0x97) P1_7        ;
+
+/*  SCON  0x98 */
+__sbit __at (0x98) RI          ;  /* SCON.0 - RECEIVE INTERRUPT FLAG               */
+__sbit __at (0x98) RI0         ;  /* SCON.0 - RECEIVE INTERRUPT FLAG               */
+__sbit __at (0x99) TI          ;  /* SCON.1 - TRANSMIT INTERRUPT FLAG              */
+__sbit __at (0x99) TI0         ;  /* SCON.1 - TRANSMIT INTERRUPT FLAG              */
+__sbit __at (0x9A) RB8         ;  /* SCON.2 - RECEIVE BIT 8                        */
+__sbit __at (0x9A) RB80        ;  /* SCON.2 - RECEIVE BIT 8                        */
+__sbit __at (0x9B) TB8         ;  /* SCON.3 - TRANSMIT BIT 8                       */
+__sbit __at (0x9B) TB80        ;  /* SCON.3 - TRANSMIT BIT 8                       */
+__sbit __at (0x9C) REN         ;  /* SCON.4 - RECEIVE ENABLE                       */
+__sbit __at (0x9C) REN0        ;  /* SCON.4 - RECEIVE ENABLE                       */
+__sbit __at (0x9D) SM2         ;  /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE  */
+__sbit __at (0x9D) MCE0        ;  /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE  */
+__sbit __at (0x9F) SM0         ;  /* SCON.7 - SERIAL MODE CONTROL BIT 0            */
+__sbit __at (0x9F) S0MODE      ;  /* SCON.7 - SERIAL MODE CONTROL BIT 0            */
+
+/*  P2  0xA0 */
+__sbit __at (0xA0) P2_0        ;
+__sbit __at (0xA1) P2_1        ;
+__sbit __at (0xA2) P2_2        ;
+__sbit __at (0xA3) P2_3        ;
+__sbit __at (0xA4) P2_4        ;
+__sbit __at (0xA5) P2_5        ;
+__sbit __at (0xA6) P2_6        ;
+__sbit __at (0xA7) P2_7        ;
+
+/*  IE  0xA8 */
+__sbit __at (0xA8) EX0         ;  /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE            */
+__sbit __at (0xA9) ET0         ;  /* IE.1 - TIMER 0 INTERRUPT ENABLE               */
+__sbit __at (0xAA) EX1         ;  /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE            */
+__sbit __at (0xAB) ET1         ;  /* IE.3 - TIMER 1 INTERRUPT ENABLE               */
+__sbit __at (0xAC) ES          ;  /* IE.4 - SERIAL PORT INTERRUPT ENABLE           */
+__sbit __at (0xAC) ES0         ;  /* IE.4 - SERIAL PORT INTERRUPT ENABLE           */
+__sbit __at (0xAD) ET2         ;  /* IE.5 - TIMER 2 INTERRUPT ENABLE               */
+__sbit __at (0xAE) ESPI0       ;  /* IE.6 - SPI0 INTERRUPT ENABLE                  */
+__sbit __at (0xAF) EA          ;  /* IE.7 - GLOBAL INTERRUPT ENABLE                */
+
+/*  P0ODEN  0xB0 */
+__sbit __at (0xB0) P0OD_0      ;  /* P0ODEN.0 - PORT0.0 OVERDRIVE ENABLE           */
+__sbit __at (0xB1) P0OD_1      ;  /* P0ODEN.1 - PORT0.1 OVERDRIVE ENABLE           */
+__sbit __at (0xB2) P0OD_2      ;  /* P0ODEN.2 - PORT0.2 OVERDRIVE ENABLE           */
+__sbit __at (0xB3) P0OD_3      ;  /* P0ODEN.3 - PORT0.3 OVERDRIVE ENABLE           */
+__sbit __at (0xB4) P0OD_4      ;  /* P0ODEN.4 - PORT0.4 OVERDRIVE ENABLE           */
+__sbit __at (0xB5) P0OD_5      ;  /* P0ODEN.5 - PORT0.5 OVERDRIVE ENABLE           */
+__sbit __at (0xB6) P0OD_6      ;  /* P0ODEN.6 - PORT0.6 OVERDRIVE ENABLE           */
+__sbit __at (0xB7) P0OD_7      ;  /* P0ODEN.7 - PORT0.7 OVERDRIVE ENABLE           */
+
+/*  IP  0xB8 */
+__sbit __at (0xB8) PX0         ;  /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY          */
+__sbit __at (0xB9) PT0         ;  /* IP.1 - TIMER 0 PRIORITY                       */
+__sbit __at (0xBA) PX1         ;  /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY          */
+__sbit __at (0xBB) PT1         ;  /* IP.3 - TIMER 1 PRIORITY                       */
+__sbit __at (0xBC) PS          ;  /* IP.4 - SERIAL PORT PRIORITY                   */
+__sbit __at (0xBC) PS0         ;  /* IP.4 - SERIAL PORT PRIORITY                   */
+__sbit __at (0xBD) PT2         ;  /* IP.5 - TIMER 2 PRIORITY                       */
+__sbit __at (0xBE) PSPI0       ;  /* IP.6 - SPI0 PRIORITY                          */
+
+/*  SMB0CN  0xC0 */
+__sbit __at (0xC0) SI          ;  /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG     */
+__sbit __at (0xC1) ACK         ;  /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG           */
+__sbit __at (0xC2) ARBLOST     ;  /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
+__sbit __at (0xC3) ACKRQ       ;  /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST        */
+__sbit __at (0xC4) STO         ;  /* SMB0CN.4 - SMBUS 0 STOP FLAG                  */
+__sbit __at (0xC5) STA         ;  /* SMB0CN.5 - SMBUS 0 START FLAG                 */
+__sbit __at (0xC6) TXMODE      ;  /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR    */
+__sbit __at (0xC7) MASTER      ;  /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR     */
+
+/*  TMR2CN  0xC8 */
+__sbit __at (0xC8) T2XCLK      ;  /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT      */
+__sbit __at (0xC9) T2RCLK      ;  /* TMR2CN.1 - TIMER 2 CAPTURE MODE               */
+__sbit __at (0xCA) TR2         ;  /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL             */
+__sbit __at (0xCB) T2SPLIT     ;  /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE          */
+__sbit __at (0xCD) TF2CEN      ;  /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
+__sbit __at (0xCD) TF2LEN      ;  /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE  */
+__sbit __at (0xCE) TF2L        ;  /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG     */
+__sbit __at (0xCF) TF2         ;  /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG              */
+__sbit __at (0xCF) TF2H        ;  /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG    */
+
+/*  PSW  0xD0 */
+__sbit __at (0xD0) PARITY      ;  /* PSW.0 - ACCUMULATOR PARITY FLAG               */
+__sbit __at (0xD1) F1          ;  /* PSW.1 - FLAG 1                                */
+__sbit __at (0xD2) OV          ;  /* PSW.2 - OVERFLOW FLAG                         */
+__sbit __at (0xD3) RS0         ;  /* PSW.3 - REGISTER BANK SELECT 0                */
+__sbit __at (0xD4) RS1         ;  /* PSW.4 - REGISTER BANK SELECT 1                */
+__sbit __at (0xD5) F0          ;  /* PSW.5 - FLAG 0                                */
+__sbit __at (0xD6) AC          ;  /* PSW.6 - AUXILIARY CARRY FLAG                  */
+__sbit __at (0xD7) CY          ;  /* PSW.7 - CARRY FLAG                            */
+
+/*  PCA0CN  0xD8 */
+__sbit __at (0xD8) CCF0        ;  /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG  */
+__sbit __at (0xD9) CCF1        ;  /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG  */
+__sbit __at (0xDA) CCF2        ;  /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG  */
+__sbit __at (0xDB) CCF3        ;  /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG  */
+__sbit __at (0xDC) CCF4        ;  /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG  */
+__sbit __at (0xDD) CCF5        ;  /* PCA0CN.5 - PCA MODULE 5 CAPTURE/COMPARE FLAG  */
+__sbit __at (0xDE) CR          ;  /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL      */
+__sbit __at (0xDF) CF          ;  /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG    */
+
+/*  ADC0CN  0xE8 */
+__sbit __at (0xE8) AD0CM0      ;  /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0    */
+__sbit __at (0xE9) AD0CM1      ;  /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1    */
+__sbit __at (0xEA) AD0LJST     ;  /* ADC0CN.2 - ADC 0 LEFT JUSTIFY SELECT          */
+__sbit __at (0xEB) AD0WINT     ;  /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG     */
+__sbit __at (0xEC) AD0BUSY     ;  /* ADC0CN.4 - ADC 0 BUSY FLAG                    */
+__sbit __at (0xED) AD0INT      ;  /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG     */
+__sbit __at (0xEE) BURSTEN     ;  /* ADC0CN.6 - ADC 0 BURST MODE ENABLE            */
+__sbit __at (0xEF) AD0EN       ;  /* ADC0CN.7 - ADC 0 ENABLE                       */
+
+/*  SPI0CN  0xF8 */
+__sbit __at (0xF8) SPIEN       ;  /* SPI0CN.0 - SPI0 ENABLE                        */
+__sbit __at (0xF9) TXBMT       ;  /* SPI0CN.1 - TRANSMIT BUFFER EMPTY              */
+__sbit __at (0xFA) NSSMD0      ;  /* SPI0CN.2 - SLAVE SELECT MODE BIT 0            */
+__sbit __at (0xFB) NSSMD1      ;  /* SPI0CN.3 - SLAVE SELECT MODE BIT 1            */
+__sbit __at (0xFC) RXOVRN      ;  /* SPI0CN.4 - RECEIVE OVERRUN FLAG               */
+__sbit __at (0xFD) MODF        ;  /* SPI0CN.5 - MODE FAULT FLAG                    */
+__sbit __at (0xFE) WCOL        ;  /* SPI0CN.6 - WRITE COLLISION FLAG               */
+__sbit __at (0xFF) SPIF        ;  /* SPI0CN.7 - SPI0 INTERRUPT FLAG                */
+
+
+/* Predefined SFR Bit Masks */
+
+#define PCON_IDLE         0x01    /* PCON                                */
+#define PCON_STOP         0x02    /* PCON                                */
+#define T1M               0x08    /* CKCON                               */
+#define PSWE              0x01    /* PSCTL                               */
+#define PSEE              0x02    /* PSCTL                               */
+#define ECP0              0x20    /* EIE1                                */
+#define PORSF             0x02    /* RSTSRC                              */
+#define SWRSF             0x10    /* RSTSRC                              */
+#define ECCF              0x01    /* PCA0CPMn                            */
+#define PWM               0x02    /* PCA0CPMn                            */
+#define TOG               0x04    /* PCA0CPMn                            */
+#define MAT               0x08    /* PCA0CPMn                            */
+#define CAPN              0x10    /* PCA0CPMn                            */
+#define CAPP              0x20    /* PCA0CPMn                            */
+#define ECOM              0x40    /* PCA0CPMn                            */
+#define PWM16             0x80    /* PCA0CPMn                            */
+#define CP0E              0x10    /* XBR0                                */
+#define CP0OEN            0x10    /* XBR0                                */
+#define CP0AE             0x20    /* XBR0                                */
+#define CP0AOEN           0x20    /* XBR0                                */
+
+#endif

diff --git a/src/ds390/peeph.def b/src/ds390/peeph.def
index 38d81982a41dac746d4b3098d2b0bb0bffcc6789..5f14ad006c92d1a00548abb3d8576548798f15e8 100644 (file)
--- a/src/ds390/peeph.def
+++ b/src/ds390/peeph.def
@@ -11,7 +11,7 @@
 //        push %1
 //} by {
 //        ; Peephole 2     removed pop %1 push %1 (not push pop)
-//        mov  %2,%3 
+//        mov  %2,%3
 //}
 
 //
@@ -164,7 +164,7 @@ replace {
         clr  c
         mov  a,%1
 } by {
-        ; Peephole 106   removed redundant mov 
+        ; Peephole 106   removed redundant mov
         mov  %1,a
         clr  c
 }
@@ -276,7 +276,7 @@ replace {
 %3:
         jnz  %4
 } by {
-        ; Peephole 115   jump optimization 
+        ; Peephole 115   jump optimization
         cjne %1,%2,%3
         sjmp %4
 %3:
@@ -490,22 +490,22 @@ replace {
         jc   %1
 }
 
-replace { 
+replace {
         mov  r%1,@r%2
 } by {
         ; Peephole 130   changed target address mode r%1 to ar%1
         mov  ar%1,@r%2
 }
 
-replace { 
+replace {
         mov  a,%1
         subb a,#0x01
         mov  %2,a
         mov  %1,%2
 } by {
         ; Peephole 131   optimized decrement (not caring for c)
-        dec  %1         
-        mov  %2,%1      
+        dec  %1
+        mov  %2,%1
 }
 
 replace {
@@ -661,7 +661,7 @@ replace {
         clr  c
         addc a,%1
 } by {
-        ; Peephole 145   changed to add without carry  
+        ; Peephole 145   changed to add without carry
         add  a,%1
 }
 
@@ -1141,13 +1141,13 @@ replace {
 }
 
 replace {
-        add  a,#%1
-        mov  dpl,a
-        clr  a
-        addc a,#(%1 >> 8)
-        mov  dph,a
-        clr  a
-        movc a,@a+dptr
+       add  a,#%1
+       mov  dpl,a
+       clr  a
+       addc a,#(%1 >> 8)
+       mov  dph,a
+       clr  a
+       movc a,@a+dptr
        mov  %2,a
        inc  dptr
        clr  a
@@ -1158,32 +1158,33 @@ replace {
        movc a,@a+dptr
        mov  %4,a
        inc  dptr
-       clr  a  
+       clr  a
 } by {
-        ; Peephole 186.a   optimized movc sequence
-        mov  dptr,#%1
+       ; Peephole 186.a   optimized movc sequence
+       mov  dptr,#%1
        mov  b,acc
-        movc a,@a+dptr
+       movc a,@a+dptr
        mov  %2,a
        mov  acc,b
-       inc  dptr       
+       inc  dptr
        movc a,@a+dptr
        mov  %3,a
        mov  acc,b
        inc  dptr
+       movc a,@a+dptr
        mov  %4,a
        mov  acc,b
        inc  dptr
 }
 
 replace {
-        add  a,#%1
-        mov  dpl,a
-        clr  a
-        addc a,#(%1 >> 8)
-        mov  dph,a
-        clr  a
-        movc a,@a+dptr
+       add  a,#%1
+       mov  dpl,a
+       clr  a
+       addc a,#(%1 >> 8)
+       mov  dph,a
+       clr  a
+       movc a,@a+dptr
        mov  %2,a
        inc  dptr
        clr  a
@@ -1192,53 +1193,55 @@ replace {
        inc  dptr
        clr  a
 } by {
-        ; Peephole 186.b   optimized movc sequence
-        mov  dptr,#%1
+       ; Peephole 186.b   optimized movc sequence
+       mov  dptr,#%1
        mov  b,acc
-        movc a,@a+dptr
+       movc a,@a+dptr
        mov  %2,a
        mov  acc,b
-       inc  dptr       
+       inc  dptr
        movc a,@a+dptr
        mov  %3,a
        mov  acc,b
-       inc  dptr       
+       inc  dptr
 }
 
 replace {
-        add  a,#%1
-        mov  dpl,a
-        clr  a
-        addc a,#(%1 >> 8)
-        mov  dph,a
-        clr  a
-        movc a,@a+dptr
+       add  a,#%1
+       mov  dpl,a
+       clr  a
+       addc a,#(%1 >> 8)
+       mov  dph,a
+       clr  a
+       movc a,@a+dptr
        mov  %2,a
        inc  dptr
        clr  a
 } by {
-        ; Peephole 186.c   optimized movc sequence
-        mov  dptr,#%1
+       ; Peephole 186.c   optimized movc sequence
+       mov  dptr,#%1
        mov  b,acc
-        movc a,@a+dptr
+       movc a,@a+dptr
        mov  %2,a
        mov  acc,b
        inc  dptr
 }
 
-replace {
-        add  a,#%1
-        mov  dpl,a
-        clr  a
-        addc a,#(%1 >> 8)
-        mov  dph,a
-        clr  a
-        movc a,@a+dptr
-} by {
-        ; Peephole 186   optimized movc sequence
-        mov  dptr,#%1
-        movc a,@a+dptr
-}
+// disabled due to bug #1434401
+//// char indexed access to: char code table[] = {4,3,2,1};
+//replace {
+//     add  a,#%1
+//     mov  dpl,a
+//     clr  a
+//     addc a,#(%1 >> 8)
+//     mov  dph,a
+//     clr  a
+//     movc a,@a+dptr
+//} by {
+//     ; Peephole 186.d  optimized movc sequence
+//     mov  dptr,#%1
+//     movc a,@a+dptr
+//}
 
 replace {
         mov  r%1,%2
@@ -1480,14 +1483,14 @@ replace {
         cjne %5,%6,%3
         sjmp %7
 %3:
-        sjmp %8 
+        sjmp %8
 } by {
         ; Peephole 197.a optimized misc jump sequence
         jnz  %8
         mov  a,%4
         cjne %5,%6,%8
         sjmp %7
-;%3:     
+;%3:
 } if labelRefCount %3 2
 
 replace {
@@ -1667,8 +1670,8 @@ replace restart {
         push ar%1
         pop  ar%1
 } by {
-        ; Peephole 211   removed redundant push r%1 pop r%1  
-} 
+        ; Peephole 211   removed redundant push r%1 pop r%1
+}
 
 replace {
        mov  a,_bp
@@ -1698,7 +1701,7 @@ replace {
 
 replace {
        mov  %1,#(( %2 + %3 >> 8 ) ^ 0x80)
-} by { 
+} by {
        ; Peephole 213.c inserted fix
        mov  %1,#((%2 + %3) >> 8)
        xrl  %1,#0x80
@@ -1711,7 +1714,7 @@ replace  {
 } by {
        ; Peephole 214 reduced some extra movs
        mov  %1,a
-       add  a,%2       
+       add  a,%2
 } if operandsNotSame
 
 replace {
@@ -1990,22 +1993,23 @@ replace {
 }
 
 
-replace {
-       add     a,#%2
-       mov     dpl,a
-       clr  a
-       addc    a,#(%2 >> 8)
-       mov     dph,a
-       clr  a
-       addc    a,#(%2 >> 16)
-       mov     dpx,a
-       clr     a
-       movc    a,@a+dptr
-} by {
-       ; Peephole 227.a movc optimize
-       mov     dptr,#%2
-       movc    a,@a+dptr
-}
+// disabled due to bug #1434401
+//replace {
+//     add     a,#%2
+//     mov     dpl,a
+//     clr  a
+//     addc    a,#(%2 >> 8)
+//     mov     dph,a
+//     clr  a
+//     addc    a,#(%2 >> 16)
+//     mov     dpx,a
+//     clr     a
+//     movc    a,@a+dptr
+//} by {
+//     ; Peephole 227.a movc optimize
+//     mov     dptr,#%2
+//     movc    a,@a+dptr
+//}
 
 replace {
        mov     r%1,%2
@@ -2068,7 +2072,7 @@ replace {
        mov     dpx,r%3
        movx    a,@dptr
        mov     r%4,a
-       add     a,#0x01 
+       add     a,#0x01
        mov     r%5,a
        mov     dpl,r%1
        mov     dph,r%2
@@ -2081,7 +2085,7 @@ replace {
        mov     dpx,r%3
        movx    a,@dptr
        mov     r%4,a
-       add     a,#0x01 
+       add     a,#0x01
        mov     r%5,a
        movx    @dptr,a
 }
@@ -2131,7 +2135,7 @@ replace {
        mov     r%4,a
        movx    @dptr,a
 }
-       
+
 replace {
        mov     r%1,dpl
        mov     r%2,dph
@@ -2168,7 +2172,7 @@ replace {
         mov     r%4,a
         movx    @dptr,a
 }
-       
+
 replace {
         mov     dpl,r%1
         mov     dph,r%2
@@ -2215,7 +2219,7 @@ replace {
        inc     dptr
        mov     dps,#0
 }
-       
+
 replace {
        mov     ar%1,r%2
        mov     ar%3,r%1
@@ -2281,7 +2285,7 @@ replace {
        inc     dps
        mov     dptr,#%1
        dec     dps
-} 
+}
 
 // 14 rules by Fiorenzo D. Ramaglia <fd.ramaglia@tin.it>
 
@@ -2423,7 +2427,7 @@ replace {
         mov     %2,%10
         mov     %3,%11
         mov     %4,%12
-        
+
         mov     %5,%13
         mov     %6,%14
         mov     %7,%15
@@ -2438,7 +2442,7 @@ replace {
         mov     %2,%10
         mov     %3,%11
         mov     %4,%12
-        
+
         mov     %5,%13
         mov     %6,%14
         mov     %7,%15
@@ -2452,7 +2456,7 @@ replace {
         mov     %2,%6
         mov     %3,%7
         mov     %4,%8
-        
+
         mov     %5,%1
         mov     %6,%2
         mov     %7,%3
@@ -2468,7 +2472,7 @@ replace {
 replace {
         mov     %1,%5
         mov     %2,%6
-        
+
         mov     %3,%7
         mov     %4,%8
 
@@ -2477,7 +2481,7 @@ replace {
 } by {
         mov     %1,%5
         mov     %2,%6
-        
+
         mov     %3,%7
         mov     %4,%8
         ;       Peephole 238.c  removed 2 redundant moves
@@ -2497,7 +2501,7 @@ replace {
         mov     %2,%5
         mov     %3,%6
         ;       Peephole 238.d  removed 3 redundant moves
-} if operandsNotSame6 %1 %2 %3 %4 %5 %6 
+} if operandsNotSame6 %1 %2 %3 %4 %5 %6
 
 // applies to f.e. ser_ir.asm
 replace {
@@ -2523,10 +2527,10 @@ replace {
         cjne    r%6,#%7,%3
         cjne    r%8,#%9,%3
         mov     a,#0x01
-        sjmp    %10      
-%3:     
+        sjmp    %10
+%3:
         clr     a
-%10:     
+%10:
 } by {
         ;       Peephole 241.a  optimized compare
         clr     a
@@ -2537,17 +2541,17 @@ replace {
         inc     a
 %3:
 %10:
-} 
+}
 
 // applies to f.e. time.c
 replace {
         cjne    r%1,#%2,%3
         cjne    r%4,#%5,%3
         mov     a,#0x01
-        sjmp    %6      
-%3:     
+        sjmp    %6
+%3:
         clr     a
-%6:     
+%6:
 } by {
         ;       Peephole 241.b  optimized compare
         clr     a
@@ -2556,16 +2560,16 @@ replace {
         inc     a
 %3:
 %6:
-} 
+}
 
 // applies to f.e. malloc.c
 replace {
         cjne    r%1,#%2,%3
         mov     a,#0x01
         sjmp    %4
-%3:     
+%3:
         clr     a
-%4:     
+%4:
 } by {
         ;       Peephole 241.c  optimized compare
         clr     a
@@ -2573,23 +2577,23 @@ replace {
         inc     a
 %3:
 %4:
-} 
+}
 
-// applies to f.e. j = (k!=0x1000); 
+// applies to f.e. j = (k!=0x1000);
 // with volatile idata long k;
 replace {
         cjne    @r%1,#%2,%3
-       inc     r%1     
+       inc     r%1
         cjne    @r%1,#%4,%3
-       inc     r%1     
+       inc     r%1
         cjne    @r%1,#%5,%3
-       inc     r%1     
+       inc     r%1
         cjne    @r%1,#%6,%3
         mov     a,#0x01
-        sjmp    %7      
-%3:     
+        sjmp    %7
+%3:
         clr     a
-%7:     
+%7:
 } by {
         ;       Peephole 241.d  optimized compare
         clr     a
@@ -2603,19 +2607,19 @@ replace {
         inc     a
 %3:
 %7:
-} 
+}
 
-// applies to f.e. j = (k!=0x1000); 
+// applies to f.e. j = (k!=0x1000);
 // with volatile idata int k;
 replace {
         cjne    @r%1,#%2,%3
-       inc     r%1     
+       inc     r%1
         cjne    @r%1,#%4,%3
         mov     a,#0x01
-        sjmp    %7      
-%3:     
+        sjmp    %7
+%3:
         clr     a
-%7:     
+%7:
 } by {
         ;       Peephole 241.e  optimized compare
         clr     a
@@ -2625,16 +2629,16 @@ replace {
         inc     a
 %3:
 %7:
-} 
+}
 
 // applies to f.e. vprintf.asm (--stack-auto)
 replace {
         cjne    @r%1,#%2,%3
         mov     a,#0x01
         sjmp    %7
-%3:     
+%3:
         clr     a
-%7:     
+%7:
 } by {
         ;       Peephole 241.f  optimized compare
         clr     a
@@ -2642,7 +2646,7 @@ replace {
         inc     a
 %3:
 %7:
-} 
+}
 
 // applies to f.e. scott-bool1.c
 replace {

diff --git a/support/regression/tests/array.c b/support/regression/tests/array.c
index cc0705407658fdb992b38fec0d130c013311906e..b2e1853977d0bd9874a9bc29c7cca627c525a529 100644 (file)
--- a/support/regression/tests/array.c
+++ b/support/regression/tests/array.c
@@ -13,13 +13,13 @@
 #define TI(x) (0x1020+(x) + 0x100*(x))
 #define TL(x) (0x10203040+(x))
 
-const {storage} char array_const_char[4] = {TC(0), TC(1), TC(2), TC(3)};
-const {storage} int  array_const_int [4] = {TI(0), TI(1), TI(2), TI(3)};
-const {storage} long array_const_long[4] = {TL(0), TL(1), TL(2), TL(3)};
+const {storage} unsigned char array_const_char[4] = {TC(0), TC(1), TC(2), TC(3)};
+const {storage} unsigned int  array_const_int [4] = {TI(0), TI(1), TI(2), TI(3)};
+const {storage} unsigned long array_const_long[4] = {TL(0), TL(1), TL(2), TL(3)};
 
-char array_char[4] = {TC(0), TC(1), TC(2), TC(3)};
-int  array_int [4] = {TI(0), TI(1), TI(2), TI(3)};
-long array_long[4] = {TL(0), TL(1), TL(2), TL(3)};
+unsigned char array_char[4] = {TC(0), TC(1), TC(2), TC(3)};
+unsigned int  array_int [4] = {TI(0), TI(1), TI(2), TI(3)};
+unsigned long array_long[4] = {TL(0), TL(1), TL(2), TL(3)};
 
 volatile unsigned {type} idx;
 volatile unsigned {type} idx2;
@@ -28,7 +28,7 @@ void
 testArrayAccess(void)
 {
   idx = 2;
-  
+
   ASSERT(array_const_char[idx] == TC(2));
   ASSERT(array_const_int [idx] == TI(2));
   ASSERT(array_const_long[idx] == TL(2));
@@ -52,7 +52,7 @@ testArrayAccess(void)
   array_int [idx2] = array_const_int [idx] | 0x8080;
   array_long[idx2] = array_const_long[idx] | 0x80808080;
 
-  ASSERT(array_char[idx2] == TC(3) | 0x80);
-  ASSERT(array_int [idx2] == TI(3) | 0x8080);
-  ASSERT(array_long[idx2] == TL(3) | 0x80808080);
+  ASSERT(array_char[idx2] == (TC(3) | 0x80));
+  ASSERT(array_int [idx2] == (TI(3) | 0x8080));
+  ASSERT(array_long[idx2] == (TL(3) | 0x80808080));
 }