fullchip sim now compiles again, after moving eth and models over to new simple_gemac

diff --git a/usrp2/fpga/models/miim_model.v b/usrp2/fpga/models/miim_model.v
new file mode 100644 (file)
index 0000000..936d99a
--- /dev/null
+++ b/usrp2/fpga/models/miim_model.v
@@ -0,0 +1,14 @@
+
+// Skeleton PHY interface simulator
+
+module miim_model(input mdc_i, 
+                 inout mdio, 
+                 input phy_resetn_i, 
+                 input phy_clk_i, 
+                 output phy_intn_o,
+                 output [2:0] speed_o);
+
+   assign                     phy_intn_o = 1;    // No interrupts
+   assign                     speed_o = 3'b100;  // 1G mode
+   
+endmodule // miim_model

diff --git a/usrp2/fpga/models/phy_sim.v b/usrp2/fpga/models/phy_sim.v
new file mode 100644 (file)
index 0000000..b3de19b
--- /dev/null
+++ b/usrp2/fpga/models/phy_sim.v
@@ -0,0 +1,113 @@
+//////////////////////////////////////////////////////////////////////\r
+////                                                              ////\r
+////  Phy_sim.v                                                   ////\r
+////                                                              ////\r
+////  This file is part of the Ethernet IP core project           ////\r
+////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
+////                                                              ////\r
+////  Author(s):                                                  ////\r
+////      - Jon Gao (gaojon@yahoo.com)                            ////\r
+////                                                              ////\r
+////                                                              ////\r
+//////////////////////////////////////////////////////////////////////\r
+////                                                              ////\r
+//// Copyright (C) 2001 Authors                                   ////\r
+////                                                              ////\r
+//// This source file may be used and distributed without         ////\r
+//// restriction provided that this copyright statement is not    ////\r
+//// removed from the file and that any derivative work contains  ////\r
+//// the original copyright notice and the associated disclaimer. ////\r
+////                                                              ////\r
+//// This source file is free software; you can redistribute it   ////\r
+//// and/or modify it under the terms of the GNU Lesser General   ////\r
+//// Public License as published by the Free Software Foundation; ////\r
+//// either version 2.1 of the License, or (at your option) any   ////\r
+//// later version.                                               ////\r
+////                                                              ////\r
+//// This source is distributed in the hope that it will be       ////\r
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\r
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\r
+//// PURPOSE.  See the GNU Lesser General Public License for more ////\r
+//// details.                                                     ////\r
+////                                                              ////\r
+//// You should have received a copy of the GNU Lesser General    ////\r
+//// Public License along with this source; if not, download it   ////\r
+//// from http://www.opencores.org/lgpl.shtml                     ////\r
+////                                                              ////\r
+//////////////////////////////////////////////////////////////////////\r
+//                                                                    \r
+// CVS Revision History                                               \r
+//                                                                    \r
+// $Log: Phy_sim.v,v $\r
+// Revision 1.3  2006/11/17 17:53:07  maverickist\r
+// no message\r
+//\r
+// Revision 1.2  2006/01/19 14:07:50  maverickist\r
+// verification is complete.\r
+//\r
+// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator\r
+// no message\r
+// \r
+\r
+`timescale 1ns/100ps \r
+\r
+module phy_sim(\r
+  input        Gtx_clk, // Used only in GMII mode\r
+  output       Rx_clk,\r
+  output       Tx_clk, // Used only in MII mode\r
+  input        Tx_er,\r
+  input        Tx_en,\r
+  input  [7:0] Txd,\r
+  output       Rx_er,\r
+  output       Rx_dv,\r
+  output [7:0] Rxd,\r
+  output       Crs,\r
+  output       Col,\r
+  input  [2:0] Speed,\r
+  input        Done\r
+);\r
+\r
+//////////////////////////////////////////////////////////////////////\r
+// this file used to simulate Phy.\r
+// generate clk and loop the Tx data to Rx data\r
+// full duplex mode can be verified on loop mode.\r
+//////////////////////////////////////////////////////////////////////\r
+//////////////////////////////////////////////////////////////////////\r
+// internal signals\r
+//////////////////////////////////////////////////////////////////////\r
+reg Clk_25m;  // Used for 100 Mbps mode\r
+reg Clk_2_5m; // Used for 10 Mbps mode\r
+\r
+//wire Rx_clk;\r
+//wire Tx_clk; // Used only in MII mode\r
+\r
+  initial \r
+    begin\r
+      #10;\r
+      while ( !Done )\r
+        begin\r
+          #20 Clk_25m = 0;\r
+          #20 Clk_25m = 1;\r
+        end\r
+    end\r
+\r
+  initial \r
+    begin\r
+      #10;\r
+      while ( !Done )\r
+        begin\r
+          #200 Clk_2_5m = 0;\r
+          #200 Clk_2_5m = 1;\r
+        end\r
+    end\r
+\r
+  assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;        \r
+  assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;\r
+\r
+  assign Rx_dv = Tx_en;\r
+  assign Rxd   = Txd;\r
+  assign Rx_er = Tx_er;\r
+  assign Crs   = Tx_en;\r
+  assign Col   = 0;\r
+\r
+endmodule\r

diff --git a/usrp2/fpga/models/xlnx_glbl.v b/usrp2/fpga/models/xlnx_glbl.v
new file mode 100644 (file)
index 0000000..662a60e
--- /dev/null
+++ b/usrp2/fpga/models/xlnx_glbl.v
@@ -0,0 +1,29 @@
+module xlnx_glbl\r
+(\r
+  GSR,\r
+  GTS\r
+);\r
+\r
+  //--------------------------------------------------------------------------\r
+  // Parameters\r
+  //--------------------------------------------------------------------------\r
+\r
+  //--------------------------------------------------------------------------\r
+  // IO declarations\r
+  //--------------------------------------------------------------------------\r
+\r
+  output GSR;\r
+  output GTS;\r
+\r
+  //--------------------------------------------------------------------------\r
+  // Local declarations\r
+  //--------------------------------------------------------------------------\r
+\r
+  //--------------------------------------------------------------------------\r
+  // Internal declarations\r
+  //--------------------------------------------------------------------------\r
+\r
+  assign GSR = 0;\r
+  assign GTS = 0;\r
+  \r
+endmodule\r

diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile
index ed251665cf3cae2646eec3cabff16e8ec8980a9c..8083eb92ada0225e079f0ce3f6eb43c5c239000a 100644 (file)
--- a/usrp2/fpga/testbench/cmdfile
+++ b/usrp2/fpga/testbench/cmdfile
@@ -9,6 +9,8 @@
 -y ../timing
 -y ../coregen
 -y ../extram
+-y ../simple_gemac
+-y ../simple_gemac/miim
 
 # Models
 -y ../models
@@ -18,24 +20,8 @@
 -y ../opencores/8b10b
 -y ../opencores/spi/rtl/verilog
 +incdir+../opencores/spi/rtl/verilog
--y ../opencores/wb_conbus/rtl/verilog
-+incdir+../opencores/wb_conbus/rtl/verilog
 -y ../opencores/i2c/rtl/verilog
 +incdir+../opencores/i2c/rtl/verilog
 -y ../opencores/aemb/rtl/verilog
 -y ../opencores/simple_pic/rtl
 
-# Ethernet
-+incdir+../eth/rtl/verilog
--y ../eth/rtl/verilog
--y ../eth/rtl/verilog/MAC_tx
--y ../eth/rtl/verilog/MAC_rx
--y ../eth/rtl/verilog/miim
--y ../eth/rtl/verilog/TECH
--y ../eth/rtl/verilog/TECH/xilinx
--y ../eth/rtl/verilog/RMON
--y ../eth
--y ../eth/bench/verilog
-
-# Ethernet Models
--y ../eth/bench/verilog

diff --git a/usrp2/fpga/top/single_u2_sim/single_u2_sim.v b/usrp2/fpga/top/single_u2_sim/single_u2_sim.v
index 016815ff7704308148ed1f3362ad9fa7fc18abfb..2a7b24849767a61158ae5dcead48a4c311171fbd 100644 (file)
--- a/usrp2/fpga/top/single_u2_sim/single_u2_sim.v
+++ b/usrp2/fpga/top/single_u2_sim/single_u2_sim.v
@@ -178,7 +178,7 @@ module single_u2_sim();
       .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) );
 
    wire [2:0] speed;
-   Phy_sim phy_model
+   phy_sim phy_model
      (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK),
       .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD),
       .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD),