always @(posedge clk) strobe_cic_d1 <= strobe_cic;
small_hb_dec #(.WIDTH(18)) small_hb_i
- (.clk(clk),.rst(rst),.bypass(~enable_hb1),
+ (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
.stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1));
small_hb_dec #(.WIDTH(18)) small_hb_q
- (.clk(clk),.rst(rst),.bypass(~enable_hb1),
+ (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
.stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
- (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb),
+ (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
.stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
- (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb),
+ (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
.stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
(input clk,
input rst,
input bypass,
+ input run,
input stb_in,
input [WIDTH-1:0] data_in,
output reg stb_out,
wire go;
reg phase, go_d1, go_d2, go_d3, go_d4;
always @(posedge clk)
- if(rst)
+ if(rst | ~run)
phase <= 0;
else if(stb_in_d1)
phase <= ~phase;
assign go = stb_in_d1 & phase;
- always @(posedge clk) go_d1 <= go;
- always @(posedge clk) go_d2 <= go_d1;
- always @(posedge clk) go_d3 <= go_d2;
- always @(posedge clk) go_d4 <= go_d3;
+ always @(posedge clk)
+ if(rst | ~run)
+ begin
+ go_d1 <= 0;
+ go_d2 <= 0;
+ go_d3 <= 0;
+ go_d4 <= 0;
+ end
+ else
+ begin
+ go_d1 <= go;
+ go_d2 <= go_d1;
+ go_d3 <= go_d2;
+ go_d4 <= go_d3;
+ end
wire [17:0] coeff_a = -10690;
wire [17:0] coeff_b = 75809;