zy1000: revc FPGA now works

remove kludge code.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

diff --git a/src/jtag/zy1000/jtag_minidriver.h b/src/jtag/zy1000/jtag_minidriver.h
index 536c677061d3d97c92af3d60a25aa056807a3745..a78a0631a965151d2dd6aa06e50898cbc5981668 100644 (file)
--- a/src/jtag/zy1000/jtag_minidriver.h
+++ b/src/jtag/zy1000/jtag_minidriver.h
@@ -32,33 +32,9 @@ int  diag_printf(const char *fmt, ...);
 #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b); diag_printf("peek 0x%08x = 0x%08x\n", a, b)
 #else
 #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b)
-
-#ifdef CYGPKG_HAL_NIOS2
-#define ZY1000_POKE(a, b) \
-                {/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \
-                flush every "often". No precise system has been found, but 4 seems solid. \
-                 This code goes away once the FPGA has been fixed. */ \
-\
-CYG_INTERRUPT_STATE _old_; \
-HAL_DISABLE_INTERRUPTS(_old_); \
-HAL_WRITE_UINT32(a, b);\
- static int overflow_counter = 0; \
-   if (++overflow_counter >= 1) \
-   { \
-          /* clear FIFO */ \
-          cyg_uint32 empty; ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); \
-          overflow_counter = 0; \
-   } \
-   /* NB! interrupts must be restored *after* read */ \
-   HAL_RESTORE_INTERRUPTS(_old_); \
-}\
-
-#else
 #define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b)
 #endif
 
-#endif
-
 // FIFO empty?
 static __inline__ void waitIdle(void)
 {

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 5ddc7c5ce0768000f7a5a2024bd939310449229a..30b9a4ba44b178a47424623fc1ee678e73e8dc1e 100644 (file)
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -93,8 +93,8 @@ static bool readPowerDropout(void)
 {
        cyg_uint32 state;
        // sample and clear power dropout
-       HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x10, 0x80);
-       HAL_READ_UINT32(ZY1000_JTAG_BASE + 0x10, state);
+       ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x80);
+       ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
        bool powerDropout;
        powerDropout = (state & 0x80) != 0;
        return powerDropout;
@@ -105,8 +105,8 @@ static bool readSRST(void)
 {
        cyg_uint32 state;
        // sample and clear SRST sensing
-       HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x10, 0x00000040);
-       HAL_READ_UINT32(ZY1000_JTAG_BASE + 0x10, state);
+       ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000040);
+       ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
        bool srstAsserted;
        srstAsserted = (state & 0x40) != 0;
        return srstAsserted;
@@ -218,10 +218,10 @@ static void setPower(bool power)
        savePower = power;
        if (power)
        {
-               HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x14, 0x8);
+               ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x8);
        } else
        {
-               HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x10, 0x8);
+               ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x8);
        }
 }