<name>USRP Dual Sink</name>
<key>usrp_dual_sink_x</key>
<import>from grc_gnuradio import usrp as grc_usrp</import>
- <make>grc_usrp.dual_sink_$(type.fcn)(number=$number)
+ <make>grc_usrp.dual_sink_$(type.fcn)(which=$which)
#if $format.eval
self.$(id).set_format(width=$format.width, shift=$format.shift)
#end if
</param>
<param>
<name>Unit Number</name>
- <key>number</key>
+ <key>which</key>
<value>0</value>
<type>int</type>
</param>
<name>USRP Dual Source</name>
<key>usrp_dual_source_x</key>
<import>from grc_gnuradio import usrp as grc_usrp</import>
- <make>grc_usrp.dual_source_$(type.fcn)(number=$number, side_a='$rx_ant_a.side', rx_ant_a='$rx_ant_a.rx_ant', side_b='$rx_ant_b.side', rx_ant_b='$rx_ant_b.rx_ant')
+ <make>grc_usrp.dual_source_$(type.fcn)(which=$which, side_a='$rx_ant_a.side', rx_ant_a='$rx_ant_a.rx_ant', side_b='$rx_ant_b.side', rx_ant_b='$rx_ant_b.rx_ant')
#if $format.eval
self.$(id).set_format(width=$format.width, shift=$format.shift)
#end if
</param>
<param>
<name>Unit Number</name>
- <key>number</key>
+ <key>which</key>
<value>0</value>
<type>int</type>
</param>
<key>usrp_probe</key>
<make></make>
<param>
- <name>USRP Number</name>
- <key>number</key>
+ <name>Unit Number</name>
+ <key>which</key>
<value>0</value>
<type>int</type>
</param>
<name>USRP Sink</name>
<key>usrp_simple_sink_x</key>
<import>from grc_gnuradio import usrp as grc_usrp</import>
- <make>grc_usrp.simple_sink_$(type.fcn)(number=$number, side='$side')
+ <make>grc_usrp.simple_sink_$(type.fcn)(which=$which, side='$side')
#if $format.eval
self.$(id).set_format(width=$format.width, shift=$format.shift)
#end if
</param>
<param>
<name>Unit Number</name>
- <key>number</key>
+ <key>which</key>
<value>0</value>
<type>int</type>
</param>
<name>USRP Source</name>
<key>usrp_simple_source_x</key>
<import>from grc_gnuradio import usrp as grc_usrp</import>
- <make>grc_usrp.simple_source_$(type.fcn)(number=$number, side='$side', rx_ant='$rx_ant')
+ <make>grc_usrp.simple_source_$(type.fcn)(which=$which, side='$side', rx_ant='$rx_ant'#if $hb_filters.eval then ', no_hb=True' else ''#)
#if $format.eval
self.$(id).set_format(width=$format.width, shift=$format.shift)
#end if
</param>
<param>
<name>Unit Number</name>
- <key>number</key>
+ <key>which</key>
<value>0</value>
<type>int</type>
</param>
<key>False</key>
</option>
</param>
+ <param>
+ <name>Halfband Filters</name>
+ <key>hb_filters</key>
+ <value></value>
+ <type>enum</type>
+ <hide>#if $hb_filters.eval then 'none' else 'part'#</hide>
+ <option>
+ <name>Enable</name>
+ <key></key>
+ </option>
+ <option>
+ <name>Disable</name>
+ <key>1</key>
+ </option>
+ </param>
<source>
<name>out</name>
<type>$type</type>
Flex RF boards only: If enabled, "Auto Transmit/Receive Switching" handles the preference for transmit packets vs receive packets. \
By default, "Auto TR" is disabled.
+
+With the format set to 8 bits and the halfband filters disabled, the USRP can acheive a decimation rate of 4. \
+Disabling the halfband filters requires a special USRP firmware without halfband filters or TX paths. \
+For this reason, the USRP cannot transmit with the halfband filters disabled.
</doc>
</block>
block = flow_graph.get_new_block('usrp_probe')
##all params
-usrp_number_param = block.get_param('number')
+usrp_which_param = block.get_param('which')
usrp_dboard_param = block.get_param('dboard')
class USRPProbeWindow(gtk.Window):
#create vbox for storage
vbox = gtk.VBox()
frame.add(vbox)
- vbox.pack_start(usrp_number_param.get_input_object(), False)
+ vbox.pack_start(usrp_which_param.get_input_object(), False)
vbox.pack_start(usrp_dboard_param.get_input_object(), False)
self.probe_button = gtk.Button('Probe')
self.probe_button.connect('clicked', self._probe_usrp)
make = usrp.sink_c
get_mux = usrp.determine_tx_mux_value
try:
- u = make(usrp_number_param.evaluate())
+ u = make(which=usrp_which_param.evaluate())
subdev_spec = (side, 0)
subdev = usrp.selected_subdev(u, subdev_spec) #get the subdev
msg = ">>> USRP Probe\n"
def _make_usrp(self, *args, **kwargs): self._u = self._usrp_args[0](*args, **kwargs)
def _get_u(self): return self._u
def _get_io_size(self): return self._usrp_args[1]
- def _set_frequency(self, which, subdev, frequency, verbose=False):
+ def _set_frequency(self, chan, subdev, frequency, verbose=False):
"""
Set the carrier frequency for the given subdevice.
- @param which specifies the DDC/DUC number
+ @param chan specifies the DDC/DUC number
@param frequency the carrier frequency in Hz
@param verbose if true, print usrp tuning information
"""
- r = self._get_u().tune(which, subdev, frequency)
+ r = self._get_u().tune(chan, subdev, frequency)
if not verbose: return
print subdev.side_and_name()
if r:
class _dual_source(gr.hier_block2):
"""A dual usrp source of IO type short or complex."""
- def __init__(self, number, side_a='A', rx_ant_a='RXA', side_b='B', rx_ant_b='RXA'):
+ def __init__(self, which, side_a='A', rx_ant_a='RXA', side_b='B', rx_ant_b='RXA'):
"""
USRP dual source contructor.
- @param number the unit number
+ @param which the unit number
@param side_a A or B
@param rx_ant_a the antenna choice
@param side_b A or B
gr.io_signature(2, 2, self._get_io_size()),
)
#create usrp object
- self._make_usrp(number, nchan=2)
+ self._make_usrp(which=which, nchan=2)
#get the mux for output A
subdev_spec_a = common.to_spec(side_a, rx_ant_a)
self._subdev_a = usrp.selected_subdev(self._get_u(), subdev_spec_a)
def set_decim_rate(self, decim): self._get_u().set_decim_rate(int(decim))
def set_frequency_a(self, frequency, verbose=False):
self._set_frequency(
- which=0, #ddc0
+ chan=0, #ddc0
subdev=self._subdev_a,
frequency=frequency,
verbose=verbose,
)
def set_frequency_b(self, frequency, verbose=False):
self._set_frequency(
- which=1, #ddc1
+ chan=1, #ddc1
subdev=self._subdev_b,
frequency=frequency,
verbose=verbose,
class _dual_sink(gr.hier_block2):
"""A dual usrp sink of IO type short or complex."""
- def __init__(self, number):
+ def __init__(self, which):
"""
USRP simple sink contructor.
- @param number the unit number
+ @param which the unit number
"""
#initialize hier2 block
gr.hier_block2.__init__(
gr.io_signature(0, 0, 0),
)
#create usrp object
- self._make_usrp(number, nchan=2)
+ self._make_usrp(which=which, nchan=2)
#get the mux for side A
subdev_spec_a = common.to_spec('A')
self._subdev_a = usrp.selected_subdev(self._get_u(), subdev_spec_a)
def set_interp_rate(self, interp): self._get_u().set_interp_rate(int(interp))
def set_frequency_a(self, frequency, verbose=False):
self._set_frequency(
- which=self._subdev_a.which(),
+ chan=self._subdev_a.which(),
subdev=self._subdev_a,
frequency=frequency,
verbose=verbose,
)
def set_frequency_b(self, frequency, verbose=False):
self._set_frequency(
- which=self._subdev_b.which(),
+ chan=self._subdev_b.which(),
subdev=self._subdev_b,
frequency=frequency,
verbose=verbose,
class _simple_source(gr.hier_block2):
"""A single usrp source of IO type short or complex."""
- def __init__(self, number, side='A', rx_ant='RXA'):
+ def __init__(self, which, side='A', rx_ant='RXA', no_hb=False):
"""
USRP simple source contructor.
- @param number the unit number
+ @param which the unit number
@param side the usrp side A or B
@param rx_ant the antenna choice
+ @param no_hb disable half band filters
"""
+ self._no_hb = no_hb
#initialize hier2 block
gr.hier_block2.__init__(
self, 'usrp_simple_source',
gr.io_signature(1, 1, self._get_io_size()),
)
#create usrp object
- self._make_usrp(number, nchan=1)
+ if self._no_hb: self._make_usrp(which=which, nchan=1, fpga_filename="std_4rx_0tx.rbf")
+ else: self._make_usrp(which=which, nchan=1)
subdev_spec = common.to_spec(side, rx_ant)
self._get_u().set_mux(usrp.determine_rx_mux_value(self._get_u(), subdev_spec))
self._subdev = usrp.selected_subdev(self._get_u(), subdev_spec)
#connect
self.connect(self._get_u(), self)
- def set_decim_rate(self, decim): self._get_u().set_decim_rate(int(decim))
+ def set_decim_rate(self, decim):
+ self._get_u().set_decim_rate(int(decim))
+ if self._no_hb: #set the BW to half the sample rate
+ self._subdev.set_bw(self._get_u().converter_rate()/decim/2)
def set_frequency(self, frequency, verbose=False):
self._set_frequency(
- which=0, #ddc0
+ chan=0, #ddc0
subdev=self._subdev,
frequency=frequency,
verbose=verbose,
class _simple_sink(gr.hier_block2):
"""A single usrp sink of IO type short or complex."""
- def __init__(self, number, side='A'):
+ def __init__(self, which, side='A'):
"""
USRP simple sink contructor.
- @param number the unit number
+ @param which the unit number
@param side the usrp side A or B
"""
#initialize hier2 block
gr.io_signature(0, 0, 0),
)
#create usrp object
- self._make_usrp(number, nchan=1)
+ self._make_usrp(which=which, nchan=1)
subdev_spec = common.to_spec(side)
self._get_u().set_mux(usrp.determine_tx_mux_value(self._get_u(), subdev_spec))
self._subdev = usrp.selected_subdev(self._get_u(), subdev_spec)
def set_interp_rate(self, interp): self._get_u().set_interp_rate(int(interp))
def set_frequency(self, frequency, verbose=False):
self._set_frequency(
- which=self._subdev.which(),
+ chan=self._subdev.which(),
subdev=self._subdev,
frequency=frequency,
verbose=verbose,