helper/align.h: use it

Use the new helper to make the code more readable.

Change-Id: I11b2a79dbc6f93f6cfde382bcc00dd7ff710d908
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6375
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index d70895c536fa0b2ce1665f4ef1dd606f908b4693..e6d3a8350bba59ae6c38c1ecf7fabb7e5ac4226c 100644 (file)
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -24,6 +24,7 @@
 #endif
 
 #include "imp.h"
+#include <helper/align.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
@@ -1591,7 +1592,7 @@ static int stm32l4_probe(struct flash_bank *bank)
         * max_flash_size is always power of two, so max_pages too
         */
        uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
-       assert((max_pages & (max_pages - 1)) == 0);
+       assert(IS_PWR_OF_2(max_pages));
 
        /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
        stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);

diff --git a/src/flash/nor/xmc1xxx.c b/src/flash/nor/xmc1xxx.c
index 11542ac5bb16e9a7aef21c4438aed077a3aa9991..a519ab864302d2bc177bde6ddd11bf81132c51c8 100644 (file)
--- a/src/flash/nor/xmc1xxx.c
+++ b/src/flash/nor/xmc1xxx.c
@@ -11,6 +11,7 @@
 #endif
 
 #include "imp.h"
+#include <helper/align.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
@@ -256,12 +257,12 @@ static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer,
        LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
                offset, byte_count);
 
-       if (offset & (NVM_BLOCK_SIZE - 1)) {
+       if (!IS_ALIGNED(offset, NVM_BLOCK_SIZE)) {
                LOG_ERROR("offset 0x%" PRIx32 " breaks required block alignment",
                        offset);
                return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
        }
-       if (byte_count & (NVM_BLOCK_SIZE - 1)) {
+       if (!IS_ALIGNED(byte_count, NVM_BLOCK_SIZE)) {
                LOG_WARNING("length %" PRIu32 " is not block aligned, rounding up",
                        byte_count);
        }

diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 4a8cfcd4bf6f917b717128adeceb0ce57264d89e..923cdf8772f405d414d718f6277723f0d451f57d 100644 (file)
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -68,6 +68,7 @@
 #include "config.h"
 #endif
 
+#include <helper/align.h>
 #include <helper/time_support.h>
 
 #include "mips32.h"
@@ -658,7 +659,7 @@ static int mips32_pracc_synchronize_cache(struct mips_ejtag *ejtag_info,
                goto exit;  /* Nothing to do */
 
        /* make sure clsiz is power of 2 */
-       if (clsiz & (clsiz - 1)) {
+       if (!IS_PWR_OF_2(clsiz)) {
                LOG_DEBUG("clsiz must be power of 2");
                ctx.retval = ERROR_FAIL;
                goto exit;

diff --git a/src/target/target.c b/src/target/target.c
index a67712009d3d24320baa491d434350aa35e3490b..7bace83f9ca34f2213401b06765139ad1f32bcc3 100644 (file)
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -41,6 +41,7 @@
 #include "config.h"
 #endif
 
+#include <helper/align.h>
 #include <helper/time_support.h>
 #include <jtag/jtag.h>
 #include <flash/nor/core.h>
@@ -1004,7 +1005,7 @@ int target_run_flash_async_algorithm(struct target *target,
        uint32_t rp = fifo_start_addr;
 
        /* validate block_size is 2^n */
-       assert(!block_size || !(block_size & (block_size - 1)));
+       assert(IS_PWR_OF_2(block_size));
 
        retval = target_write_u32(target, wp_addr, wp);
        if (retval != ERROR_OK)
@@ -1042,7 +1043,7 @@ int target_run_flash_async_algorithm(struct target *target,
                        break;
                }
 
-               if (((rp - fifo_start_addr) & (block_size - 1)) || rp < fifo_start_addr || rp >= fifo_end_addr) {
+               if (!IS_ALIGNED(rp - fifo_start_addr, block_size) || rp < fifo_start_addr || rp >= fifo_end_addr) {
                        LOG_ERROR("corrupted fifo read pointer 0x%" PRIx32, rp);
                        break;
                }
@@ -1157,7 +1158,7 @@ int target_run_read_async_algorithm(struct target *target,
        uint32_t rp = fifo_start_addr;
 
        /* validate block_size is 2^n */
-       assert(!block_size || !(block_size & (block_size - 1)));
+       assert(IS_PWR_OF_2(block_size));
 
        retval = target_write_u32(target, wp_addr, wp);
        if (retval != ERROR_OK)
@@ -1194,7 +1195,7 @@ int target_run_read_async_algorithm(struct target *target,
                        break;
                }
 
-               if (((wp - fifo_start_addr) & (block_size - 1)) || wp < fifo_start_addr || wp >= fifo_end_addr) {
+               if (!IS_ALIGNED(wp - fifo_start_addr, block_size) || wp < fifo_start_addr || wp >= fifo_end_addr) {
                        LOG_ERROR("corrupted fifo write pointer 0x%" PRIx32, wp);
                        break;
                }