{
dirty = 1;
LOG_DEBUG("examining dirty reg: %s", reg->name);
- if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
+ if ((reg_arch_info->mode != ARM_MODE_ANY)
&& (reg_arch_info->mode != current_mode)
- && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
- && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
+ && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
+ && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
{
mode_change = 1;
LOG_DEBUG("require mode change");
reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
reg_arch_info = reg->arch_info;
- if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
+ if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
{
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY))
+ && (areg->mode != ARM_MODE_ANY))
{
uint32_t tmp_cpsr;
/* read a program status register
* if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
*/
- arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
+ arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
r->dirty = 0;
buf_set_u32(r->value, 0, 32, value);
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
/* write a program status register
* if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
*/
- int spsr = (areg->mode != ARMV4_5_MODE_ANY);
+ int spsr = (areg->mode != ARM_MODE_ANY);
/* if we're writing the CPSR, mask the T bit */
if (!spsr)
r->valid = 1;
r->dirty = 0;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
struct reg_param reg_params[1];
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
uint32_t cpsr;
/* restore previous mode */
- if (mode == ARMV4_5_MODE_ANY)
+ if (mode == ARM_MODE_ANY)
cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
/* else force to the specified mode */
* actually find anything to do...
*/
do {
- enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+ enum armv4_5_mode mode = ARM_MODE_ANY;
did_write = false;
* we "know" core mode is accurate
* since we haven't changed it yet
*/
- if (arm->core_mode == ARMV4_5_MODE_FIQ
- && ARMV4_5_MODE_ANY
+ if (arm->core_mode == ARM_MODE_FIQ
+ && ARM_MODE_ANY
!= mode)
- tmode = ARMV4_5_MODE_USR;
+ tmode = ARM_MODE_USR;
break;
case 16:
/* SPSR */
}
/* REVISIT error checks */
- if (tmode != ARMV4_5_MODE_ANY)
+ if (tmode != ARM_MODE_ANY)
retval = dpm_modeswitch(dpm, tmode);
}
if (r->mode != mode)
* or it's dirty. Must write PC to ensure the return address is
* defined, and must not write it before CPSR.
*/
- retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+ retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
arm->cpsr->dirty = false;
retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
return retval;
}
-/* Returns ARMV4_5_MODE_ANY or temporary mode to use while reading the
+/* Returns ARM_MODE_ANY or temporary mode to use while reading the
* specified register ... works around flakiness from ARM core calls.
* Caller already filtered out SPSR access; mode is never MODE_SYS
* or MODE_ANY.
enum armv4_5_mode amode = arm->core_mode;
/* don't switch if the mode is already correct */
- if (amode == ARMV4_5_MODE_SYS)
- amode = ARMV4_5_MODE_USR;
+ if (amode == ARM_MODE_SYS)
+ amode = ARM_MODE_USR;
if (mode == amode)
- return ARMV4_5_MODE_ANY;
+ return ARM_MODE_ANY;
switch (num) {
/* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
break;
/* r8..r12 aren't shadowed for anything except FIQ */
case 8 ... 12:
- if (mode == ARMV4_5_MODE_FIQ)
+ if (mode == ARM_MODE_FIQ)
return mode;
break;
/* r13/sp, and r14/lr are always shadowed */
LOG_WARNING("invalid register #%u", num);
break;
}
- return ARMV4_5_MODE_ANY;
+ return ARM_MODE_ANY;
}
return ERROR_INVALID_ARGUMENTS;
if (regnum == 16) {
- if (mode != ARMV4_5_MODE_ANY)
+ if (mode != ARM_MODE_ANY)
regnum = 17;
} else
mode = dpm_mapmode(dpm->arm, regnum, mode);
if (retval != ERROR_OK)
return retval;
- if (mode != ARMV4_5_MODE_ANY) {
+ if (mode != ARM_MODE_ANY) {
retval = dpm_modeswitch(dpm, mode);
if (retval != ERROR_OK)
goto fail;
retval = dpm_read_reg(dpm, r, regnum);
/* always clean up, regardless of error */
- if (mode != ARMV4_5_MODE_ANY)
- /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+ if (mode != ARM_MODE_ANY)
+ /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
fail:
/* (void) */ dpm->finish(dpm);
return ERROR_INVALID_ARGUMENTS;
if (regnum == 16) {
- if (mode != ARMV4_5_MODE_ANY)
+ if (mode != ARM_MODE_ANY)
regnum = 17;
} else
mode = dpm_mapmode(dpm->arm, regnum, mode);
if (retval != ERROR_OK)
return retval;
- if (mode != ARMV4_5_MODE_ANY) {
+ if (mode != ARM_MODE_ANY) {
retval = dpm_modeswitch(dpm, mode);
if (retval != ERROR_OK)
goto fail;
retval = dpm_write_reg(dpm, r, regnum);
/* always clean up, regardless of error */
- if (mode != ARMV4_5_MODE_ANY)
- /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+ if (mode != ARM_MODE_ANY)
+ /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
fail:
/* (void) */ dpm->finish(dpm);
goto done;
do {
- enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+ enum armv4_5_mode mode = ARM_MODE_ANY;
did_read = false;
/* For R8..R12 when we've entered debug
* state in FIQ mode... patch mode.
*/
- if (mode == ARMV4_5_MODE_ANY)
- mode = ARMV4_5_MODE_USR;
+ if (mode == ARM_MODE_ANY)
+ mode = ARM_MODE_USR;
/* REVISIT error checks */
retval = dpm_modeswitch(dpm, mode);
} while (did_read);
- retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+ retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
/* (void) */ dpm->finish(dpm);
done:
return retval;
*/
{
.name = "User",
- .psr = ARMV4_5_MODE_USR,
+ .psr = ARM_MODE_USR,
.n_indices = ARRAY_SIZE(arm_usr_indices),
.indices = arm_usr_indices,
},
{
.name = "FIQ",
- .psr = ARMV4_5_MODE_FIQ,
+ .psr = ARM_MODE_FIQ,
.n_indices = ARRAY_SIZE(arm_fiq_indices),
.indices = arm_fiq_indices,
},
{
.name = "Supervisor",
- .psr = ARMV4_5_MODE_SVC,
+ .psr = ARM_MODE_SVC,
.n_indices = ARRAY_SIZE(arm_svc_indices),
.indices = arm_svc_indices,
},
{
.name = "Abort",
- .psr = ARMV4_5_MODE_ABT,
+ .psr = ARM_MODE_ABT,
.n_indices = ARRAY_SIZE(arm_abt_indices),
.indices = arm_abt_indices,
},
{
.name = "IRQ",
- .psr = ARMV4_5_MODE_IRQ,
+ .psr = ARM_MODE_IRQ,
.n_indices = ARRAY_SIZE(arm_irq_indices),
.indices = arm_irq_indices,
},
{
.name = "Undefined instruction",
- .psr = ARMV4_5_MODE_UND,
+ .psr = ARM_MODE_UND,
.n_indices = ARRAY_SIZE(arm_und_indices),
.indices = arm_und_indices,
},
{
.name = "System",
- .psr = ARMV4_5_MODE_SYS,
+ .psr = ARM_MODE_SYS,
.n_indices = ARRAY_SIZE(arm_usr_indices),
.indices = arm_usr_indices,
},
int armv4_5_mode_to_number(enum armv4_5_mode mode)
{
switch (mode) {
- case ARMV4_5_MODE_ANY:
+ case ARM_MODE_ANY:
/* map MODE_ANY to user mode */
- case ARMV4_5_MODE_USR:
+ case ARM_MODE_USR:
return 0;
- case ARMV4_5_MODE_FIQ:
+ case ARM_MODE_FIQ:
return 1;
- case ARMV4_5_MODE_IRQ:
+ case ARM_MODE_IRQ:
return 2;
- case ARMV4_5_MODE_SVC:
+ case ARM_MODE_SVC:
return 3;
- case ARMV4_5_MODE_ABT:
+ case ARM_MODE_ABT:
return 4;
- case ARMV4_5_MODE_UND:
+ case ARM_MODE_UND:
return 5;
- case ARMV4_5_MODE_SYS:
+ case ARM_MODE_SYS:
return 6;
case ARM_MODE_MON:
return 7;
{
switch (number) {
case 0:
- return ARMV4_5_MODE_USR;
+ return ARM_MODE_USR;
case 1:
- return ARMV4_5_MODE_FIQ;
+ return ARM_MODE_FIQ;
case 2:
- return ARMV4_5_MODE_IRQ;
+ return ARM_MODE_IRQ;
case 3:
- return ARMV4_5_MODE_SVC;
+ return ARM_MODE_SVC;
case 4:
- return ARMV4_5_MODE_ABT;
+ return ARM_MODE_ABT;
case 5:
- return ARMV4_5_MODE_UND;
+ return ARM_MODE_UND;
case 6:
- return ARMV4_5_MODE_SYS;
+ return ARM_MODE_SYS;
case 7:
return ARM_MODE_MON;
default:
LOG_ERROR("mode index out of bounds %d", number);
- return ARMV4_5_MODE_ANY;
+ return ARM_MODE_ANY;
}
}
* correspond to r0..r7, and the fifteenth to PC, so that callers
* don't need to map them.
*/
- { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
+ { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
+ { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
+ { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
+ { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
+ { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
+ { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
+ { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
* them as MODE_ANY creates special cases. (ANY means
* "not mapped" elsewhere; here it's "everything but FIQ".)
*/
- { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
+ { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
+ { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
+ { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
+ { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
- { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
- { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
+ { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
+ { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
/* guaranteed to be at index 15 */
- { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
- { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
+ { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
+ { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
+ { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
+ { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
- { .name = "sp_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "lr_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
+ { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
- { .name = "sp_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
- { .name = "lr_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
+ { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
+ { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
- { .name = "sp_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
- { .name = "lr_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
+ { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
+ { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
- { .name = "sp_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
- { .name = "lr_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
+ { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
+ { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
- { .name = "sp_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
- { .name = "lr_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
+ { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
+ { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
- { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
- { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
- { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
- { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
- { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
+ { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
+ { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
+ { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
+ { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
+ { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
+ { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
{ .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
{ .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
/* mode_to_number() warned; set up a somewhat-sane mapping */
num = armv4_5_mode_to_number(mode);
if (num < 0) {
- mode = ARMV4_5_MODE_USR;
+ mode = ARM_MODE_USR;
num = 0;
}
arm->map = &armv4_5_core_reg_map[num][0];
- arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS)
+ arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
? NULL
: arm->core_cache->reg_list + arm->map[16];
arm_mode_name(value & 0x1f));
value &= ~((1 << 24) | (1 << 5));
armv4_5_target->write_core_reg(target, reg,
- 16, ARMV4_5_MODE_ANY, value);
+ 16, ARM_MODE_ANY, value);
}
} else {
buf_set_u32(reg->value, 0, 32, value);
/* label this bank of registers (or shadows) */
switch (arm_mode_data[mode].psr) {
- case ARMV4_5_MODE_SYS:
+ case ARM_MODE_SYS:
continue;
- case ARMV4_5_MODE_USR:
+ case ARM_MODE_USR:
name = "System and User";
sep = "";
break;
return ERROR_INVALID_ARGUMENTS;
}
- if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
+ if (armv4_5_algorithm_info->core_mode != ARM_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x",
armv4_5_algorithm_info->core_mode);
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
armv4_5->target = target;
armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
- arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
+ arm_set_cpsr(armv4_5, ARM_MODE_USR);
/* core_type may be overridden by subtype logic */
- armv4_5->core_type = ARMV4_5_MODE_ANY;
+ armv4_5->core_type = ARM_MODE_ANY;
/* default full_context() has no core-specific optimizations */
if (!armv4_5->full_context && armv4_5->read_core_reg)