- replaces all calls to target->type->write_memory.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1960
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
16 files changed:
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
- if((retval = target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
+ if((retval = target_write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
}
cfi_command(bank, 0x50, command);
}
cfi_command(bank, 0x50, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
}
u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x20, command);
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x20, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xd0, command);
{
return retval;
}
cfi_command(bank, 0xd0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
else
{
cfi_command(bank, 0xff, command);
else
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
}
cfi_command(bank, 0xff, command);
}
cfi_command(bank, 0xff, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
for (i = first; i <= last; i++)
{
cfi_command(bank, 0xaa, command);
for (i = first; i <= last; i++)
{
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x80, command);
{
return retval;
}
cfi_command(bank, 0x80, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xaa, command);
{
return retval;
}
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x30, command);
{
return retval;
}
cfi_command(bank, 0x30, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
else
{
cfi_command(bank, 0xf0, command);
else
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
}
cfi_command(bank, 0xf0, command);
}
cfi_command(bank, 0xf0, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_erase(struct flash_bank_s *bank, int first, int last)
}
static int cfi_erase(struct flash_bank_s *bank, int first, int last)
{
cfi_command(bank, 0x60, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
{
cfi_command(bank, 0x60, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
cfi_command(bank, 0x01, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
{
cfi_command(bank, 0x01, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
cfi_command(bank, 0xd0, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
{
cfi_command(bank, 0xd0, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
u8 block_status;
/* read block lock bit, to verify status */
cfi_command(bank, 0x90, command);
u8 block_status;
/* read block lock bit, to verify status */
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
{
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x60, command);
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x60, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x01, command);
{
return retval;
}
cfi_command(bank, 0x01, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
}
cfi_command(bank, 0xff, command);
}
cfi_command(bank, 0xff, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
}
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command);
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
/* Initiate buffer operation _*/
cfi_command(bank, 0xE8, command);
/* Initiate buffer operation _*/
cfi_command(bank, 0xE8, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
- if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0xd0, command);
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0xd0, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
u8 command[8];
cfi_command(bank, 0xaa, command);
u8 command[8];
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xa0, command);
{
return retval;
}
cfi_command(bank, 0xa0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
// Unlock
cfi_command(bank, 0xaa, command);
// Unlock
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
// Buffer load command
cfi_command(bank, 0x25, command);
{
return retval;
}
// Buffer load command
cfi_command(bank, 0x25, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
{
return retval;
}
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
- if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0x29, command);
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0x29, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
/* return to read array mode, so we can read from flash again for padding */
cfi_command(bank, 0xf0, current_word);
/* return to read array mode, so we can read from flash again for padding */
cfi_command(bank, 0xf0, current_word);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, current_word);
{
return retval;
}
cfi_command(bank, 0xff, current_word);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
/* return to read array mode */
cfi_command(bank, 0xf0, current_word);
/* return to read array mode */
cfi_command(bank, 0xf0, current_word);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, current_word);
{
return retval;
}
cfi_command(bank, 0xff, current_word);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
}
static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
}
static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
/* switch to read identifier codes mode ("AUTOSELECT") */
cfi_command(bank, 0xaa, command);
/* switch to read identifier codes mode ("AUTOSELECT") */
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x90, command);
{
return retval;
}
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
/* switch back to read array mode */
cfi_command(bank, 0xf0, command);
LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
/* switch back to read array mode */
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
* SST flashes clearly violate this, and we will consider them incompatbile for now
*/
cfi_command(bank, 0x98, command);
* SST flashes clearly violate this, and we will consider them incompatbile for now
*/
cfi_command(bank, 0x98, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
cfi_command(bank, 0xf0, command);
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/
cfi_command(bank, 0xf0, command);
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;
cfi_command(bank, 0x90, command);
return ERROR_FLASH_OPERATION_FAILED;
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
}
cfi_command(bank, 0xff, command);
}
cfi_command(bank, 0xff, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_spansion_protect_check(struct flash_bank_s *bank)
}
static int cfi_spansion_protect_check(struct flash_bank_s *bank)
int i;
cfi_command(bank, 0xaa, command);
int i;
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x90, command);
{
return retval;
}
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
}
cfi_command(bank, 0xf0, command);
}
cfi_command(bank, 0xf0, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_protect_check(struct flash_bank_s *bank)
}
static int cfi_protect_check(struct flash_bank_s *bank)
/* write IAP code to working area */
target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
/* write IAP code to working area */
target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
- if((retval = target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK)
+ if((retval = target_write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK)
* it seems not to be a LOT slower....
* bulk_write_memory() is no quicker :(*/
#if 1
* it seems not to be a LOT slower....
* bulk_write_memory() is no quicker :(*/
#if 1
- if (target->type->write_memory(target, offset + dest_offset, 4, 128, page_buffer) != ERROR_OK)
+ if (target_write_memory(target, offset + dest_offset, 4, 128, page_buffer) != ERROR_OK)
{
LOG_ERROR("Write failed s %x p %x", sector, page);
return ERROR_FLASH_OPERATION_FAILED;
{
LOG_ERROR("Write failed s %x p %x", sector, page);
return ERROR_FLASH_OPERATION_FAILED;
/* write MLC_ECC_ENC_REG to start encode cycle */
target_write_u32(target, 0x200b8008, 0x0);
/* write MLC_ECC_ENC_REG to start encode cycle */
target_write_u32(target, 0x200b8008, 0x0);
- target->type->write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
- target->type->write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
+ target_write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
+ target_write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
target_write_u32(target, 0x200b8010, 0x0);
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
target_write_u32(target, 0x200b8010, 0x0);
if (ret != ERROR_OK)
LOG_ERROR("mg_io_wait_drq time out");
if (ret != ERROR_OK)
LOG_ERROR("mg_io_wait_drq time out");
- ret = target->type->write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
+ ret = target_write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
if (ret != ERROR_OK)
LOG_ERROR("mem write error");
buff_ptr += MG_MFLASH_SECTOR_SIZE;
if (ret != ERROR_OK)
LOG_ERROR("mem write error");
buff_ptr += MG_MFLASH_SECTOR_SIZE;
for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++)
buff[i] = i;
for (i = 0; i < MG_MFLASH_SECTOR_SIZE >> 1; i++)
buff[i] = i;
- target->type->write_memory(target, address, 2,
+ target_write_memory(target, address, 2,
MG_MFLASH_SECTOR_SIZE / 2, (u8 *)buff);
memset(buff, 0xff, MG_MFLASH_SECTOR_SIZE);
MG_MFLASH_SECTOR_SIZE / 2, (u8 *)buff);
memset(buff, 0xff, MG_MFLASH_SECTOR_SIZE);
target_buffer_set_u32(target, code_buf + i*4, code[i]);
/* write code to working area */
target_buffer_set_u32(target, code_buf + i*4, code[i]);
/* write code to working area */
- retval = target->type->write_memory(target,
+ retval = target_write_memory(target,
hw->copy_area->address,
4, code_size/4, code_buf);
if (retval != ERROR_OK)
hw->copy_area->address,
4, code_size/4, code_buf);
if (retval != ERROR_OK)
retval = target->type->bulk_write_memory(target, target_buf,
size/4, data);
if (retval == ERROR_OK && size & 3) {
retval = target->type->bulk_write_memory(target, target_buf,
size/4, data);
if (retval == ERROR_OK && size & 3) {
- retval = target->type->write_memory(target,
+ retval = target_write_memory(target,
target_buf + (size & ~3),
1, size & 3, data + (size & ~3));
}
target_buf + (size & ~3),
1, size & 3, data + (size & ~3));
}
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */
- target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
+ target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
bytes_written += 4;
/* data word 2 */
bytes_written += 4;
/* data word 2 */
- target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
+ target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
bytes_written += 4;
/* start programming cycle */
bytes_written += 4;
/* start programming cycle */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
/* data word 1 */
- target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
+ target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
bytes_written += 4;
/* data word 2 */
bytes_written += 4;
/* data word 2 */
- target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
+ target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
bytes_written += 4;
/* start programming cycle */
bytes_written += 4;
/* start programming cycle */
/* write data command */
target_write_u16(target, bank_adr, 0x40);
/* write data command */
target_write_u16(target, bank_adr, 0x40);
- target->type->write_memory(target, address, 2, 1, buffer + bytes_written);
+ target_write_memory(target, address, 2, 1, buffer + bytes_written);
/* get status command */
target_write_u16(target, bank_adr, 0x70);
/* get status command */
target_write_u16(target, bank_adr, 0x70);
/* write data comamnd */
target_write_u16(target, bank_adr, 0x40);
/* write data comamnd */
target_write_u16(target, bank_adr, 0x40);
- target->type->write_memory(target, address, 2, 1, last_halfword);
+ target_write_memory(target, address, 2, 1, last_halfword);
/* query status command */
target_write_u16(target, bank_adr, 0x70);
/* query status command */
target_write_u16(target, bank_adr, 0x70);
return retval;
}
if (current_instr==arm7_9->arm_bkpt)
return retval;
}
if (current_instr==arm7_9->arm_bkpt)
- if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
return retval;
}
if (current_instr==arm7_9->thumb_bkpt)
return retval;
}
if (current_instr==arm7_9->thumb_bkpt)
- if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
int i;
if (!arm7_9->dcc_downloads)
int i;
if (!arm7_9->dcc_downloads)
- return target->type->write_memory(target, address, 4, count, buffer);
+ return target_write_memory(target, address, 4, count, buffer);
/* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area)
/* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area)
if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
{
LOG_INFO("no working area available, falling back to memory writes");
if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
{
LOG_INFO("no working area available, falling back to memory writes");
- return target->type->write_memory(target, address, 4, count, buffer);
+ return target_write_memory(target, address, 4, count, buffer);
}
/* copy target instructions to target endianness */
}
/* copy target instructions to target endianness */
}
/* write DCC code to working area */
}
/* write DCC code to working area */
- if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
+ if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
- if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
+ if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
{
return retval;
}
}
else
{
- if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
u32 dcc_size = sizeof(dcc_code);
if (!arm7_9->dcc_downloads)
u32 dcc_size = sizeof(dcc_code);
if (!arm7_9->dcc_downloads)
- return target->type->write_memory(target, address, 4, count, buffer);
+ return target_write_memory(target, address, 4, count, buffer);
/* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area)
/* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area)
if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
{
LOG_INFO("no working area available, falling back to memory writes");
if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
{
LOG_INFO("no working area available, falling back to memory writes");
- return target->type->write_memory(target, address, 4, count, buffer);
+ return target_write_memory(target, address, 4, count, buffer);
}
/* copy target instructions to target endianness */
}
/* copy target instructions to target endianness */
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */
- if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK)
+ if((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK)
}
if (current_instr == MIPS32_SDBBP)
{
}
if (current_instr == MIPS32_SDBBP)
{
- if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
if (current_instr == MIPS16_SDBBP)
{
if (current_instr == MIPS16_SDBBP)
{
- if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
return target->type->read_memory(target, address, size, count, buffer);
}
return target->type->read_memory(target, address, size, count, buffer);
}
+int target_write_memory(struct target_s *target,
+ u32 address, u32 size, u32 count, u8 *buffer)
+{
+ return target->type->write_memory(target, address, size, count, buffer);
+}
+
+
int target_init(struct command_context_s *cmd_ctx)
{
target_t *target = all_targets;
int target_init(struct command_context_s *cmd_ctx)
{
target_t *target = all_targets;
if (restore&&target->backup_working_area)
{
int retval;
if (restore&&target->backup_working_area)
{
int retval;
- if((retval = target->type->write_memory(target, area->address, 4, area->size / 4, area->backup)) != ERROR_OK)
+ if((retval = target_write_memory(target, area->address, 4, area->size / 4, area->backup)) != ERROR_OK)
if (((address % 2) == 0) && (size == 2))
{
if (((address % 2) == 0) && (size == 2))
{
- return target->type->write_memory(target, address, 2, 1, buffer);
+ return target_write_memory(target, address, 2, 1, buffer);
}
/* handle unaligned head bytes */
}
/* handle unaligned head bytes */
if (unaligned > size)
unaligned = size;
if (unaligned > size)
unaligned = size;
- if ((retval = target->type->write_memory(target, address, 1, unaligned, buffer)) != ERROR_OK)
+ if ((retval = target_write_memory(target, address, 1, unaligned, buffer)) != ERROR_OK)
return retval;
buffer += unaligned;
return retval;
buffer += unaligned;
- if ((retval = target->type->write_memory(target, address, 4, aligned / 4, buffer)) != ERROR_OK)
+ if ((retval = target_write_memory(target, address, 4, aligned / 4, buffer)) != ERROR_OK)
/* handle tail writes of less than 4 bytes */
if (size > 0)
{
/* handle tail writes of less than 4 bytes */
if (size > 0)
{
- if ((retval = target->type->write_memory(target, address, 1, size, buffer)) != ERROR_OK)
+ if ((retval = target_write_memory(target, address, 1, size, buffer)) != ERROR_OK)
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u32(target, value_buf, value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u32(target, value_buf, value);
- if ((retval = target->type->write_memory(target, address, 4, 1, value_buf)) != ERROR_OK)
+ if ((retval = target_write_memory(target, address, 4, 1, value_buf)) != ERROR_OK)
{
LOG_DEBUG("failed: %i", retval);
}
{
LOG_DEBUG("failed: %i", retval);
}
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u16(target, value_buf, value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u16(target, value_buf, value);
- if ((retval = target->type->write_memory(target, address, 2, 1, value_buf)) != ERROR_OK)
+ if ((retval = target_write_memory(target, address, 2, 1, value_buf)) != ERROR_OK)
{
LOG_DEBUG("failed: %i", retval);
}
{
LOG_DEBUG("failed: %i", retval);
}
LOG_DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);
- if ((retval = target->type->write_memory(target, address, 1, 1, &value)) != ERROR_OK)
+ if ((retval = target_write_memory(target, address, 1, 1, &value)) != ERROR_OK)
{
LOG_DEBUG("failed: %i", retval);
}
{
LOG_DEBUG("failed: %i", retval);
}
}
for (i=0; i<count; i++)
{
}
for (i=0; i<count; i++)
{
- int retval = target->type->write_memory(target,
+ int retval = target_write_memory(target,
address + i * wordsize, wordsize, 1, value_buf);
if (ERROR_OK != retval)
return retval;
address + i * wordsize, wordsize, 1, value_buf);
if (ERROR_OK != retval)
return retval;
- retval = target->type->write_memory(target, addr, width, count, buffer);
+ retval = target_write_memory(target, addr, width, count, buffer);
if (retval != ERROR_OK) {
/* BOO !*/
LOG_ERROR("array2mem: Write @ 0x%08x, w=%d, cnt=%d, failed", addr, width, count);
if (retval != ERROR_OK) {
/* BOO !*/
LOG_ERROR("array2mem: Write @ 0x%08x, w=%d, cnt=%d, failed", addr, width, count);
break;
}
for( x = 0 ; x < c ; x++ ){
break;
}
for( x = 0 ; x < c ; x++ ){
- e = target->type->write_memory( target, a, b, 1, target_buf );
+ e = target_write_memory( target, a, b, 1, target_buf );
if( e != ERROR_OK ){
Jim_SetResult_sprintf( interp, "Error writing @ 0x%08x: %d\n", (int)(a), e );
return JIM_ERR;
if( e != ERROR_OK ){
Jim_SetResult_sprintf( interp, "Error writing @ 0x%08x: %d\n", (int)(a), e );
return JIM_ERR;
*/
int (*read_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int (*write_memory_imp)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
*/
int (*read_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int (*write_memory_imp)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+ /**
+ * Target memory write callback. Do @b not call this function
+ * directly, use target_write_memory() instead.
+ */
int (*write_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
int (*write_memory)(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
*/
extern int target_read_memory(struct target_s *target,
u32 address, u32 size, u32 count, u8 *buffer);
*/
extern int target_read_memory(struct target_s *target,
u32 address, u32 size, u32 count, u8 *buffer);
+/**
+ * Write @count items of @a size bytes to the memory of @a target at
+ * the @a address given.
+ *
+ * This routine is wrapper for target->type->write_memory.
+ */
+extern int target_write_memory(struct target_s *target,
+ u32 address, u32 size, u32 count, u8 *buffer);
extern int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
extern int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
extern int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
extern int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
{
return retval;
}
}
else
{
- if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)