(saveRBank, unsaveRBank): don't save bits,
(genFunction, genEndFunction): save bits exactly once, fix bug
1535242
* support/regression/tests/bug1535242.c: new, added
git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4710
4a8a32a2-be11-0410-ad9d-
d568d2c75423
+2007-03-24 Maarten Brock <sourceforge.brock AT dse.nl>
+
+ * src/mcs51/gen.c (saveRegisters, unsaveRegisters): free some bitVects,
+ (saveRBank, unsaveRBank): don't save bits,
+ (genFunction, genEndFunction): save bits exactly once, fix bug 1535242
+ * support/regression/tests/bug1535242.c: new, added
+
2007-03-22 Borut Razem <borut.razem AT siol.net>
* debugger/mcs51/cmd.c, debugger/mcs51/sdcdb.c:
2007-03-22 Borut Razem <borut.razem AT siol.net>
* debugger/mcs51/cmd.c, debugger/mcs51/sdcdb.c:
};
extern struct dbuf_s *codeOutBuf;
};
extern struct dbuf_s *codeOutBuf;
-static void saveRBank (int, iCode *, bool);
#define RESULTONSTACK(x) \
(IC_RESULT(x) && IC_RESULT(x)->aop && \
#define RESULTONSTACK(x) \
(IC_RESULT(x) && IC_RESULT(x)->aop && \
rsave = bitVectCplAnd (rsave, rsavebits);
rsave = bitVectSetBit (rsave, bitVectFirstBit (rsavebits));
}
rsave = bitVectCplAnd (rsave, rsavebits);
rsave = bitVectSetBit (rsave, bitVectFirstBit (rsavebits));
}
+ freeBitVect (rsavebits);
}
/*-----------------------------------------------------------------*/
}
/*-----------------------------------------------------------------*/
rsave = bitVectCplAnd (rsave, rsavebits);
rsave = bitVectSetBit (rsave, bitVectFirstBit (rsavebits));
}
rsave = bitVectCplAnd (rsave, rsavebits);
rsave = bitVectSetBit (rsave, bitVectFirstBit (rsavebits));
}
+ freeBitVect (rsavebits);
saveRBank (int bank, iCode * ic, bool pushPsw)
{
int i;
saveRBank (int bank, iCode * ic, bool pushPsw)
{
int i;
- int count = 8 + ((mcs51_nRegs > 8) ? 1 : 0) + (pushPsw ? 1 : 0);
+ int count = 8 + (pushPsw ? 1 : 0);
asmop *aop = NULL;
regs *r = NULL;
asmop *aop = NULL;
regs *r = NULL;
if (!ic)
{
/* Assume r0 is available for use. */
if (!ic)
{
/* Assume r0 is available for use. */
- r = REG_WITH_INDEX (R0_IDX);;
+ r = REG_WITH_INDEX (R0_IDX);
regs8051[i].base, 8 * bank + regs8051[i].offset);
}
regs8051[i].base, 8 * bank + regs8051[i].offset);
}
- if (mcs51_nRegs > 8)
- {
- if (options.useXstack)
- {
- emitcode ("mov", "a,bits");
- emitcode ("movx", "@%s,a", r->name);
- if (--count)
- emitcode ("inc", "%s", r->name);
- }
- else
- {
- emitcode ("push", "bits");
- }
- BitBankUsed = 1;
- }
-
if (pushPsw)
{
if (options.useXstack)
if (pushPsw)
{
if (options.useXstack)
- if (mcs51_nRegs > 8)
- {
- if (options.useXstack)
- {
- emitcode ("dec", "%s", r->name);
- emitcode ("movx", "a,@%s", r->name);
- emitcode ("mov", "bits,a");
- }
- else
- {
- emitcode ("pop", "bits");
- }
- }
-
for (i = 7; i >= 0; i--)
{
if (options.useXstack)
for (i = 7; i >= 0; i--)
{
if (options.useXstack)
/* if we are calling a not _naked function that is not using
the same register bank then we need to save the
destination registers on the stack */
/* if we are calling a not _naked function that is not using
the same register bank then we need to save the
destination registers on the stack */
- if (currFunc && dtype && !IFFUNC_ISNAKED(dtype) &&
+ if (currFunc && dtype && !IFFUNC_ISNAKED (dtype) &&
(FUNC_REGBANK (currFunc->type) != FUNC_REGBANK (dtype)) &&
!IFFUNC_ISISR (dtype))
{
(FUNC_REGBANK (currFunc->type) != FUNC_REGBANK (dtype)) &&
!IFFUNC_ISISR (dtype))
{
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
- ((FUNC_REGBANK(dtype)) << 3) & 0xff);
+ ((FUNC_REGBANK (dtype)) << 3) & 0xff);
- if (IFFUNC_ISBANKEDCALL (dtype) && !SPEC_STAT(getSpec(dtype)))
+ if (IFFUNC_ISBANKEDCALL (dtype) && !SPEC_STAT (getSpec(dtype)))
- if (IFFUNC_CALLEESAVES(dtype))
+ if (IFFUNC_CALLEESAVES (dtype))
{
werror (E_BANKED_WITH_CALLEESAVES);
}
{
werror (E_BANKED_WITH_CALLEESAVES);
}
- if (IFFUNC_ISBANKEDCALL (dtype) && !SPEC_STAT(getSpec(dtype)))
+ if (IFFUNC_ISBANKEDCALL (dtype) && !SPEC_STAT (getSpec(dtype)))
- if (IFFUNC_CALLEESAVES(dtype))
+ if (IFFUNC_CALLEESAVES (dtype))
{
werror (E_BANKED_WITH_CALLEESAVES);
}
{
werror (E_BANKED_WITH_CALLEESAVES);
}
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
- ((FUNC_REGBANK(dtype)) << 3) & 0xff);
+ ((FUNC_REGBANK (dtype)) << 3) & 0xff);
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
- ((FUNC_REGBANK(dtype)) << 3) & 0xff);
+ ((FUNC_REGBANK (dtype)) << 3) & 0xff);
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
if (swapBanks)
{
emitcode ("mov", "psw,#0x%02x",
- ((FUNC_REGBANK(dtype)) << 3) & 0xff);
+ ((FUNC_REGBANK (dtype)) << 3) & 0xff);
- selectRegBank (FUNC_REGBANK(currFunc->type), IS_BIT (etype));
+ selectRegBank (FUNC_REGBANK (currFunc->type), IS_BIT (etype));
}
/* if we need assign a result value */
}
/* if we need assign a result value */
// unsaveRBank (FUNC_REGBANK (dtype), ic, TRUE);
/* if we had saved some registers then unsave them */
// unsaveRBank (FUNC_REGBANK (dtype), ic, TRUE);
/* if we had saved some registers then unsave them */
- if (ic->regsSaved && !IFFUNC_CALLEESAVES(dtype))
+ if (ic->regsSaved && !IFFUNC_CALLEESAVES (dtype))
unsaveRegisters (ic);
if (IS_BIT (OP_SYM_ETYPE (IC_RESULT (ic))))
unsaveRegisters (ic);
if (IS_BIT (OP_SYM_ETYPE (IC_RESULT (ic))))
save acc, b, dpl, dph */
if (IFFUNC_ISISR (sym->type))
{
save acc, b, dpl, dph */
if (IFFUNC_ISISR (sym->type))
{
+ bitVect *rsavebits;
+
+ rsavebits = bitVectIntersect (bitVectCopy (mcs51_allBitregs ()), sym->regsUsed);
+ if (IFFUNC_HASFCALL(sym->type) || !bitVectIsZero (rsavebits))
+ {
+ emitcode ("push", "bits");
+ BitBankUsed = 1;
+ }
+ freeBitVect (rsavebits);
+
if (!inExcludeList ("acc"))
emitcode ("push", "acc");
if (!inExcludeList ("b"))
if (!inExcludeList ("acc"))
emitcode ("push", "acc");
if (!inExcludeList ("b"))
/* if any registers used */
if (sym->regsUsed)
{
/* if any registers used */
if (sym->regsUsed)
{
- bool bits_pushed = FALSE;
/* save the registers used */
for (i = 0; i < sym->regsUsed->size; i++)
{
if (bitVectBitValue (sym->regsUsed, i))
/* save the registers used */
for (i = 0; i < sym->regsUsed->size; i++)
{
if (bitVectBitValue (sym->regsUsed, i))
- bits_pushed = pushReg (i, bits_pushed);
if (IFFUNC_ISISR (sym->type))
{
if (IFFUNC_ISISR (sym->type))
{
/* now we need to restore the registers */
/* if this isr has no bank i.e. is going to
/* now we need to restore the registers */
/* if this isr has no bank i.e. is going to
/* if any registers used */
if (sym->regsUsed)
{
/* if any registers used */
if (sym->regsUsed)
{
- bool bits_popped = FALSE;
/* save the registers used */
for (i = sym->regsUsed->size; i >= 0; i--)
{
if (bitVectBitValue (sym->regsUsed, i))
/* save the registers used */
for (i = sym->regsUsed->size; i >= 0; i--)
{
if (bitVectBitValue (sym->regsUsed, i))
- bits_popped = popReg (i, bits_popped);
emitcode ("pop","%s",rb1regs[i]);
}
}
emitcode ("pop","%s",rb1regs[i]);
}
}
- /* this function has a function call cannot
- determines register usage so we will have to pop the
+ /* this function has a function call. We cannot
+ determine register usage so we will have to pop the
entire bank */
unsaveRBank (0, ic, FALSE);
}
entire bank */
unsaveRBank (0, ic, FALSE);
}
if (!inExcludeList ("acc"))
emitcode ("pop", "acc");
if (!inExcludeList ("acc"))
emitcode ("pop", "acc");
+ rsavebits = bitVectIntersect (bitVectCopy (mcs51_allBitregs ()), sym->regsUsed);
+ if (IFFUNC_HASFCALL(sym->type) || !bitVectIsZero (rsavebits))
+ emitcode ("pop", "bits");
+ freeBitVect (rsavebits);
+
/* if debug then send end of function */
if (options.debug && currFunc)
{
/* if debug then send end of function */
if (options.debug && currFunc)
{
--- /dev/null
+/* saving "bits" test for mcs51/stack-auto.
+ */
+#include <testfwk.h>
+
+#if defined(SDCC_mcs51)
+#include <8052.h>
+#include <stdbool.h>
+
+bool manipulate_bits(bool x) using 2
+{
+ return x;
+}
+
+bool complement(bool x)
+{
+ return !x;
+}
+
+#endif
+
+void
+testSaveBits(void)
+{
+#if defined(SDCC_mcs51)
+
+ //enable the interrupt and set it
+ ET2 = 1;
+ EA = 1;
+ TF2 = 1;
+
+ //this will pass b0 cleared, test whether it will arrive cleared
+ if (complement(false))
+ {
+ EA = 0;
+ ASSERT(1);
+ }
+ else
+ {
+ EA = 0;
+ ASSERT(0);
+ }
+
+#else
+ ASSERT(1);
+#endif
+}
+
+#if defined(SDCC_mcs51)
+void T2_isr (void) interrupt 5 using 2
+{
+ //do not clear flag ET2 so it keeps interrupting !
+
+ //this will set b0
+ manipulate_bits(true);
+}
+#endif