+{
+ int mmu_enabled = 0;
+ int retval;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+
+ /* cortex_a handles unaligned memory access */
+ LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
+ size, count);
+
+ /* determine if MMU was enabled on target stop */
+ if (!armv7a->is_armv7r) {
+ retval = cortex_a_mmu(target, &mmu_enabled);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ if (mmu_enabled) {
+ retval = cortex_a_check_address(target, address);
+ if (retval != ERROR_OK)
+ return retval;
+ /* enable MMU as we could have disabled it for phys access */
+ retval = cortex_a_mmu_modify(target, 1);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ retval = cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
+
+ return retval;
+}
+
+static int cortex_a_write_memory_ahb(struct target *target, uint32_t address,
+ uint32_t size, uint32_t count, const uint8_t *buffer)