summary |
shortlog |
log |
commit | commitdiff |
tree
raw |
patch |
inline | side by side (from parent 1:
f068262)
Change-Id: I345658cfdc8a34a98418727423ac6bd562e980f3
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/3201
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
* Writes final value of DSCR into *dscr. Pass force to force always
* reading DSCR at least once. */
struct armv7a_common *armv7a = target_to_armv7a(target);
* Writes final value of DSCR into *dscr. Pass force to force always
* reading DSCR at least once. */
struct armv7a_common *armv7a = target_to_armv7a(target);
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
force = false;
int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
force = false;
int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
do {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
do {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
}
/* Wait for DTRRXfull then read DTRRTX */
}
/* Wait for DTRRXfull then read DTRRTX */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
dscr = *dscr_p;
/* Wait for DTRRXfull */
dscr = *dscr_p;
/* Wait for DTRRXfull */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
for (;; ) {
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while (target->state != TARGET_HALTED) {
retval = cortex_a_poll(target);
if (retval != ERROR_OK)
while (target->state != TARGET_HALTED) {
retval = cortex_a_poll(target);
if (retval != ERROR_OK)
{
/* Waits until the specified bit(s) of DSCR take on a specified value. */
struct armv7a_common *armv7a = target_to_armv7a(target);
{
/* Waits until the specified bit(s) of DSCR take on a specified value. */
struct armv7a_common *armv7a = target_to_armv7a(target);
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
int retval;
while ((*dscr & mask) != value) {
int retval;
while ((*dscr & mask) != value) {
armv7a->debug_base + CPUDBG_DSCR, &dscr);
/* check if we have data */
armv7a->debug_base + CPUDBG_DSCR, &dscr);
/* check if we have data */
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &request);
while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &request);
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
}
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
}
+ if (timeval_ms() > then + 1000) {
+ LOG_ERROR("Timeout waiting for dtr tx full");
+ return ERROR_FAIL;
+ }