Remove old mac. Good riddance.
authorMatt Ettus <matt@ettus.com>
Fri, 11 Sep 2009 06:11:44 +0000 (23:11 -0700)
committerMatt Ettus <matt@ettus.com>
Fri, 11 Sep 2009 06:11:44 +0000 (23:11 -0700)
commitab47612cf0b6f2226d192fbc9db80c5b225a4f2d
treefd850548b20709a0c2d5c5bb751f4a28984533cf
parent1e585a79df197653b752427b4372895e12afc2d4
Remove old mac.  Good riddance.
64 files changed:
usrp2/fpga/eth/bench/verilog/.gitignore [deleted file]
usrp2/fpga/eth/bench/verilog/100m.scr [deleted file]
usrp2/fpga/eth/bench/verilog/Phy_sim.v [deleted file]
usrp2/fpga/eth/bench/verilog/User_int_sim.v [deleted file]
usrp2/fpga/eth/bench/verilog/error.scr [deleted file]
usrp2/fpga/eth/bench/verilog/files.lst [deleted file]
usrp2/fpga/eth/bench/verilog/host_sim.v [deleted file]
usrp2/fpga/eth/bench/verilog/icomp.bat [deleted file]
usrp2/fpga/eth/bench/verilog/isim.bat [deleted file]
usrp2/fpga/eth/bench/verilog/jumbo_err.scr [deleted file]
usrp2/fpga/eth/bench/verilog/jumbos.scr [deleted file]
usrp2/fpga/eth/bench/verilog/mdio.scr [deleted file]
usrp2/fpga/eth/bench/verilog/miim_model.v [deleted file]
usrp2/fpga/eth/bench/verilog/misc.scr [deleted file]
usrp2/fpga/eth/bench/verilog/pause.scr [deleted file]
usrp2/fpga/eth/bench/verilog/tb_top.v [deleted file]
usrp2/fpga/eth/bench/verilog/test.scr [deleted file]
usrp2/fpga/eth/bench/verilog/txmac.scr [deleted file]
usrp2/fpga/eth/bench/verilog/xlnx_glbl.v [deleted file]
usrp2/fpga/eth/demo/verilog/RAMB16_S1_S2.v [deleted file]
usrp2/fpga/eth/demo/verilog/demo.ucf [deleted file]
usrp2/fpga/eth/demo/verilog/demo.v [deleted file]
usrp2/fpga/eth/demo/verilog/demo_packet_descriptor_memory.v [deleted file]
usrp2/fpga/eth/demo/verilog/demo_packet_generator.v [deleted file]
usrp2/fpga/eth/demo/verilog/demo_uart.v [deleted file]
usrp2/fpga/eth/demo/verilog/demo_wishbone_master.v [deleted file]
usrp2/fpga/eth/demo/verilog/tb_demo.v [deleted file]
usrp2/fpga/eth/header_ram.v [deleted file]
usrp2/fpga/eth/mac_rxfifo_int.v [deleted file]
usrp2/fpga/eth/mac_txfifo_int.v [deleted file]
usrp2/fpga/eth/rtl/verilog/Clk_ctrl.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_rx.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_rx/Broadcast_filter.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_top.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_tx.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v [deleted file]
usrp2/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v [deleted file]
usrp2/fpga/eth/rtl/verilog/Phy_int.v [deleted file]
usrp2/fpga/eth/rtl/verilog/RMON.v [deleted file]
usrp2/fpga/eth/rtl/verilog/RMON/RMON_addr_gen.v [deleted file]
usrp2/fpga/eth/rtl/verilog/RMON/RMON_ctrl.v [deleted file]
usrp2/fpga/eth/rtl/verilog/Reg_int.v [deleted file]
usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v [deleted file]
usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_switch.v [deleted file]
usrp2/fpga/eth/rtl/verilog/TECH/xilinx/BUFGMUX.v [deleted file]
usrp2/fpga/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v [deleted file]
usrp2/fpga/eth/rtl/verilog/elastic_buffer.v [deleted file]
usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v [deleted file]
usrp2/fpga/eth/rtl/verilog/eth_miim.v [deleted file]
usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v [deleted file]
usrp2/fpga/eth/rtl/verilog/flow_ctrl_tx.v [deleted file]
usrp2/fpga/eth/rtl/verilog/header.vh [deleted file]
usrp2/fpga/eth/rtl/verilog/miim/eth_clockgen.v [deleted file]
usrp2/fpga/eth/rtl/verilog/miim/eth_outputcontrol.v [deleted file]
usrp2/fpga/eth/rtl/verilog/miim/eth_shiftreg.v [deleted file]
usrp2/fpga/eth/rx_prot_engine.v [deleted file]
usrp2/fpga/eth/tx_prot_engine.v [deleted file]