Properly reset the fifos. We didn't connect before.
authorMatt Ettus <matt@ettus.com>
Mon, 5 Oct 2009 09:15:10 +0000 (02:15 -0700)
committerMatt Ettus <matt@ettus.com>
Mon, 5 Oct 2009 09:15:10 +0000 (02:15 -0700)
commit61926130bef20051001f97abfae4c16ffc7963f6
treed59579154742a6cd7f807696e3712c633ad52a57
parentbf76534044a1bbcc665f0400a53d1070cae8caf0
Properly reset the fifos.  We didn't connect before.
usrp2/fpga/control_lib/newfifo/fifo_2clock.v