seems to build a decent fpga, but still some issues with a full connection.
authorMatt Ettus <matt@ettus.com>
Fri, 4 Sep 2009 04:39:48 +0000 (21:39 -0700)
committerMatt Ettus <matt@ettus.com>
Fri, 4 Sep 2009 04:39:48 +0000 (21:39 -0700)
commit5965a434d0923738d49334eb5f3d74a259e7b431
tree79f75c69c85e399a9ba9b5eac849962fdb0915bc
parent43dec22f22e9c47b4f908675ac880a05377993fa
seems to build a decent fpga, but still some issues with a full connection.
usrp2/fpga/sdr_lib/rx_control.v
usrp2/fpga/sdr_lib/tx_control.v
usrp2/fpga/top/u2_core/u2_core.v