Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top...
authorjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>
Mon, 8 Sep 2008 01:00:12 +0000 (01:00 +0000)
committerjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>
Mon, 8 Sep 2008 01:00:12 +0000 (01:00 +0000)
commite0fcbaee124d3e8c4c11bdda662f88e082352058
treea51ef1c8b949681f45e5664478e8515065cfff5b
parentc86f6c23c6883f73d953d64c28ab42cedb77e4d7
Merged r9433:9527 from features/gr-usrp2 into trunk.  Adds usrp2 and gr-usrp2 top-level components.  Trunk passes distcheck with mb-gcc installed, but currently not without them.  The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball.  But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
1269 files changed:
Makefile.am
bootstrap
config/Makefile.am
config/grc_gr_usrp2.m4 [new file with mode: 0644]
config/grc_usrp2.m4 [new file with mode: 0644]
configure.ac
gnuradio-core/src/utils/Makefile.am
gnuradio-core/src/utils/read_cshort_binary.m [new file with mode: 0644]
gr-usrp2/Makefile.am [new file with mode: 0644]
gr-usrp2/src/Makefile.am [new file with mode: 0644]
gr-usrp2/src/qa_usrp2.py [new file with mode: 0755]
gr-usrp2/src/run_tests.in [new file with mode: 0644]
gr-usrp2/src/rx_16sc_handler.cc [new file with mode: 0644]
gr-usrp2/src/rx_16sc_handler.h [new file with mode: 0644]
gr-usrp2/src/rx_32fc_handler.cc [new file with mode: 0644]
gr-usrp2/src/rx_32fc_handler.h [new file with mode: 0644]
gr-usrp2/src/usrp2.i [new file with mode: 0644]
gr-usrp2/src/usrp2_sink_32fc.cc [new file with mode: 0644]
gr-usrp2/src/usrp2_sink_32fc.h [new file with mode: 0644]
gr-usrp2/src/usrp2_sink_base.cc [new file with mode: 0644]
gr-usrp2/src/usrp2_sink_base.h [new file with mode: 0644]
gr-usrp2/src/usrp2_source_16sc.cc [new file with mode: 0644]
gr-usrp2/src/usrp2_source_16sc.h [new file with mode: 0644]
gr-usrp2/src/usrp2_source_32fc.cc [new file with mode: 0644]
gr-usrp2/src/usrp2_source_32fc.h [new file with mode: 0644]
gr-usrp2/src/usrp2_source_base.cc [new file with mode: 0644]
gr-usrp2/src/usrp2_source_base.h [new file with mode: 0644]
gr-utils/src/python/Makefile.am
gr-utils/src/python/usrp2_fft.py [new file with mode: 0755]
gr-utils/src/python/usrp2_rx_cfile.py [new file with mode: 0755]
usrp2/Makefile.am [new file with mode: 0644]
usrp2/doc/inband-signaling-eth [new file with mode: 0644]
usrp2/firmware/AUTHORS [new file with mode: 0644]
usrp2/firmware/COPYING [new file with mode: 0644]
usrp2/firmware/ChangeLog [new file with mode: 0644]
usrp2/firmware/INSTALL [new file with mode: 0644]
usrp2/firmware/Makefile.am [new file with mode: 0644]
usrp2/firmware/Makefile.common [new file with mode: 0644]
usrp2/firmware/NEWS [new file with mode: 0644]
usrp2/firmware/README [new file with mode: 0644]
usrp2/firmware/apps/Makefile.am [new file with mode: 0644]
usrp2/firmware/apps/app_common_v2.c [new file with mode: 0644]
usrp2/firmware/apps/app_common_v2.h [new file with mode: 0644]
usrp2/firmware/apps/app_passthru_v2.c [new file with mode: 0644]
usrp2/firmware/apps/app_passthru_v2.h [new file with mode: 0644]
usrp2/firmware/apps/bitrot/tx_drop.c [new file with mode: 0644]
usrp2/firmware/apps/bitrot/tx_drop2.c [new file with mode: 0644]
usrp2/firmware/apps/bitrot/tx_drop_rate_limited.c [new file with mode: 0644]
usrp2/firmware/apps/blink_leds.c [new file with mode: 0644]
usrp2/firmware/apps/blink_leds2.c [new file with mode: 0644]
usrp2/firmware/apps/buf_ram_test.c [new file with mode: 0644]
usrp2/firmware/apps/can_i_sub.c [new file with mode: 0644]
usrp2/firmware/apps/double_buffer_fragment.c [new file with mode: 0644]
usrp2/firmware/apps/echo.c [new file with mode: 0644]
usrp2/firmware/apps/eth_serdes.c [new file with mode: 0644]
usrp2/firmware/apps/gen_eth_packets.c [new file with mode: 0644]
usrp2/firmware/apps/gen_pause_frames.c [new file with mode: 0644]
usrp2/firmware/apps/hello.c [new file with mode: 0644]
usrp2/firmware/apps/ibs_rx_test.c [new file with mode: 0644]
usrp2/firmware/apps/ibs_tx_test.c [new file with mode: 0644]
usrp2/firmware/apps/rcv_eth_packets.c [new file with mode: 0644]
usrp2/firmware/apps/read_dbids.c [new file with mode: 0644]
usrp2/firmware/apps/rx_only_v2.c [new file with mode: 0644]
usrp2/firmware/apps/sd_bounce.c [new file with mode: 0644]
usrp2/firmware/apps/sd_gentest.c [new file with mode: 0644]
usrp2/firmware/apps/serdes_to_dsp.c [new file with mode: 0644]
usrp2/firmware/apps/serdes_txrx.c [new file with mode: 0644]
usrp2/firmware/apps/test1.c [new file with mode: 0644]
usrp2/firmware/apps/test_db_spi.c [new file with mode: 0644]
usrp2/firmware/apps/test_i2c.c [new file with mode: 0644]
usrp2/firmware/apps/test_lsadc.c [new file with mode: 0644]
usrp2/firmware/apps/test_lsdac.c [new file with mode: 0644]
usrp2/firmware/apps/test_phy_comm.c [new file with mode: 0644]
usrp2/firmware/apps/test_serdes.c [new file with mode: 0644]
usrp2/firmware/apps/timer_test.c [new file with mode: 0644]
usrp2/firmware/apps/tx_only_v2.c [new file with mode: 0644]
usrp2/firmware/apps/tx_standalone.c [new file with mode: 0644]
usrp2/firmware/apps/txrx.c [new file with mode: 0644]
usrp2/firmware/bootstrap [new file with mode: 0755]
usrp2/firmware/config.guess [new file with mode: 0644]
usrp2/firmware/config.sub [new file with mode: 0644]
usrp2/firmware/configure.ac [new file with mode: 0644]
usrp2/firmware/divisors.py [new file with mode: 0755]
usrp2/firmware/include/Makefile.am [new file with mode: 0644]
usrp2/firmware/include/usrp2_cdefs.h [new file with mode: 0644]
usrp2/firmware/include/usrp2_eth_packet.h [new file with mode: 0644]
usrp2/firmware/include/usrp2_fpga_regs.h [new file with mode: 0644]
usrp2/firmware/include/usrp2_i2c_addr.h [new file with mode: 0644]
usrp2/firmware/include/usrp2_mac_addr.h [new file with mode: 0644]
usrp2/firmware/include/usrp2_mimo_config.h [new file with mode: 0644]
usrp2/firmware/include/usrp2_types.h [new file with mode: 0644]
usrp2/firmware/lib/Makefile.am [new file with mode: 0644]
usrp2/firmware/lib/ad9510.c [new file with mode: 0644]
usrp2/firmware/lib/ad9510.h [new file with mode: 0644]
usrp2/firmware/lib/ad9777.c [new file with mode: 0644]
usrp2/firmware/lib/ad9777.h [new file with mode: 0644]
usrp2/firmware/lib/ad9777_regs.h [new file with mode: 0644]
usrp2/firmware/lib/bool.h [new file with mode: 0644]
usrp2/firmware/lib/buffer_pool.c [new file with mode: 0644]
usrp2/firmware/lib/buffer_pool.h [new file with mode: 0644]
usrp2/firmware/lib/clocks.c [new file with mode: 0644]
usrp2/firmware/lib/clocks.h [new file with mode: 0644]
usrp2/firmware/lib/db.h [new file with mode: 0644]
usrp2/firmware/lib/db_base.h [new file with mode: 0644]
usrp2/firmware/lib/db_basic.c [new file with mode: 0644]
usrp2/firmware/lib/db_init.c [new file with mode: 0644]
usrp2/firmware/lib/db_rfx.c [new file with mode: 0644]
usrp2/firmware/lib/db_tvrx.c [new file with mode: 0644]
usrp2/firmware/lib/dbsm.c [new file with mode: 0644]
usrp2/firmware/lib/dbsm.h [new file with mode: 0644]
usrp2/firmware/lib/eeprom.c [new file with mode: 0644]
usrp2/firmware/lib/eth_mac.c [new file with mode: 0644]
usrp2/firmware/lib/eth_mac.h [new file with mode: 0644]
usrp2/firmware/lib/eth_mac_regs.h [new file with mode: 0644]
usrp2/firmware/lib/eth_phy.h [new file with mode: 0644]
usrp2/firmware/lib/ethernet.c [new file with mode: 0644]
usrp2/firmware/lib/ethernet.h [new file with mode: 0644]
usrp2/firmware/lib/hal_io.c [new file with mode: 0644]
usrp2/firmware/lib/hal_io.h [new file with mode: 0644]
usrp2/firmware/lib/hal_uart.c [new file with mode: 0644]
usrp2/firmware/lib/hal_uart.h [new file with mode: 0644]
usrp2/firmware/lib/i2c.c [new file with mode: 0644]
usrp2/firmware/lib/i2c.h [new file with mode: 0644]
usrp2/firmware/lib/lsadc.c [new file with mode: 0644]
usrp2/firmware/lib/lsadc.h [new file with mode: 0644]
usrp2/firmware/lib/lsdac.c [new file with mode: 0644]
usrp2/firmware/lib/lsdac.h [new file with mode: 0644]
usrp2/firmware/lib/mdelay.c [new file with mode: 0644]
usrp2/firmware/lib/mdelay.h [new file with mode: 0644]
usrp2/firmware/lib/memcpy_wa.c [new file with mode: 0644]
usrp2/firmware/lib/memcpy_wa.h [new file with mode: 0644]
usrp2/firmware/lib/memory_map.h [new file with mode: 0644]
usrp2/firmware/lib/memset_wa.c [new file with mode: 0644]
usrp2/firmware/lib/memset_wa.h [new file with mode: 0644]
usrp2/firmware/lib/microblaze.ld [new file with mode: 0644]
usrp2/firmware/lib/nonstdio.c [new file with mode: 0644]
usrp2/firmware/lib/nonstdio.h [new file with mode: 0644]
usrp2/firmware/lib/pic.c [new file with mode: 0644]
usrp2/firmware/lib/pic.h [new file with mode: 0644]
usrp2/firmware/lib/print_buffer.c [new file with mode: 0644]
usrp2/firmware/lib/print_fxpt.c [new file with mode: 0644]
usrp2/firmware/lib/print_mac_addr.c [new file with mode: 0644]
usrp2/firmware/lib/print_rmon_regs.c [new file with mode: 0644]
usrp2/firmware/lib/print_rmon_regs.h [new file with mode: 0644]
usrp2/firmware/lib/printf.c [new file with mode: 0644]
usrp2/firmware/lib/printf.c.smaller [new file with mode: 0644]
usrp2/firmware/lib/spi.c [new file with mode: 0644]
usrp2/firmware/lib/spi.h [new file with mode: 0644]
usrp2/firmware/lib/stdint.h [new file with mode: 0644]
usrp2/firmware/lib/stdio.h [new file with mode: 0644]
usrp2/firmware/lib/u2_init.c [new file with mode: 0644]
usrp2/firmware/lib/u2_init.h [new file with mode: 0644]
usrp2/firmware/lib/usrp2_bytesex.h [new file with mode: 0644]
usrp2/firmware/lib/wb16550.h [new file with mode: 0644]
usrp2/firmware/u2_flash_tool [new file with mode: 0755]
usrp2/fpga/boot_cpld/_impact.cmd [new file with mode: 0755]
usrp2/fpga/boot_cpld/boot_cpld.ipf [new file with mode: 0755]
usrp2/fpga/boot_cpld/boot_cpld.ise [new file with mode: 0755]
usrp2/fpga/boot_cpld/boot_cpld.lfp [new file with mode: 0755]
usrp2/fpga/boot_cpld/boot_cpld.ucf [new file with mode: 0755]
usrp2/fpga/boot_cpld/boot_cpld.v [new file with mode: 0755]
usrp2/fpga/control_lib/CRC16_D16.v [new file with mode: 0644]
usrp2/fpga/control_lib/SYSCTRL.sav [new file with mode: 0644]
usrp2/fpga/control_lib/WB_SIM.sav [new file with mode: 0644]
usrp2/fpga/control_lib/atr_controller.v [new file with mode: 0644]
usrp2/fpga/control_lib/bin2gray.v [new file with mode: 0644]
usrp2/fpga/control_lib/bootrom.mem [new file with mode: 0644]
usrp2/fpga/control_lib/buffer_int.v [new file with mode: 0644]
usrp2/fpga/control_lib/buffer_int_tb.v [new file with mode: 0644]
usrp2/fpga/control_lib/buffer_pool.v [new file with mode: 0644]
usrp2/fpga/control_lib/buffer_pool_tb.v [new file with mode: 0644]
usrp2/fpga/control_lib/cascadefifo.v [new file with mode: 0644]
usrp2/fpga/control_lib/cascadefifo2.v [new file with mode: 0644]
usrp2/fpga/control_lib/clock_bootstrap_rom.v [new file with mode: 0644]
usrp2/fpga/control_lib/clock_control.v [new file with mode: 0644]
usrp2/fpga/control_lib/clock_control_tb.sav [new file with mode: 0644]
usrp2/fpga/control_lib/clock_control_tb.v [new file with mode: 0644]
usrp2/fpga/control_lib/cmdfile [new file with mode: 0644]
usrp2/fpga/control_lib/dcache.v [new file with mode: 0644]
usrp2/fpga/control_lib/decoder_3_8.v [new file with mode: 0644]
usrp2/fpga/control_lib/dpram32.v [new file with mode: 0644]
usrp2/fpga/control_lib/extram_interface.v [new file with mode: 0644]
usrp2/fpga/control_lib/fifo_2clock.v [new file with mode: 0644]
usrp2/fpga/control_lib/fifo_2clock_casc.v [new file with mode: 0644]
usrp2/fpga/control_lib/fifo_reader.v [new file with mode: 0644]
usrp2/fpga/control_lib/fifo_tb.v [new file with mode: 0644]
usrp2/fpga/control_lib/fifo_writer.v [new file with mode: 0644]
usrp2/fpga/control_lib/gray2bin.v [new file with mode: 0644]
usrp2/fpga/control_lib/gray_send.v [new file with mode: 0644]
usrp2/fpga/control_lib/icache.v [new file with mode: 0644]
usrp2/fpga/control_lib/longfifo.v [new file with mode: 0644]
usrp2/fpga/control_lib/medfifo.v [new file with mode: 0644]
usrp2/fpga/control_lib/mux4.v [new file with mode: 0644]
usrp2/fpga/control_lib/mux8.v [new file with mode: 0644]
usrp2/fpga/control_lib/mux_32_4.v [new file with mode: 0644]
usrp2/fpga/control_lib/nsgpio.v [new file with mode: 0644]
usrp2/fpga/control_lib/oneshot_2clk.v [new file with mode: 0644]
usrp2/fpga/control_lib/ram_2port.v [new file with mode: 0644]
usrp2/fpga/control_lib/ram_harv_cache.v [new file with mode: 0644]
usrp2/fpga/control_lib/ram_loader.v [new file with mode: 0644]
usrp2/fpga/control_lib/ram_wb_harvard.v [new file with mode: 0644]
usrp2/fpga/control_lib/sd_spi.v [new file with mode: 0644]
usrp2/fpga/control_lib/sd_spi_tb.v [new file with mode: 0644]
usrp2/fpga/control_lib/sd_spi_wb.v [new file with mode: 0644]
usrp2/fpga/control_lib/setting_reg.v [new file with mode: 0644]
usrp2/fpga/control_lib/settings_bus.v [new file with mode: 0644]
usrp2/fpga/control_lib/shortfifo.v [new file with mode: 0644]
usrp2/fpga/control_lib/simple_uart.v [new file with mode: 0644]
usrp2/fpga/control_lib/simple_uart_rx.v [new file with mode: 0644]
usrp2/fpga/control_lib/simple_uart_tx.v [new file with mode: 0644]
usrp2/fpga/control_lib/spi.v [new file with mode: 0644]
usrp2/fpga/control_lib/srl.v [new file with mode: 0644]
usrp2/fpga/control_lib/ss_rcvr.v [new file with mode: 0644]
usrp2/fpga/control_lib/system_control.v [new file with mode: 0644]
usrp2/fpga/control_lib/system_control_tb.v [new file with mode: 0644]
usrp2/fpga/control_lib/traffic_cop.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_1master.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_bus_writer.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_output_pins32.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_ram_block.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_ram_dist.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_readback_mux.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_regfile_2clock.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_semaphore.v [new file with mode: 0644]
usrp2/fpga/control_lib/wb_sim.v [new file with mode: 0644]
usrp2/fpga/coregen/coregen.cgp [new file with mode: 0644]
usrp2/fpga/coregen/fifo_generator_release_notes.txt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_generator_ug175.pdf [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.asy [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_flist.txt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.asy [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.sym [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vhd [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vho [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/100m.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/Phy_sim.v [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/User_int_sim.v [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/error.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/files.lst [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/host_sim.v [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/icomp.bat [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/isim.bat [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/jumbo_err.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/jumbos.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/mdio.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/miim_model.v [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/misc.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/pause.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/tb_top.v [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/test.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/txmac.scr [new file with mode: 0644]
usrp2/fpga/eth/bench/verilog/xlnx_glbl.v [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/RAMB16_S1_S2.v [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/demo.ucf [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/demo.v [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/demo_packet_descriptor_memory.v [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/demo_packet_generator.v [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/demo_uart.v [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/demo_wishbone_master.v [new file with mode: 0644]
usrp2/fpga/eth/demo/verilog/tb_demo.v [new file with mode: 0644]
usrp2/fpga/eth/header_ram.v [new file with mode: 0644]
usrp2/fpga/eth/mac_rxfifo_int.v [new file with mode: 0644]
usrp2/fpga/eth/mac_txfifo_int.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/Clk_ctrl.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_rx.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_rx/Broadcast_filter.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_top.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_tx.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/Phy_int.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/RMON.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/RMON/RMON_addr_gen.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/RMON/RMON_ctrl.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/Reg_int.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_switch.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/TECH/xilinx/BUFGMUX.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/elastic_buffer.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/eth_miim.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/flow_ctrl_tx.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/header.vh [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/miim/eth_clockgen.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/miim/eth_outputcontrol.v [new file with mode: 0644]
usrp2/fpga/eth/rtl/verilog/miim/eth_shiftreg.v [new file with mode: 0644]
usrp2/fpga/eth/rx_prot_engine.v [new file with mode: 0644]
usrp2/fpga/eth/tx_prot_engine.v [new file with mode: 0644]
usrp2/fpga/models/BUFG.v [new file with mode: 0644]
usrp2/fpga/models/CY7C1356C/cy1356.inp [new file with mode: 0644]
usrp2/fpga/models/CY7C1356C/cy1356.v [new file with mode: 0644]
usrp2/fpga/models/CY7C1356C/readme.txt [new file with mode: 0644]
usrp2/fpga/models/CY7C1356C/testbench.v [new file with mode: 0644]
usrp2/fpga/models/FIFO_GENERATOR_V4_3.v [new file with mode: 0644]
usrp2/fpga/models/M24LC024B.v [new file with mode: 0644]
usrp2/fpga/models/M24LC02B.v [new file with mode: 0644]
usrp2/fpga/models/MULT18X18S.v [new file with mode: 0644]
usrp2/fpga/models/RAMB16_S36_S36.v [new file with mode: 0644]
usrp2/fpga/models/SRL16E.v [new file with mode: 0644]
usrp2/fpga/models/SRLC16E.v [new file with mode: 0644]
usrp2/fpga/models/adc_model.v [new file with mode: 0644]
usrp2/fpga/models/cpld_model.v [new file with mode: 0644]
usrp2/fpga/models/math_real.v [new file with mode: 0644]
usrp2/fpga/models/serdes_model.v [new file with mode: 0644]
usrp2/fpga/models/uart_rx.v [new file with mode: 0644]
usrp2/fpga/opencores/8b10b/8b10b_a.mem [new file with mode: 0644]
usrp2/fpga/opencores/8b10b/README [new file with mode: 0644]
usrp2/fpga/opencores/8b10b/decode_8b10b.v [new file with mode: 0644]
usrp2/fpga/opencores/8b10b/encode_8b10b.v [new file with mode: 0644]
usrp2/fpga/opencores/8b10b/validate_8b10b.v [new file with mode: 0644]
usrp2/fpga/opencores/README [new file with mode: 0644]
usrp2/fpga/opencores/aemb/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/doc/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/doc/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/doc/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/doc/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/doc/aeMB_datasheet.pdf [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_bpcu.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_regf.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/CODE_DEBUG.sav [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/cversim [new file with mode: 0755]
usrp2/fpga/opencores/aemb/sim/iversim [new file with mode: 0755]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/verilog/aemb2.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sim/verilog/edk32.v [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/c/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/c/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/c/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/c/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/c/aeMB_testbench.c [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/c/endian-test.c [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/c/libaemb.h [new file with mode: 0644]
usrp2/fpga/opencores/aemb/sw/gccrom [new file with mode: 0755]
usrp2/fpga/opencores/ethernet_tri_mode/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/altera_mf.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/host_sim.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/reg_int_sim.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/tb_top.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/cmdfile [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/doc/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/doc/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/doc/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/doc/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/doc/Tri-mode_Ethernet_MAC_Specifications.pdf [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/doc/Tri-mode_Ethernet_MAC_Verification_plan.pdf [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/Clk_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/Broadcast_filter.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/CRC_chk.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_add_chk.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CRC_gen.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_addr_add.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/flow_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/Phy_int.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_addr_gen.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CLK_SWITCH.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_DIV2.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_SWITCH.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/duram.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CLK_DIV2.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CLK_SWITCH.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/duram.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/cmdfile [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/eth_miim.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/eth_wrapper.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/header.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/mac_tb.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_clockgen.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_outputcontrol.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_shiftreg.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/timescale.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/cds.lib [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/com.nc [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/config.ini [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/hdl.var [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim.nc [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim_only.nc [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/vlog.list [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/46-50.ini [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CPU.vec [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/batch.dat [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/config.ini [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/ncsim.log [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/filesel.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run_proc.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/start_verify.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/user_lib.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/start.tcl [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/syn/syn.prj [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_altrea.prj [new file with mode: 0644]
usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_xilinx.prj [new file with mode: 0644]
usrp2/fpga/opencores/i2c/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/i2c_slave_model.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/spi_slave_model.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/tst_bench_top.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/bench/verilog/wb_master_model.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/i2c_specs.pdf [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/src/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/src/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/src/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/src/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/doc/src/I2C_specs.doc [new file with mode: 0644]
usrp2/fpga/opencores/i2c/documentation/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/documentation/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/documentation/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/documentation/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_top.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/verilog/timescale.v [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/I2C.VHD [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_top.vhd [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/readme [new file with mode: 0644]
usrp2/fpga/opencores/i2c/rtl/vhdl/tst_ds1621.vhd [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/bench.vcd [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.key [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.log [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/run [new file with mode: 0755]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/include/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/include/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/include/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/include/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/software/include/oc_i2c_master.h [new file with mode: 0644]
usrp2/fpga/opencores/i2c/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/i2c/vhdl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/i2c/vhdl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/i2c/vhdl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/i2c/vhdl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/RxFifo.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/RxFifoBI.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/TxFifo.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/TxFifoBI.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/ctrlStsRegBI.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/dpMem_dc.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/fifoRTL.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/initSD.asf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/initSD.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.asf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/readWriteSPIWireData.asf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/readWriteSPIWireData.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/sendCmd.asf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/sendCmd.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.asf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/spiMaster.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/spiMaster_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/spiTxRxData.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/timescale.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/RTL/wishBoneBI.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/bench/testCase0.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/bench/testHarness.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/doc/spiMaster_FSM.pdf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/doc/spiMaster_Specification.pdf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/doc/src/spiMaster_Specification.sxw [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/model/sdModel.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/model/wb_master_model.v [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/sim/build_icarus.bat [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/sim/compile.do [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/sim/filelist.icarus [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/sim/run.do [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/sim/run_icarus.bat [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/sim/testHarness [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/sim/wave.do [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/syn/spiMaster.qpf [new file with mode: 0644]
usrp2/fpga/opencores/sd_interface/syn/spiMaster.qsf [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/simple_gpio/rtl/simple_gpio.v [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/simple_pic/rtl/simple_pic.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/verilog/spi_slave_model.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/verilog/tb_spi_top.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/bench/verilog/wb_master_model.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/spi.pdf [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/src/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/src/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/src/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/src/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/doc/src/spi.doc [new file with mode: 0755]
usrp2/fpga/opencores/spi/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/spi_clgen.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/spi_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/spi_shift.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/spi_top.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/rtl/verilog/timescale.v [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/rtl.fl [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/run_sim [new file with mode: 0755]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/sim.fl [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi/sim/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/COMPILE_LIST [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/COPYING [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/KNOWN_BUGS [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/README [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/card-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/card.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/spi_boot.pdf [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/spi_boot_schematic.pdf [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/architecture.eps [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/architecture.fig [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/initialization.eps [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/initialization.fig [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.eps [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.fig [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/spi_boot.sxw [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/transfer.eps [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/doc/src/transfer.fig [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-e.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter.vhd [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sim/CVS/Repository [new file with mode: 0644]
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usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/Makefile [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sw/CVS/Entries [new file with mode: 0644]
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usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/spi_boot/sw/misc/bit_reverse.c [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/CVS/Root [new file with mode: 0644]
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usrp2/fpga/opencores/uart16550/bench/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/CVS/Root [new file with mode: 0644]
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usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/readme.txt [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/uart_int.v [new file with mode: 0755]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_device.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_device_utilities.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_log.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_test.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_utilities.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/uart_wb_utilities.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/vapi.log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/wb_mast.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/wb_master_model.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/verilog/wb_model_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/vhdl/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/CHANGES.txt [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/UART_spec.pdf [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/src/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/src/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/src/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/src/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/doc/src/UART_spec.doc [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/fv/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/fv/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/fv/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/fv/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/fv/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/bin/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/bin/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/bin/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/bin/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/bin/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/log/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/log/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/log/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/log/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/log/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/out/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/out/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/out/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/out/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/out/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/run/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/lint/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/timescale.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_fifo.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_receiver.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_regs.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_top.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_transmitter.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_wb.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/raminfr.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/timescale.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_debug_if.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_receiver.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_regs.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_rfifo.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_sync_flops.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_tfifo.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_top.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_transmitter.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/verilog/uart_wb.v [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/vhdl/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/log/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/out/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/run/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/src/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/nc.scr [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/sim.tcl [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_report.log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_signalscan [new file with mode: 0755]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim [new file with mode: 0755]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim.scr [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/CVS/Entries.Log [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/bin/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/bin/CVS/Entries [new file with mode: 0644]
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usrp2/fpga/opencores/uart16550/syn/bin/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/bin/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/log/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/log/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/log/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/log/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/log/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/out/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/out/CVS/Entries [new file with mode: 0644]
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usrp2/fpga/opencores/uart16550/syn/out/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/out/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/run/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/run/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/run/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/run/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/run/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/src/.keepme [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/src/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/src/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/src/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/syn/src/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/uart16550/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/CVS/Root [new file with mode: 0644]
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usrp2/fpga/opencores/wb_conbus/bench/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/CVS/Repository [new file with mode: 0644]
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usrp2/fpga/opencores/wb_conbus/bench/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/tests.v [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/wb_mast_model.v [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/wb_model_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/bench/verilog/wb_slv_model.v [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/CVS/Repository [new file with mode: 0644]
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usrp2/fpga/opencores/wb_conbus/rtl/verilog/CVS/Entries [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/verilog/CVS/Repository [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/verilog/CVS/Root [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/verilog/CVS/Template [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/verilog/wb_conbus_arb.v [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/verilog/wb_conbus_defines.v [new file with mode: 0644]
usrp2/fpga/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/HB.sav [new file with mode: 0644]
usrp2/fpga/sdr_lib/SMALL_HB.sav [new file with mode: 0644]
usrp2/fpga/sdr_lib/acc.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/add2.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/add2_and_round.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/add2_and_round_reg.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/add2_reg.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/cic_dec_shifter.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/cic_decim.v [new file with mode: 0755]
usrp2/fpga/sdr_lib/cic_int_shifter.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/cic_interp.v [new file with mode: 0755]
usrp2/fpga/sdr_lib/cic_strober.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/clip.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/clip_and_round.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/clip_and_round_reg.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/clip_reg.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/cordic.v [new file with mode: 0755]
usrp2/fpga/sdr_lib/cordic_stage.v [new file with mode: 0755]
usrp2/fpga/sdr_lib/ddc.v [new file with mode: 0755]
usrp2/fpga/sdr_lib/dsp_core_rx.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/dsp_core_tx.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/duc.v [new file with mode: 0755]
usrp2/fpga/sdr_lib/dummy_rx.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/gen_cordic_consts.py [new file with mode: 0755]
usrp2/fpga/sdr_lib/halfband_ideal.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/halfband_tb.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/acc.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/coeff_ram.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/coeff_rom.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/halfband_decim.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/halfband_interp.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/hbd_tb/HBD [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/hbd_tb/really_golden [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/hbd_tb/regression [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/hbd_tb/run_hbd [new file with mode: 0755]
usrp2/fpga/sdr_lib/hb/hbd_tb/test_hbd.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/mac.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/mult.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/ram16_2port.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/ram16_2sum.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb/ram32_2sum.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb_dec.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb_dec_tb.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb_interp.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb_interp_tb.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/hb_tb.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/input.dat [new file with mode: 0644]
usrp2/fpga/sdr_lib/output.dat [new file with mode: 0644]
usrp2/fpga/sdr_lib/round.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/round_reg.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/rssi.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/rx_control.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/rx_dcoffset.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/rx_dcoffset_tb.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/sign_extend.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/small_hb_dec.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/small_hb_dec_tb.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/small_hb_int.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/small_hb_int_tb.v [new file with mode: 0644]
usrp2/fpga/sdr_lib/tx_control.v [new file with mode: 0644]
usrp2/fpga/serdes/serdes.v [new file with mode: 0644]
usrp2/fpga/serdes/serdes_fc_rx.v [new file with mode: 0644]
usrp2/fpga/serdes/serdes_fc_tx.v [new file with mode: 0644]
usrp2/fpga/serdes/serdes_rx.v [new file with mode: 0644]
usrp2/fpga/serdes/serdes_tb.v [new file with mode: 0644]
usrp2/fpga/serdes/serdes_tx.v [new file with mode: 0644]
usrp2/fpga/testbench/BOOTSTRAP.sav [new file with mode: 0644]
usrp2/fpga/testbench/Makefile [new file with mode: 0644]
usrp2/fpga/testbench/PAUSE.sav [new file with mode: 0644]
usrp2/fpga/testbench/README [new file with mode: 0644]
usrp2/fpga/testbench/SERDES.sav [new file with mode: 0644]
usrp2/fpga/testbench/U2_SIM.sav [new file with mode: 0644]
usrp2/fpga/testbench/cmdfile [new file with mode: 0644]
usrp2/fpga/timing/time_receiver.v [new file with mode: 0644]
usrp2/fpga/timing/time_sender.v [new file with mode: 0644]
usrp2/fpga/timing/time_sync.v [new file with mode: 0644]
usrp2/fpga/timing/time_transfer_tb.v [new file with mode: 0644]
usrp2/fpga/timing/timer.v [new file with mode: 0644]
usrp2/fpga/top/eth_test/eth_sim_top.v [new file with mode: 0644]
usrp2/fpga/top/eth_test/eth_tb.v [new file with mode: 0644]
usrp2/fpga/top/single_u2_sim/single_u2_sim.v [new file with mode: 0644]
usrp2/fpga/top/tcl/ise_helper.tcl [new file with mode: 0644]
usrp2/fpga/top/u2_core/u2_core.v [new file with mode: 0755]
usrp2/fpga/top/u2_fpga/Makefile [new file with mode: 0644]
usrp2/fpga/top/u2_fpga/u2_fpga.ise [new file with mode: 0644]
usrp2/fpga/top/u2_fpga/u2_fpga.ucf [new file with mode: 0755]
usrp2/fpga/top/u2_fpga/u2_fpga_top.prj [new file with mode: 0644]
usrp2/fpga/top/u2_fpga/u2_fpga_top.v [new file with mode: 0644]
usrp2/fpga/top/u2_rev2/Makefile [new file with mode: 0644]
usrp2/fpga/top/u2_rev2/u2_rev2.ucf [new file with mode: 0644]
usrp2/fpga/top/u2_rev2/u2_rev2.v [new file with mode: 0644]
usrp2/fpga/top/u2_rev3/Makefile [new file with mode: 0644]
usrp2/fpga/top/u2_rev3/u2_rev3.ucf [new file with mode: 0644]
usrp2/fpga/top/u2_rev3/u2_rev3.v [new file with mode: 0644]
usrp2/fpga/top/u2plus/u2plus.ucf [new file with mode: 0755]
usrp2/fpga/top/u2plus/u2plus.v [new file with mode: 0644]
usrp2/host/Makefile.am [new file with mode: 0644]
usrp2/host/apps/Makefile.am [new file with mode: 0644]
usrp2/host/apps/find_usrps.cc [new file with mode: 0644]
usrp2/host/apps/gen_2tone.py [new file with mode: 0755]
usrp2/host/apps/gen_const.cc [new file with mode: 0644]
usrp2/host/apps/gen_sine.py [new file with mode: 0755]
usrp2/host/apps/rx_samples.cc [new file with mode: 0644]
usrp2/host/apps/rx_streaming_samples.cc [new file with mode: 0644]
usrp2/host/apps/stdin_int32_fft.py [new file with mode: 0755]
usrp2/host/apps/streaming_fft.py [new file with mode: 0755]
usrp2/host/apps/test.sh [new file with mode: 0755]
usrp2/host/apps/tx_samples.cc [new file with mode: 0644]
usrp2/host/apps/usrp2_burn_mac_addr.cc [new file with mode: 0644]
usrp2/host/include/Makefile.am [new file with mode: 0644]
usrp2/host/include/usrp2/Makefile.am [new file with mode: 0644]
usrp2/host/include/usrp2/copiers.h [new file with mode: 0644]
usrp2/host/include/usrp2/copy_handler.h [new file with mode: 0644]
usrp2/host/include/usrp2/data_handler.h [new file with mode: 0644]
usrp2/host/include/usrp2/metadata.h [new file with mode: 0644]
usrp2/host/include/usrp2/rx_nop_handler.h [new file with mode: 0644]
usrp2/host/include/usrp2/rx_sample_handler.h [new file with mode: 0644]
usrp2/host/include/usrp2/strtod_si.h [new file with mode: 0644]
usrp2/host/include/usrp2/tune_result.h [new file with mode: 0644]
usrp2/host/include/usrp2/usrp2.h [new file with mode: 0644]
usrp2/host/include/usrp2/usrp2_cdefs.h [new file with mode: 0644]
usrp2/host/lib/Makefile.am [new file with mode: 0644]
usrp2/host/lib/control.cc [new file with mode: 0644]
usrp2/host/lib/control.h [new file with mode: 0644]
usrp2/host/lib/copiers.cc [new file with mode: 0644]
usrp2/host/lib/copy_handler.cc [new file with mode: 0644]
usrp2/host/lib/data_handler.cc [new file with mode: 0644]
usrp2/host/lib/eth_buffer.cc [new file with mode: 0644]
usrp2/host/lib/eth_buffer.h [new file with mode: 0644]
usrp2/host/lib/eth_common.h [new file with mode: 0644]
usrp2/host/lib/ethernet.cc [new file with mode: 0644]
usrp2/host/lib/ethernet.h [new file with mode: 0644]
usrp2/host/lib/find.cc [new file with mode: 0644]
usrp2/host/lib/open_usrp2_socket.cc [new file with mode: 0644]
usrp2/host/lib/open_usrp2_socket.h [new file with mode: 0644]
usrp2/host/lib/pktfilter.cc [new file with mode: 0644]
usrp2/host/lib/pktfilter.h [new file with mode: 0644]
usrp2/host/lib/ring.cc [new file with mode: 0644]
usrp2/host/lib/ring.h [new file with mode: 0644]
usrp2/host/lib/rx_nop_handler.cc [new file with mode: 0644]
usrp2/host/lib/rx_sample_handler.cc [new file with mode: 0644]
usrp2/host/lib/strtod_si.c [new file with mode: 0644]
usrp2/host/lib/usrp2.cc [new file with mode: 0644]
usrp2/host/lib/usrp2_bytesex.h [new file with mode: 0644]
usrp2/host/lib/usrp2_impl.cc [new file with mode: 0644]
usrp2/host/lib/usrp2_impl.h [new file with mode: 0644]
usrp2/host/lib/usrp2_socket_opener.cc [new file with mode: 0644]
usrp2/host/lib/usrp2_thread.cc [new file with mode: 0644]
usrp2/host/lib/usrp2_thread.h [new file with mode: 0644]
usrp2/host/usrp2.pc.in [new file with mode: 0644]