X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=usrp2%2Ffpga%2Fcoregen%2Ffifo_xlnx_512x36_2clk.veo;fp=usrp2%2Ffpga%2Fcoregen%2Ffifo_xlnx_512x36_2clk.veo;h=0000000000000000000000000000000000000000;hb=a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3;hp=6699ee73b9a91985477d807f072175a79ef60212;hpb=db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f;p=debian%2Fgnuradio

diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo
deleted file mode 100644
index 6699ee73..00000000
--- a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used             *
-*     solely for design, simulation, implementation and creation of            *
-*     design files limited to Xilinx devices or technologies. Use              *
-*     with non-Xilinx devices or technologies is expressly prohibited          *
-*     and immediately terminates your license.                                 *
-*                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
-*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
-*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
-*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
-*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
-*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
-*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
-*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
-*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
-*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
-*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
-*     FOR A PARTICULAR PURPOSE.                                                *
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-*     Xilinx products are not intended for use in life support                 *
-*     appliances, devices, or systems. Use in such applications are            *
-*     expressly prohibited.                                                    *
-*                                                                              *
-*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
-*     All rights reserved.                                                     *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_512x36_2clk YourInstanceName (
-	.din(din), // Bus [35 : 0] 
-	.rd_clk(rd_clk),
-	.rd_en(rd_en),
-	.rst(rst),
-	.wr_clk(wr_clk),
-	.wr_en(wr_en),
-	.dout(dout), // Bus [35 : 0] 
-	.empty(empty),
-	.full(full),
-	.rd_data_count(rd_data_count), // Bus [9 : 0] 
-	.wr_data_count(wr_data_count)); // Bus [9 : 0] 
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating
-// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-