X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32w108xx.cfg;h=e6a62e8df28f0af4f3e6cb377e54df51dc1ae25b;hb=9ffeedb5794e5ebe7b3a7d7fd63fde4d7124c0dd;hp=ca4f15322a7fec0c12627cc608f4a6f7fe258670;hpb=d70f86e7da1df0b6e8c13adbf748525fce4ae0e0;p=fw%2Fopenocd

diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index ca4f15322..e6a62e8df 100644
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -1,10 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Target configuration for the ST STM32W108xx chips
 #
-# Processor: ARM Cortex M3
+# Processor: ARM Cortex-M3
 # Date:      2013-06-09
 # Author:    Giuseppe Barba <giuseppe.barba@gmail.com>
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] == 0 } {
    set _CHIPNAME stm32w108
 } else {
@@ -22,32 +29,34 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-   set _CPUTAPID 0x3ba00477
+   if { [using_jtag] } {
+      set _CPUTAPID 0x3ba00477
+   } {
+      set _CPUTAPID 0x1ba01477
+   }
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-if { [info exists BSTAPID] } {
+if {[using_jtag]} {
+ if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
-   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id 0x269a862b
-} else {
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
+ } else {
    set _BSTAPID_1 0x169a862b
    set _BSTAPID_2 0x269a862b
    jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
 		-expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
+ }
 }
-
 #
 # Set Target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 
@@ -57,5 +66,8 @@ set _FLASHNAME $_CHIPNAME.flash
 # 64k (0x10000) of flash
 flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
 
-cortex_m reset_config sysresetreq
+reset_config srst_nogate
 
+if {![using_hla]} {
+   cortex_m reset_config sysresetreq
+}