X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32mp15x.cfg;h=639fbabe06e9dc23a0b56cf70a174024e513724c;hb=4ddca7dd7186a908397570a25f7ad7454bab3a20;hp=a11f6665ee127b6e392246ef116b6ff4adfb53ed;hpb=7a94d0a19fbe1762d1be26d35958ca3edb74b41e;p=fw%2Fopenocd

diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index a11f6665e..639fbabe0 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -59,10 +59,13 @@ $_CHIPNAME.cpu1 cortex_a maskisr on
 $_CHIPNAME.cpu0 cortex_a dacrfixup on
 $_CHIPNAME.cpu1 cortex_a dacrfixup on
 
-cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE0094000
-cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D8000
-cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
-cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
+cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
+cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
+cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
+cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
 
 # interface does not work while srst is asserted
 # this is target specific, valid for every board
@@ -94,6 +97,9 @@ axi_secure
 proc dbgmcu_enable_debug {} {
 	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+	# freeze watchdog 1 and 2 on cores halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
 proc toggle_cpu0_dbg_claim0 {} {
@@ -104,18 +110,22 @@ proc toggle_cpu0_dbg_claim0 {} {
 
 proc detect_cpu1 {} {
 	$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
-	set dual_core [expr $cpu1_prsr(0) & 1]
+	set dual_core [expr {$cpu1_prsr(0) & 1}]
 	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
 }
 
+proc rcc_enable_traceclk {} {
+	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
+}
+
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
-$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug}
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
 $_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
-$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
+$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
 $_CHIPNAME.ap1  configure -event examine-start       {dap init}
 $_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
 $_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
-$_CHIPNAME.ap2  configure -event examine-end         {$::_CHIPNAME.cm4 arp_examine}
+$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}