X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32l5x.cfg;h=c43b699d25970f266c042a27429f5300bd57140e;hb=f583f338b086ed3a1cd471e1fd8ef99589a64dae;hp=92083b9e0540484a4cf89c080f3500b5ca46c19b;hpb=b8fd9aecb12a5d930cf3e3e09cede4cd6787e847;p=fw%2Fopenocd

diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32l5x.cfg
index 92083b9e0..c43b699d2 100644
--- a/tcl/target/stm32l5x.cfg
+++ b/tcl/target/stm32l5x.cfg
@@ -1,10 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # script for stm32l5x family
+# stm32l5x devices support both JTAG and SWD transports.
 
-#
-# stm32l5 devices support both JTAG and SWD transports.
-#
 source [find target/swj-dp.tcl]
 source [find mem_helper.tcl]
 
@@ -14,118 +12,37 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME stm32l5x
 }
 
-set _ENDIAN little
+source [find target/stm32x5x_common.cfg]
 
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
-	set _WORKAREASIZE $WORKAREASIZE
-} else {
-	set _WORKAREASIZE 0x10000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	if { [using_jtag] } {
-		# See STM Document RM0438
-		# RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
-		# Corresponds to Cortex®-M33 JTAG debug port ID code
-		set _CPUTAPID 0x0ba04477
-	} {
-		# SWD IDCODE (single drop, arm)
-		set _CPUTAPID 0x0be12477
-	}
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-if {[using_jtag]} {
-	jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-# use non-secure RAM by default
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# declare non-secure flash
-flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp      stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
-
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
-# the safe side.
-#
-# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter speed 500
-
-adapter srst delay 100
-if {[using_jtag]} {
-	jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
-	# if srst is not fitted use SYSRESETREQ to
-	# perform a soft reset
-	cortex_m reset_config sysresetreq
-}
-
-proc clock_config_110_mhz {} {
+proc stm32l5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
 	# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
 	# RCC_APB1ENR1 = PWREN
-	mww 0x40021058 0x10000000
+	mww [expr {0x40021058 + $offset}] 0x10000000
 	# delay for register clock enable (read back reg)
-	mrw 0x40021058
+	mrw [expr {0x40021058 + $offset}]
 	# PWR_CR1 : VOS Range 0
-	mww 0x40007000 0
+	mww [expr {0x40007000 + $offset}] 0
 	# while (PWR_SR2 & VOSF)
-	while {([mrw 0x40007014] & 0x0400)} {}
+	while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
 	# FLASH_ACR : 5 WS for 110 MHz HCLK
 	mww 0x40022000 0x00000005
 	# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
 	# fVCO = 4 x 55 /1 = 220
 	# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
-	mww 0x4002100C 0x01003711
+	mww [expr {0x4002100C + $offset}] 0x01003711
 	# RCC_CR |= PLLON
-	mmw 0x40021000 0x01000000 0
+	mmw [expr {0x40021000 + $offset}] 0x01000000 0
 	# while !(RCC_CR & PLLRDY)
-	while {!([mrw 0x40021000] & 0x02000000)} {}
+	while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
 	# RCC_CFGR |= SW_PLL
-	mmw 0x40021008 0x00000003 0
+	mmw [expr {0x40021008 + $offset}] 0x00000003 0
 	# while ((RCC_CFGR & SWS) != PLL)
-	while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
+	while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
 }
 
 $_TARGETNAME configure -event reset-init {
-	clock_config_110_mhz
+	stm32l5x_clock_config
 	# Boost JTAG frequency
 	adapter speed 4000
 }
-
-$_TARGETNAME configure -event reset-start {
-	# Reset clock is MSI (4 MHz)
-	adapter speed 480
-}
-
-$_TARGETNAME configure -event examine-end {
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
-	mmw 0xE0044004 0x00000006 0
-
-	# Stop watchdog counters during halt
-	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
-	mmw 0xE0044008 0x00001800 0
-}
-
-$_TARGETNAME configure -event trace-config {
-	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
-	# assignment
-	mmw 0xE0044004 0x00000020 0
-}