X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32l0.cfg;h=b4bdb18a4d5c624e8900907b3814cd7a758cf557;hb=e6505b04892ccacf75603c3d173616f5d92809e7;hp=45b3c364cff98a49191c128f05a28042b867e221;hpb=1663a17d9d5f5988a8d129a6da36ebcf728d79a2;p=fw%2Fopenocd

diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index 45b3c364c..b4bdb18a4 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -1,9 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # M0+ devices only have SW-DP, but swj-dp code works, just don't
 # set any jtag related features
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -14,18 +17,18 @@ if { [info exists CHIPNAME] } {
 set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
-# By default use 8kB (max ram on smallest part)
+# By default use 2kB (max ram on smallest part)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x2000
+   set _WORKAREASIZE 0x800
 }
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 if { [info exists CPUTAPID] } {
     set _CPUTAPID $CPUTAPID
@@ -36,9 +39,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -46,6 +50,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
@@ -57,13 +63,16 @@ proc stm32l0_enable_HSI16 {} {
 	echo "STM32L0: Enabling HSI16"
 
 	# Set HSI16ON in RCC_CR (leave MSI enabled)
-	mww 0x40021000 0x00000101
+    mmw 0x40021000 0x00000101 0
 
 	# Set HSI16 as SYSCLK (RCC_CFGR)
-	mww 0x4002100c 0x00000001
+	mmw 0x4002100c 0x00000001 0
+
+	# Wait until System clock switches to HSI16
+	while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
 
 	# Increase speed
-	adapter_khz 2500
+	adapter speed 2500
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -71,5 +80,14 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 300
+	adapter speed 300
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0x40015804 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
 }