X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32h7x.cfg;h=5aae93861909293c1ab4f67d8a86c66c24691506;hb=e6505b04892ccacf75603c3d173616f5d92809e7;hp=1d116542a7ddc45a6f64d417be277ed6eaac7a46;hpb=678fb4f60b685ed79d35272bc515891fa53b527e;p=fw%2Fopenocd

diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 1d116542a..5aae93861 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32h7x family
 
 #
@@ -70,13 +72,15 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 if {![using_hla]} {
 	# STM32H7 provides an APB-AP at access port 2, which allows the access to
 	# the debug and trace features on the system APB System Debug Bus (APB-D).
 	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+	swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
+	tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
 }
 
 target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
@@ -104,10 +108,27 @@ if {[set $_CHIPNAME.DUAL_CORE]} {
 # Make sure that cpu0 is selected
 targets $_CHIPNAME.cpu0
 
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
+   }
+}
+
 # Clock after reset is HSI at 64 MHz, no need of PLL
-adapter_khz 1800
+adapter speed 1800
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -123,7 +144,7 @@ if {[using_jtag]} {
 # usage does not work with HLA, so is not done by default. That change could be
 # made in a local configuration file if connect_assert_srst mode is needed for
 # a specific application and a non-HLA adapter is in use.
-reset_config srst_only srst_nogate
+reset_config srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
@@ -149,8 +170,10 @@ $_CHIPNAME.cpu0 configure -event examine-end {
 	stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 
 	# Enable debug during low power modes (uses more power)
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
-	stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
+	stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
+	stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
 
 	# Stop watchdog counters during halt
 	# DBGMCU_APB3FZ1 |= WWDG1
@@ -159,24 +182,40 @@ $_CHIPNAME.cpu0 configure -event examine-end {
 	stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
 	# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
 	stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
-}
 
-$_CHIPNAME.cpu0 configure -event trace-config {
-	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
-	# assignment
+	# Enable clock for tracing
+	# DBGMCU_CR |= TRACECLKEN
 	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
+
+	# RM0399 (id 0x450) M7+M4 with SWO Funnel
+	# RM0433 (id 0x450) M7 with SWO Funnel
+	# RM0455 (id 0x480) M7 without SWO Funnel
+	# RM0468 (id 0x483) M7 without SWO Funnel
+	# Enable CM7 and CM4 slave ports in SWO trace Funnel
+	# Works ok also on devices single core and without SWO funnel
+	# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
+	# SWTF_CTRL |= ENS0 | ENS1
+	stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
 }
 
 $_CHIPNAME.cpu0 configure -event reset-init {
 	# Clock after reset is HSI at 64 MHz, no need of PLL
-	adapter_khz 4000
+	adapter speed 4000
+}
+
+# get _CHIPNAME from current target
+proc stm32h7x_get_chipname {} {
+	set t [target current]
+	set sep [string last "." $t]
+	if {$sep == -1} {
+		return $t
+	}
+	return [string range $t 0 [expr {$sep - 1}]]
 }
 
 if {[set $_CHIPNAME.DUAL_CORE]} {
 	$_CHIPNAME.cpu1 configure -event examine-end {
-		# get _CHIPNAME from the current target
-		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+		set _CHIPNAME [stm32h7x_get_chipname]
 		global $_CHIPNAME.USE_CTI
 
 		# Stop watchdog counters during halt
@@ -195,15 +234,13 @@ if {[set $_CHIPNAME.DUAL_CORE]} {
 
 # like mrw, but with target selection
 proc stm32h7x_mrw {used_target reg} {
-	set value ""
-	$used_target mem2array value 32 $reg 1
-	return $value(0)
+	return [$used_target read_memory $reg 32 1]
 }
 
 # like mmw, but with target selection
 proc stm32h7x_mmw {used_target reg setbits clearbits} {
 	set old [stm32h7x_mrw $used_target $reg]
-	set new [expr ($old & ~$clearbits) | $setbits]
+	set new [expr {($old & ~$clearbits) | $setbits}]
 	$used_target mww $reg $new
 }
 
@@ -212,13 +249,12 @@ proc stm32h7x_mmw {used_target reg setbits clearbits} {
 proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
 	# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
 	if {![using_hla]} {
-		# get _CHIPNAME from the current target
-		set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
+		set _CHIPNAME [stm32h7x_get_chipname]
 		set used_target $_CHIPNAME.ap2
-		set reg_addr [expr 0xE00E1000 + $reg_offset]
+		set reg_addr [expr {0xE00E1000 + $reg_offset}]
 	} {
 		set used_target [target current]
-		set reg_addr [expr 0x5C001000 + $reg_offset]
+		set reg_addr [expr {0x5C001000 + $reg_offset}]
 	}
 
 	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
@@ -226,8 +262,8 @@ proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
 
 if {[set $_CHIPNAME.USE_CTI]} {
 	# create CTI instances for both cores
-	cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
-	cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
+	cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
+	cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
 
 	$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
 	$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
@@ -236,8 +272,7 @@ if {[set $_CHIPNAME.USE_CTI]} {
 	$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
 
 	proc stm32h7x_cti_start {} {
-		# get _CHIPNAME from the current target
-		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+		set _CHIPNAME [stm32h7x_get_chipname]
 
 		# Configure Cores' CTIs to halt each other
 		# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
@@ -252,8 +287,7 @@ if {[set $_CHIPNAME.USE_CTI]} {
 	}
 
 	proc stm32h7x_cti_stop {} {
-		# get _CHIPNAME from the current target
-		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+		set _CHIPNAME [stm32h7x_get_chipname]
 
 		$_CHIPNAME.cti0 enable off
 		$_CHIPNAME.cti1 enable off
@@ -265,8 +299,7 @@ if {[set $_CHIPNAME.USE_CTI]} {
 	}
 
 	proc stm32h7x_cti_prepare_restart {cti} {
-		# get _CHIPNAME from the current target
-		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+		set _CHIPNAME [stm32h7x_get_chipname]
 
 		# Acknowlodge EDBGRQ at TRIGOUT0
 		$_CHIPNAME.$cti write INACK 0x01