X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f7x.cfg;h=3782b9a9cce5dcc4fb778b5cc52a9bccd7291037;hb=ca52cfb2b34d684d10e9c91eeb2c6a66a1448b9f;hp=db1794c195fdc5037f697d30df961339e4b6f17f;hpb=b27173d56329ac1c7a7b399110b004e98a9cd8d7;p=fw%2Fopenocd

diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index db1794c19..3782b9a9c 100644
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32f7x family
 
 #
@@ -12,7 +14,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f7x
 }
 
-   set _ENDIAN little
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 128kB
@@ -64,6 +66,12 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
 #     the Flash via ITCM alias as virtual
 flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
 
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
 adapter speed 2000
 
@@ -76,7 +84,7 @@ if {[using_jtag]} {
 #
 # This target is compatible with connect_assert_srst, which may be set in a
 # board file.
-reset_config srst_only srst_nogate
+reset_config srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
@@ -101,13 +109,20 @@ $_TARGETNAME configure -event examine-end {
 	mmw 0xE0042008 0x00001800 0
 }
 
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
 	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 	# change this value accordingly to configure trace pins
 	# assignment
 	mmw 0xE0042004 0x00000020 0
 }
 
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
+
 $_TARGETNAME configure -event reset-init {
 	# If the HSE was previously enabled and the external clock source
 	# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
@@ -170,4 +185,3 @@ $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
 	adapter speed 2000
 }
-