X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f7x.cfg;h=3782b9a9cce5dcc4fb778b5cc52a9bccd7291037;hb=0dd969d83badb6793519ee99dd8ab8579d5f59df;hp=927a3e8d0595793efe57e6431c1eef92eeb24c17;hpb=a3dc54d2d32919588cd7b8d22552f016cf603a49;p=fw%2Fopenocd

diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
old mode 100755
new mode 100644
index 927a3e8d0..3782b9a9c
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32f7x family
 
 #
@@ -12,7 +14,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f7x
 }
 
-   set _ENDIAN little
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 128kB
@@ -51,14 +53,29 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
 
-# Configuring the Flash via ITCM alias as virtual
-set _FLASH_ITCM_VMA itcm-flash.alias
-flash bank $_FLASH_ITCM_VMA virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
+# On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and
+# also address 0x00200000 via the ITCM. The former mapping is read-write in
+# hardware, while the latter is read-only. By presenting an alias, we
+# accomplish two things:
+# (1) We allow writing at 0x00200000 (because the alias acts identically to the
+#     original bank), which allows code intended to run from that address to
+#     also be linked for loading at that address, simplifying linking.
+# (2) We allow the proper memory map to be delivered to GDB, which will cause
+#     it to use hardware breakpoints at the 0x00200000 mapping (correctly
+#     identifying it as Flash), which it would otherwise not do. Configuring
+#     the Flash via ITCM alias as virtual
+flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -67,7 +84,7 @@ if {[using_jtag]} {
 #
 # This target is compatible with connect_assert_srst, which may be set in a
 # board file.
-reset_config srst_only srst_nogate
+reset_config srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
@@ -92,13 +109,20 @@ $_TARGETNAME configure -event examine-end {
 	mmw 0xE0042008 0x00001800 0
 }
 
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
 	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 	# change this value accordingly to configure trace pins
 	# assignment
 	mmw 0xE0042004 0x00000020 0
 }
 
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
+
 $_TARGETNAME configure -event reset-init {
 	# If the HSE was previously enabled and the external clock source
 	# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
@@ -153,12 +177,11 @@ $_TARGETNAME configure -event reset-init {
 	if {[using_jtag]} {
 		[[target current] cget -dap] memaccess 16
 	} {
-		adapter_khz 8000
+		adapter speed 8000
 	}
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
-	adapter_khz 2000
+	adapter speed 2000
 }
-