X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fpxa255.cfg;h=73518bf7e4af5b4bb58522fa85c48034214042e7;hb=2c5f263bcd61592b6575ed92672d14143bdb9aad;hp=4b222de081e56d9b21b2f7354b388972f86633d8;hpb=5d08bcb715599466dc88d1cdf5b599a7bba1be6a;p=fw%2Fopenocd

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 4b222de08..73518bf7e 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active