X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fpxa255.cfg;h=73518bf7e4af5b4bb58522fa85c48034214042e7;hb=06990a1a9e9ace74fc6e79a78b5405bb63cee6b0;hp=386242597cefd9b3a8ae3d59a455c67170458a62;hpb=ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3;p=fw%2Fopenocd

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 386242597..73518bf7e 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active
@@ -38,11 +38,11 @@ reset_config trst_and_srst separate srst_nogate
 # reset processing that works with PXA
 proc init_reset {mode} {
 	# assert both resets; equivalent to power-on reset
-	jtag_reset 1 1
+	adapter assert trst assert srst
 
 	# drop TRST after at least 32 cycles
 	sleep 1
-	jtag_reset 0 1
+	adapter deassert trst assert srst
 
 	# minimum 32 TCK cycles to wake up the controller
 	runtest 50
@@ -51,7 +51,7 @@ proc init_reset {mode} {
 	jtag arp_init
 
 	# ... and take it out of reset
-	jtag_reset 0 0
+	adapter deassert trst deassert srst
 }
 
 proc jtag_init {} {