X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fpxa255.cfg;h=5b745f8599f752300bba9b1e19902e996ce26079;hb=2e1eaaae35e506efe6190817876b1078885a83d7;hp=7137621a43c87de0ed2daf7ac756286e65d1d26f;hpb=20a3b14828c5015647fa438e0cbee84685bcdf5f;p=fw%2Fopenocd

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 7137621a4..5b745f859 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,12 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-jtag_khz 300
-$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
 
 # reset processing that works with PXA
 proc init_reset {mode} {