X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fomap4430.cfg;h=fc3db5d0ccc69214fc95939b5f0c01d0d04df95d;hb=c5c4ed82abcef3e9d5494d850d4f3acded320e55;hp=13ed80c39bcffaf79432bb9b9c2dac9bdbf2b80e;hpb=6c5e1781a102424353bf237386e7443b2ce3e4d3;p=fw%2Fopenocd

diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index 13ed80c39..fc3db5d0c 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -82,7 +82,20 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
 # second core.
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -coreid 0
+
+# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
+# 0x80000000 is cpu0 coresight region
+#
+#
+# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
+# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
+
+set _coreid 0
+set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
+echo "Using dbgbase = [format 0x%x $_dbgbase]"
+ 
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+  -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000