X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fnrf51.cfg;h=d51a50e23152bdb352136fa13a87b19482c220a2;hb=2b17a128841c9431f17aaad844f416eccd24f63f;hp=280dd4ff365609d56cddc62a82d565bf817f1e8f;hpb=0c8ec7c826c60391034fe5f0ea90f8538ac94b38;p=fw%2Fopenocd

diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 280dd4ff3..d51a50e23 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -31,9 +31,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -49,7 +50,7 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
 #  The chip should start up from internal 16Mhz RC, so setting adapter
 #  clock to 1Mhz should be OK
 #
-adapter_khz 1000
+adapter speed 1000
 
 proc enable_all_ram {} {
 	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks