X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc8nxx.cfg;h=859e99b6a3ba2298176072e301d1711b335de466;hb=ca52cfb2b34d684d10e9c91eeb2c6a66a1448b9f;hp=1bc77b20d1af1860df0f7cb4045bc61ce5dec928;hpb=38ac08c1c25adf42cf20e48e10e6ddeab6a12d71;p=fw%2Fopenocd

diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg
index 1bc77b20d..859e99b6a 100644
--- a/tcl/target/lpc8nxx.cfg
+++ b/tcl/target/lpc8nxx.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
 # Copyright (C) 2018 by Jean-Christian de Rivaz
 # Based on NXP proposal https://community.nxp.com/message/1011149
@@ -56,7 +58,7 @@ proc set_sysclk_500khz {} {
 	echo "Notice: sysclock set to 500kHz."
 }
 
-# Do not remap the ARM interrupt vectors to anything but the beginning ot the flash.
+# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
 # Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
 # Bit Symbol  Value   Description
 # 0   map         -   interrupt vector remap. 0 after boot.