X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc4350.cfg;h=453306aeebc7108c48f592a44b08e40e61186f6b;hb=ace028262ba0bda0e921afb11e6eb7d87708d889;hp=fae54f7763ebe38b23f519dc831754e451fa3a21;hpb=c7384117c66e8f18896ca09ab8095d6da16bb1e5;p=fw%2Fopenocd diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg index fae54f776..453306aee 100644 --- a/tcl/target/lpc4350.cfg +++ b/tcl/target/lpc4350.cfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/swj-dp.tcl] -adapter_khz 500 +adapter speed 500 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -43,13 +45,24 @@ if { [info exists M0_JTAG_TAPID] } { swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M4_TAPID -target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 +dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4 +target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap if { [using_jtag] } { swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M0_JTAG_TAPID - target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 + dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0 + target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap +} + +# LPC4350 has 96+32 KB SRAM +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x20000 } +$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 if {![using_hla]} { # on this CPU we should use VECTRESET to perform a soft reset and