X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc2478.cfg;h=1d2058b0440afdcd12e51a05093fbcb7f32b50e6;hb=108028112fdf285cd74eaf50d6a353a09039bb7f;hp=84675705b959a254624ca9532e96f7f573fe5889;hpb=dbbc9c41f7db210b0a4e226540a28e0a8a5019bf;p=fw%2Fopenocd

diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 84675705b..1d2058b04 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -1,35 +1,49 @@
-# Testing feeedback wanted!
-set _CHIPNAME lpc2478
-set _ENDIAN little
-set _CPUTAPID 0x4f1f0f0f
-
-# Use RCLK. If RCLK is not available fall back to 500kHz. 
-# 
-# Depending on cabling you might be able to eek this up to 2000kHz.
-jtag_rclk 500
+# NXP LPC2478 ARM7TDMI-S with 512kB Flash and 64kB Local On-Chip SRAM (98kB total), clocked with 4MHz internal RC oscillator
 
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc2478
+}
 
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4f1f0f0f
+}
 
+#delays on reset lines
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+# LPC2000 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
 
+# LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 0
 
 $_TARGETNAME configure -event reset-init {
 	# Force target into ARM state
-	soft_reset_halt
-	# FIX!!!! should we remap the range below??? Is this applicable to
-	# Copied from LPC2148.
-	#do not remap 0x0000-0x0020 to anything but the flash
+	armv4_5 core_state arm
+	# Do not remap 0x0000-0x0020 to anything but the Flash
 	mwb 0xE01FC040 0x01
 }
 
-
+# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
+# After reset the chip uses its internal 4MHz RC oscillator.
+# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
 flash bank lpc2000 0x0 0x7D000 0 0 0 lpc2000_v2 12000 calc_checksum
+
+# Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 = 666kHz, so use 500.
+jtag_rclk 500