X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc1768.cfg;h=d1734ddb11c854c0c0c9145e1cf24f175fb4c442;hb=c25ffd013ecc35f08e9e7e28cccf9318d53072bc;hp=68b33c4bb55ec15c360f719d61f1ede1e9fe9bb8;hpb=e3773e3e3d1f1ee0dbb0b69e8babe8419784d1c1;p=fw%2Fopenocd

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 68b33c4bb..d1734ddb1 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -5,9 +5,9 @@
 source [find target/swj-dp.tcl]
 
 if { [info exists CHIPNAME] } {
-	set  _CHIPNAME $CHIPNAME
+	set _CHIPNAME $CHIPNAME
 } else {
-	set  _CHIPNAME lpc1768
+	set _CHIPNAME lpc1768
 }
 
 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
@@ -17,12 +17,12 @@ if { [info exists CHIPNAME] } {
 # (The ROM code doing those updates cares about core clock speed...)
 #
 # CCLK is the core clock frequency in KHz
-if { [info exists CCLK ] } {
+if { [info exists CCLK] } {
 	set _CCLK $CCLK
 } else {
 	set _CCLK 4000
 }
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
 	set _CPUTAPID 0x4ba00477
@@ -32,9 +32,6 @@ if { [info exists CPUTAPID ] } {
 adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
-# LPC2000 & LPC1700 -> SRST causes TRST
-reset_config srst_pulls_trst
-
 #jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
@@ -55,7 +52,7 @@ flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-jtag_khz 10
+adapter_khz 10
 
 $_TARGETNAME configure -event reset-init {
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select