X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fimx8m.cfg;h=69380903c31c8a8de9644096c9c9274c5d7677eb;hb=e6505b04892ccacf75603c3d173616f5d92809e7;hp=5d7acbed10287aedc950d8417619b330f1960845;hpb=d496da2c20e579f0f8af09928049bfb04d328190;p=fw%2Fopenocd

diff --git a/tcl/target/imx8m.cfg b/tcl/target/imx8m.cfg
index 5d7acbed1..69380903c 100644
--- a/tcl/target/imx8m.cfg
+++ b/tcl/target/imx8m.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # configuration file for NXP i.MX8M family of SoCs
 #
@@ -35,16 +37,17 @@ set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
 for { set _core 0 } { $_core < $_cores } { incr _core } {
 
     cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
-        -ctibase [lindex $CTIBASE $_core]
+        -baseaddr [lindex $CTIBASE $_core]
 
     set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
-        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
 
     if { $_core != 0 } {
         # non-boot core examination may fail
         set _command "$_command -defer-examine"
         set _smp_command "$_smp_command $_TARGETNAME.$_core"
     } else {
+        set _command "$_command -rtos hwthread"
         set _smp_command "target smp $_TARGETNAME.$_core"
     }
 
@@ -52,7 +55,13 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
 }
 
 eval $_smp_command
-targets $_TARGETNAME.0
 
 # declare the auxiliary Cortex-M4 core on AP #4
-target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4
+target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
+               -defer-examine
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
+targets $_TARGETNAME.0