X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fimx6.cfg;h=29453346a45b0f509ee703e67dc5e6166259518a;hb=c280c9835705a7d104996569068826a73b665010;hp=e2ef7ae4ee3e7160186dc2d9d01e83453c7869b7;hpb=3b291a369c4e0804619be7c9bf0a68b5f9d8e7d6;p=fw%2Fopenocd

diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index e2ef7ae4e..29453346a 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -1,4 +1,10 @@
-# Freescale i.MX6 series single/dual/quad core processor
+#
+# Freescale i.MX6 series
+#
+# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
+#
+# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
+#
 
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
@@ -20,19 +26,34 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
 
 # System JTAG Controller
+
+# List supported SJC TAPIDs from imx reference manuals:
+set _SJC_TAPID_6Q   0x0191c01d
+set _SJC_TAPID_6D   0x0191e01d
+set _SJC_TAPID_6QP  0x3191c01d
+set _SJC_TAPID_6DP  0x3191d01d
+set _SJC_TAPID_6DL  0x0891a01d
+set _SJC_TAPID_6S   0x0891b01d
+set _SJC_TAPID_6SL  0x0891f01d
+set _SJC_TAPID_6SLL 0x088c201d
+
+# Allow external override of the first SJC TAPID
 if { [info exists SJC_TAPID] } {
-        set _SJC_TAPID $SJC_TAPID
+    set _SJC_TAPID $SJC_TAPID
 } else {
-        set _SJC_TAPID 0x0191c01d
+    set _SJC_TAPID $_SJC_TAPID_6Q
 }
-set _SJC_TAPID2 0x2191c01d
-set _SJC_TAPID3 0x2191e01d
-set _SJC_TAPID4 0x1191c01d
 
 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
         -ignore-version \
-        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-        -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
+        -expected-id $_SJC_TAPID \
+        -expected-id $_SJC_TAPID_6QP \
+        -expected-id $_SJC_TAPID_6DP \
+        -expected-id $_SJC_TAPID_6D \
+        -expected-id $_SJC_TAPID_6DL \
+        -expected-id $_SJC_TAPID_6S \
+        -expected-id $_SJC_TAPID_6SL \
+        -expected-id $_SJC_TAPID_6SLL
 
 # GDB target: Cortex-A9, using DAP, configuring only one core
 # Base addresses of cores:
@@ -54,7 +75,7 @@ proc imx6_dbginit {target} {
 }
 
 # Slow speed to be sure it will work
-adapter_khz 1000
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
 
 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"