X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fesp32s3.cfg;fp=tcl%2Ftarget%2Fesp32s3.cfg;h=42b2199633b54a7f8460a42fc62f701db3c174de;hb=bea4d6590356f4a9ef0bcb6b270943e565852f0e;hp=a25dc145c5f37cdb1b1063bea9a9bdcb33649dbb;hpb=7dc4be3157d666ef05905151b7b4d0f05778b08a;p=fw%2Fopenocd

diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
index a25dc145c..42b219963 100644
--- a/tcl/target/esp32s3.cfg
+++ b/tcl/target/esp32s3.cfg
@@ -7,6 +7,9 @@ set CPU_MAX_ADDRESS 0xFFFFFFFF
 source [find bitsbytes.tcl]
 source [find memory.tcl]
 source [find mmr_helpers.tcl]
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
+
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
@@ -96,6 +99,29 @@ if { $_ONLYCPU != 1 } {
 
 $_TARGETNAME_0 xtensa maskisr on
 $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+$_TARGETNAME_0 configure -event examine-end {
+	# Need to enable to set 'semihosting_basedir'
+	arm semihosting enable
+	arm semihosting_resexit enable
+	if { [info exists _SEMIHOST_BASEDIR] } {
+		if { $_SEMIHOST_BASEDIR != "" } {
+			arm semihosting_basedir $_SEMIHOST_BASEDIR
+		}
+	}
+}
+
+if { $_ONLYCPU != 1 } {
+	$_TARGETNAME_1 configure -event examine-end {
+		# Need to enable to set 'semihosting_basedir'
+		arm semihosting enable
+		arm semihosting_resexit enable
+		if { [info exists _SEMIHOST_BASEDIR] } {
+			if { $_SEMIHOST_BASEDIR != "" } {
+				arm semihosting_basedir $_SEMIHOST_BASEDIR
+			}
+		}
+	}
+}
 
 $_TARGETNAME_0 configure -event gdb-attach {
 	$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut