X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fdavinci.cfg;h=9e9369dc185c7c35fd16f0ec66f339b37b587df1;hb=94fa8fd30ae5fd29529f401e123864565591e2ed;hp=b736c6ef397db04259d881fc5997766b455d165a;hpb=98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db;p=fw%2Fopenocd

diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index b736c6ef3..9e9369dc1 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -7,20 +7,7 @@ proc davinci_pinmux {soc reg value} {
 	mww [expr [dict get $soc sysbase] + 4 * $reg] $value
 }
 
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
-
-# mmw: "memory modify word", updates value of $reg
-#	$reg <== ((value & ~$clearbits) | $setbits)
-proc mmw {reg setbits clearbits} {
-	set old [mrw $reg]
-	set new [expr ($old & ~$clearbits) | $setbits]
-	mww $reg $new
-}
+source [find mem_helper.tcl]
 
 #
 # pll_setup: initialize PLL
@@ -197,63 +184,89 @@ proc pll_v03_setup {pll_addr mult config} {
 	# 11 - optional:  set plldiv1, plldiv2, ...
 	# NOTE:  this assumes some registers have their just-reset values:
 	#	- PLLSTAT.GOSTAT is clear when we enter
-	#	- ALNCTL has everything set
 	set aln 0
 	if { [dict exists $config div1] } {
 		set div [dict get $config div1]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0118] $div
 		set aln [expr $aln | 0x1]
+	} else {
+		mww [expr $pll_addr + 0x0118] 0
 	}
 	if { [dict exists $config div2] } {
 		set div [dict get $config div2]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x011c] $div
 		set aln [expr $aln | 0x2]
+	} else {
+		mww [expr $pll_addr + 0x011c] 0
 	}
 	if { [dict exists $config div3] } {
 		set div [dict get $config div3]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0120] $div
 		set aln [expr $aln | 0x4]
+	} else {
+		mww [expr $pll_addr + 0x0120] 0
+	}
+	if { [dict exists $config oscdiv] } {
+		set div [dict get $config oscdiv]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x0124] $div
+	} else {
+		mww [expr $pll_addr + 0x0124] 0
 	}
 	if { [dict exists $config div4] } {
 		set div [dict get $config div4]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0160] $div
 		set aln [expr $aln | 0x8]
+	} else {
+		mww [expr $pll_addr + 0x0160] 0
 	}
 	if { [dict exists $config div5] } {
 		set div [dict get $config div5]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0164] $div
 		set aln [expr $aln | 0x10]
+	} else {
+		mww [expr $pll_addr + 0x0164] 0
 	}
 	if { [dict exists $config div6] } {
 		set div [dict get $config div6]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0168] $div
 		set aln [expr $aln | 0x20]
+	} else {
+		mww [expr $pll_addr + 0x0168] 0
 	}
 	if { [dict exists $config div7] } {
 		set div [dict get $config div7]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x016c] $div
 		set aln [expr $aln | 0x40]
+	} else {
+		mww [expr $pll_addr + 0x016c] 0
 	}
 	if { [dict exists $config div8] } {
 		set div [dict get $config div8]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0170] $div
 		set aln [expr $aln | 0x80]
+	} else {
+		mww [expr $pll_addr + 0x0170] 0
 	}
 	if { [dict exists $config div9] } {
 		set div [dict get $config div9]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0174] $div
 		set aln [expr $aln | 0x100]
+	} else {
+		mww [expr $pll_addr + 0x0174] 0
 	}
 	if {$aln != 0} {
+		# clear pllcmd.GO
+		mww [expr $pll_addr + 0x0138] 0x00
 		# write alingment flags
 		mww [expr $pll_addr + 0x0140] $aln
 		# write pllcmd.GO; poll pllstat.GO