X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fc100config.tcl;h=2545fa790caf3490321227f5e9b91eaa1010adc9;hb=e6505b04892ccacf75603c3d173616f5d92809e7;hp=f020f96eee1c0813c002a46b643621840a63dc52;hpb=b4acbee47fcb29afc9958b4a9e74b9916a415dec;p=fw%2Fopenocd diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index f020f96ee..2545fa790 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -1,21 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later -# board(-config) specfic parameters file. +# board(-config) specific parameters file. # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ] proc config {label} { - return [dict get [configC100] $label ] + return [dict get [configC100] $label ] } # show the value for the param. with label proc showconfig {label} { - puts [format "0x%x" [dict get [configC100] $label ]] + echo [format "0x%x" [dict get [configC100] $label ]] } # Telo board config # when there are more then one board config # use soft links to c100board-config.tcl # so that only the right board-config gets -# included (just like include/configs/board-configs.h +# included (just like include/configs/board-configs.h # in u-boot. proc configC100 {} { # xtal freq. 24MHz @@ -26,32 +27,46 @@ proc configC100 {} { dict set configC100 w_amba 1 dict set configC100 x_amba 1 # y = amba_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] + dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] - # Arm Clk 450MHz, must be a multiple of 25 MHz + # Arm Clk 450MHz, must be a multiple of 25 MHz dict set configC100 CFG_ARM_CLOCK 450000000 dict set configC100 w_arm 0 dict set configC100 x_arm 1 # y = arm_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] + dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] } +# This should be called for reset init event handler +proc setupTelo {} { + + # setup GPIO used as control signals for C100 + setupGPIO + # This will allow access to lower 8MB or NOR + lowGPIO5 + # setup NOR size,timing,etc. + setupNOR + # setup internals + PLL + DDR2 + initC100 +} + + proc setupNOR {} { - puts "Setting up NOR: 16MB, 16-bit wide bus, CS0" + echo "Setting up NOR: 16MB, 16-bit wide bus, CS0" # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init() - set EX_CSEN_REG [regs EX_CSEN_REG ] - set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] - set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] - set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] - set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] - set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] + set EX_CSEN_REG [regs EX_CSEN_REG ] + set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] + set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] + set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] + set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] + set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] - set EX_MFSM_REG [regs EX_MFSM_REG ] - set EX_CSFSM_REG [regs EX_CSFSM_REG ] - set EX_WRFSM_REG [regs EX_WRFSM_REG ] - set EX_RDFSM_REG [regs EX_RDFSM_REG ] + set EX_MFSM_REG [regs EX_MFSM_REG ] + set EX_CSFSM_REG [regs EX_CSFSM_REG ] + set EX_WRFSM_REG [regs EX_WRFSM_REG ] + set EX_RDFSM_REG [regs EX_RDFSM_REG ] # enable Expansion Bus Clock + CS0 (NOR) mww $EX_CSEN_REG 0x3 @@ -62,17 +77,17 @@ proc setupNOR {} { # set timings to NOR mww $EX_CS0_TMG1_REG 0x03034006 mww $EX_CS0_TMG2_REG 0x04040002 - #mww $EX_CS0_TMG3_REG + #mww $EX_CS0_TMG3_REG # set EBUS clock 165/5=33MHz mww $EX_CLOCK_DIV_REG 0x5 - # everthing else is OK with default + # everything else is OK with default } proc bootNOR {} { set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] set BLOCK_RESET_REG [regs BLOCK_RESET_REG] set DDR_RST [regs DDR_RST] - + # put DDR controller in reset (so that it comes reset in u-boot) mmw $BLOCK_RESET_REG 0x0 $DDR_RST # setup CS0 controller for NOR @@ -85,7 +100,7 @@ proc bootNOR {} { resume } proc setupGPIO {} { - puts "Setting up GPIO block for Telo" + echo "Setting up GPIO block for Telo" # This is current setup for Telo (see sch. for details): #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup #GPIO1 irq line for FXS-FXO @@ -93,71 +108,137 @@ proc setupGPIO {} { #GPIO17 reset for DECT module. #GPIO29 CS_n for NAND - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] - set GPIO_OE_REG [regs GPIO_OE_REG] + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + set GPIO_OE_REG [regs GPIO_OE_REG] # set GPIO29=GPIO17=1, GPIO5=0 - mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] + mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}] # enable [as output] GPIO29,GPIO17,GPIO5 - mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5] + mww $GPIO_OE_REG [expr {1<<29 | 1<<17 | 1<<5}] } proc highGPIO5 {} { - puts "GPIO5 high" - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + echo "GPIO5 high" + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=1 - mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 + mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0 } proc lowGPIO5 {} { - puts "GPIO5 low" - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + echo "GPIO5 low" + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=0 - mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] + mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}] } proc boardID {id} { # so far built: # 4'b1111 - dict set boardID 15 name "EVT1" + dict set boardID 15 name "EVT1" dict set boardID 15 ddr2size 128M # dict set boardID 15 nandsize 1G # dict set boardID 15 norsize 16M # 4'b0000 - dict set boardID 0 name "EVT2" + dict set boardID 0 name "EVT2" dict set boardID 0 ddr2size 128M # 4'b0001 - dict set boardID 1 name "EVT3" + dict set boardID 1 name "EVT3" dict set boardID 1 ddr2size 256M # 4'b1110 dict set boardID 14 name "EVT3_old" dict set boardID 14 ddr2size 128M # 4'b0010 - dict set boardID 2 name "EVT4" + dict set boardID 2 name "EVT4" dict set boardID 2 ddr2size 256M return $boardID } + # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect() -# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors +# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors proc ooma_board_detect {} { set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] - - # read the current value of the BOOTSRAP pins + + # read the current value of the BOOTSTRAP pins set tmp [mrw $GPIO_BOOTSTRAP_REG] - puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] + echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] # extract the GPBP bits - set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3] + set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}] # display board ID - puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt] + echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt] + # show it on serial console + putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt] # return the ddr2 size, used to configure DDR2 on a given board. return [dict get [boardID $gpbt] $gpbt ddr2size] } proc configureDDR2regs_256M {} { - puts "ConfigureDDR2regs_256M TBD" + + set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] + set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] + set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] + set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA] + set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA] + set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA] + set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA] + set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA] + set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA] + set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA] + set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA] + set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA] + set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA] + set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA] + set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA] + set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA] + set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA] + set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA] + set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA] + set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA] + set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] + + set DENALI_CTL_02_VAL 0x0100000000010100 + set DENALI_CTL_11_VAL 0x433a32164a560a00 + + mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 + # 01_DATA mod [40]=1, enable BA2 + mw64bit $DENALI_CTL_01_DATA 0x0100010100000001 + mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL + mw64bit $DENALI_CTL_03_DATA 0x0102020202020201 + mw64bit $DENALI_CTL_04_DATA 0x0000010100000001 + mw64bit $DENALI_CTL_05_DATA 0x0203010300010101 + mw64bit $DENALI_CTL_06_DATA 0x060a020200020202 + mw64bit $DENALI_CTL_07_DATA 0x0000000300000206 + mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209 + mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a + mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18 + # 11_DATA mod [39-32]=16,more refresh + mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL + mw64bit $DENALI_CTL_12_DATA 0x0000000000000800 + mw64bit $DENALI_CTL_13_DATA 0x0010002000100040 + mw64bit $DENALI_CTL_14_DATA 0x0010004000100040 + mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000 + mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000 + mw64bit $DENALI_CTL_17_DATA 0x0000000000000000 + mw64bit $DENALI_CTL_18_DATA 0x0302000000000000 + mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600 + mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8 + + set wr_dqs_shift 0x40 + # start DDRC + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] + # wait int_status[2] (DRAM init complete) + echo -n "Waiting for DDR2 controller to init..." + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { + sleep 1 + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + } + echo "done." + + # do ddr2 training sequence + # TBD (for now, if you need it, run trainDDR command) } # converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99() @@ -187,9 +268,9 @@ proc configureDDR2regs_128M {} { set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] - set DENALI_CTL_02_VAL 0x0100010000010100 + set DENALI_CTL_02_VAL 0x0100010000010100 set DENALI_CTL_11_VAL 0x433A42124A650A37 - # set some default values + # set some default values mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 mw64bit $DENALI_CTL_01_DATA 0x0100000100000101 mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL @@ -214,16 +295,17 @@ proc configureDDR2regs_128M {} { set wr_dqs_shift 0x40 # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] # wait int_status[2] (DRAM init complete) - puts -nonewline "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + echo -n "Waiting for DDR2 controller to init..." + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] } - mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ] - puts "done." + # This is not necessary + #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ] + echo "done." # do ddr2 training sequence # TBD (for now, if you need it, run trainDDR command) @@ -237,18 +319,18 @@ proc setupUART0 {} { set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0] - set UART0_LCR [regs UART0_LCR] - set LCR_DLAB [regs LCR_DLAB] - set UART0_DLL [regs UART0_DLL] - set UART0_DLH [regs UART0_DLH] - set UART0_IIR [regs UART0_IIR] - set UART0_IER [regs UART0_IER] - set LCR_ONE_STOP [regs LCR_ONE_STOP] - set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] + set UART0_LCR [regs UART0_LCR] + set LCR_DLAB [regs LCR_DLAB] + set UART0_DLL [regs UART0_DLL] + set UART0_DLH [regs UART0_DLH] + set UART0_IIR [regs UART0_IIR] + set UART0_IER [regs UART0_IER] + set LCR_ONE_STOP [regs LCR_ONE_STOP] + set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] set FCR_XMITRES [regs FCR_XMITRES] - set FCR_RCVRRES [regs FCR_RCVRRES] - set FCR_FIFOEN [regs FCR_FIFOEN] - set IER_UUE [regs IER_UUE] + set FCR_RCVRRES [regs FCR_RCVRRES] + set FCR_FIFOEN [regs FCR_FIFOEN] + set IER_UUE [regs IER_UUE] # unlock writing to IOCTRL register mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL @@ -260,28 +342,28 @@ proc setupUART0 {} { # Enable Divisor Latch access mmw $UART0_LCR $LCR_DLAB 0x0 # set the divisor to $tmp - mww $UART0_DLL [expr $tmp & 0xff] - mww $UART0_DLH [expr $tmp >> 8] + mww $UART0_DLL [expr {$tmp & 0xff}] + mww $UART0_DLH [expr {$tmp >> 8}] # Disable Divisor Latch access mmw $UART0_LCR 0x0 $LCR_DLAB # set the UART to 8N1 - mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0 + mmw $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0 # reset FIFO - mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0 + mmw $UART0_IIR [expr {$FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0 # enable FFUART mww $UART0_IER $IER_UUE } proc putcUART0 {char} { - set UART0_LSR [regs UART0_LSR] + set UART0_LSR [regs UART0_LSR] set UART0_THR [regs UART0_THR] set LSR_TEMT [regs LSR_TEMT] # convert the 'char' to digit set tmp [ scan $char %c ] # /* wait for room in the tx FIFO on FFUART */ - while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 } + while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 } mww $UART0_THR $tmp if { $char == "\n" } { putcUART0 \r } } @@ -291,7 +373,7 @@ proc putsUART0 {str} { set len [string length $str] while { $index < $len } { putcUART0 [string index $str $index] - set index [expr $index + 1] + set index [expr {$index + 1}] } } @@ -308,17 +390,24 @@ proc trainDDR2 {} { resume } -proc flashUBOOT {} { +proc flashUBOOT {file} { # this will update uboot on NOR partition set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] - + # setup CS0 controller for NOR setupNOR # make sure we are accessing the lower part of NOR lowGPIO5 flash probe 0 - puts "Erasing sectors 0-3 for uboot" + echo "Erasing sectors 0-3 for uboot" + putsUART0 "Erasing sectors 0-3 for uboot\n" flash erase_sector 0 0 3 - puts "Programming u-boot, takes about 4-5 min for 256kb" - flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR -} \ No newline at end of file + echo "Programming u-boot" + putsUART0 "Programming u-boot..." + arm11 memwrite burst enable + flash write_image $file $EXP_CS0_BASEADDR + arm11 memwrite burst disable + putsUART0 "done.\n" + putsUART0 "Rebooting, please wait!\n" + reboot +}