X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fatsamv.cfg;h=fdd835473c6b44d246f76635d91a0946d9e549cb;hb=4ddca7dd7186a908397570a25f7ad7454bab3a20;hp=1d026aa958bc442cefc90f258acbe4e86e07d0d1;hpb=6823a97beb706a5a3a4b7f813d33a7f3faadf2f0;p=fw%2Fopenocd

diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index 1d026aa95..fdd835473 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -39,21 +39,21 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-adapter_khz 1800
+adapter speed 1800
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
-
-# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
-# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
-# makes the data access cacheable. This allows reading and writing data in the
-# CPU cache from the debugger, which is far more useful than going straight to
-# RAM when operating on typical variables, and is generally no worse when
-# operating on special memory locations.
-$_CHIPNAME.dap apcsw 0x08000000 0x08000000