X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fatsamv.cfg;h=7e9f6c57ef6341fc04d22e59e357b048419a033b;hb=e6505b04892ccacf75603c3d173616f5d92809e7;hp=d1f8454d52498f1d3422168b18550ff18874d968;hpb=2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f;p=fw%2Fopenocd

diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index d1f8454d5..7e9f6c57e 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
 # The chips are very similar; the SAMV series just has
 # more peripherals and seems like the "flagship" of the
@@ -39,14 +41,21 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-adapter_khz 1800
+adapter speed 1800
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
+
+   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+   # makes the data access cacheable. This allows reading and writing data in the
+   # CPU cache from the debugger, which is far more useful than going straight to
+   # RAM when operating on typical variables, and is generally no worse when
+   # operating on special memory locations.
+   $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
-