X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Ftarget%2Fat91sam3XXX.cfg;h=7d01ccdb0c43210dd25c6e6eaae6dbc768038748;hb=9a6417e03595e1194f125ca33d2b60b8eac9a512;hp=517a871911179a666d6de89e39616263849d3dec;hpb=2986320cde399b0b0ee006a4fecbdec83bebc248;p=fw%2Fopenocd diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg index 517a87191..7d01ccdb0 100644 --- a/tcl/target/at91sam3XXX.cfg +++ b/tcl/target/at91sam3XXX.cfg @@ -1,4 +1,4 @@ -# script for ATMEL sam3, a CORTEX-M3 chip +# script for ATMEL sam3, a Cortex-M3 chip # # at91sam3u4e # at91sam3u2e @@ -16,35 +16,73 @@ # at91sam3s1c # at91sam3s1b # at91sam3s1a +# +# at91sam3A4C +# at91sam3A8C +# at91sam3X4C +# at91sam3X4E +# at91sam3X8C +# at91sam3X8E +# at91sam3X8H + +source [find target/swj-dp.tcl] if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME sam3 + set _CHIPNAME sam3 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} #jtag scan chain -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap # 16K is plenty, the smallest chip has this much -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 $_TARGETNAME configure -event gdb-flash-erase-start { halt } + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. + +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +}