X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fchip%2Fatmel%2Fat91%2Fat91sam9_init.cfg;h=688cb1f4c4d4a779faf12fbb82bc3e279f35c467;hb=f5657aa76e795e4ed5b13a9f5df943181a123e49;hp=47d22e0ac0cc1a838072bd34ff71ddf5fd3e34ec;hpb=ba71e8c521a7e7c1652560f580f81d564e613508;p=fw%2Fopenocd

diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg
index 47d22e0ac..688cb1f4c 100644
--- a/tcl/chip/atmel/at91/at91sam9_init.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_init.cfg
@@ -12,8 +12,8 @@ proc at91sam9_reset_start { } {
 	halt
 	wait_halt 10000
 	set rstc_mr_val [expr $::AT91_RSTC_KEY]
-	set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
-	set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+	set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
 	mww $::AT91_RSTC_MR $rstc_mr_val	;# RSTC_MR : enable user reset.
 }
 
@@ -21,14 +21,14 @@ proc at91sam9_reset_init { config } {
 
 	mww $::AT91_WDT_MR $config(wdt_mr_val)	;# disable watchdog
 
-	set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
+	set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
 
 	mww $::AT91_CKGR_MOR $ckgr_mor	;# CKGR_MOR - enable main osc.
 	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
 
 	set pllar_val	[expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
-	set pllar_val	[expr ($pllar_val | $::AT91_PMC_OUT)]
-	set pllar_val	[expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_OUT}]
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
 	set pllar_val	[expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
 	set pllar_val	[expr ($pllar_val | $config(master_pll_div))]
 
@@ -37,27 +37,36 @@ proc at91sam9_reset_init { config } {
 
 	;# PCK/2 = MCK Master Clock from PLLA
 	set mckr_val	[expr $::AT91_PMC_CSS_PLLA]
-	set mckr_val	[expr ($mckr_val | $::AT91_PMC_PRES_1)]
-	set mckr_val	[expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
-	set mckr_val	[expr ($mckr_val | $::AT91_PMC_PDIV_1)]
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PRES_1}]
+	set mckr_val	[expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PDIV_1}]
 
 	mww $::AT91_PMC_MCKR $mckr_val	;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
 	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
 
-	## switch JTAG clock to highseepd clock
+	## switch JTAG clock to highspeed clock
 	jtag_rclk 0
 
 	arm7_9 dcc_downloads enable	;# Enable faster DCC downloads
 	arm7_9 fast_memory_access enable
 
 	set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
-	set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
 	mww $::AT91_RSTC_MR $rstc_mr_val	;# user reset enable
 
-	set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
-	mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
-	set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
-	mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
+	if { [info exists config(sdram_piod)] } {
+		set pdr_addr	[expr {$::AT91_PIOD + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOD + $::PIO_PUDR}]
+		set asr_addr	[expr {$::AT91_PIOD + $::PIO_ASR}]
+		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
+		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
+		mww $asr_addr 0xffff0000
+	} else {
+		set pdr_addr	[expr {$::AT91_PIOC + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOC + $::PIO_PUDR}]
+		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
+		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
+	}
 
 	mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
 	mww $::AT91_SDRAMC_MR	$::AT91_SDRAMC_MODE_NORMAL	;# SDRAMC_MR Mode register