X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fuptech_2410.cfg;h=0a2c475f718ca0361edd5a940ea8933ffc7da66f;hb=57c61cee4b538b449421bc6ff8ebca5be70e60b1;hp=680cfd7d60419ba1eb8896b2c3c146081f755cd0;hpb=9e23c9ae3551dc14e15bdfe129fd9e03c6970f33;p=fw%2Fopenocd

diff --git a/tcl/board/uptech_2410.cfg b/tcl/board/uptech_2410.cfg
index 680cfd7d6..0a2c475f7 100644
--- a/tcl/board/uptech_2410.cfg
+++ b/tcl/board/uptech_2410.cfg
@@ -1,5 +1,5 @@
 # Target Configuration for the Uptech 2410 board.
-# This configuration hould also work on smdk2410, but I havn't tested it yet.
+# This configuration should also work on smdk2410, but I haven't tested it yet.
 # Author: xionglingfeng@Gmail.com
 
 source [find target/samsung_s3c2410.cfg]
@@ -11,28 +11,28 @@ proc init_pll_sdram { } {
 	#echo "---------- Initializing PLL and SDRAM ---------"
 	#watchdog timer disable
 	mww phys 0x53000000 0x00000000
-	
+
 	#disable all interrupts
 	mww phys 0x4a000008 0xffffffff
-	
+
 	#disable all sub-interrupts
 	mww phys 0x4a00001c 0x000007ff
-	
+
 	#clear all source pending bits
 	mww phys 0x4a000000 0xffffffff
-	
+
 	#clear all sub-source pending bits
 	mww phys 0x4a000018 0x000007ff
-	
+
 	#clear interrupt pending bit
 	mww phys 0x4a000010 0xffffffff
-	
+
 	#PLL locktime counter
 	mww phys 0x4c000000 0x00ffffff
-	
+
 	#Fin=12MHz Fout=202.8MHz
 	#mww phys 0x4c000004 0x000a1031
-	
+
 	#FCLK:HCLK:PCLK = 1:2:4
 	mww phys 0x4c000014 0x00000003