X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fphytec_lpc3250.cfg;h=cee28cdd26552cd49b0d6d33cca91a621ad4e9bf;hb=248161cbf47af9f7fc8c00b5efa79a1ff8e65848;hp=6a7e8e923b7c442daa74a14dcf0569c8d7352cb3;hpb=b559b273b526b3077b3ca219eecc8df9f86efac0;p=fw%2Fopenocd

diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index 6a7e8e923..cee28cdd2 100644
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -1,8 +1,8 @@
 source [find target/lpc3250.cfg]
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 1
-adapter_khz 200
+adapter speed 200
 reset_config trst_and_srst separate
 
 arm7_9 dcc_downloads enable
@@ -11,11 +11,11 @@ $_TARGETNAME configure -event gdb-attach { reset init }
 
 $_TARGETNAME configure -event reset-start {
              arm7_9 fast_memory_access disable
-             adapter_khz 200
+             adapter speed 200
 }
 
 $_TARGETNAME configure -event reset-end {
-             adapter_khz 6000
+             adapter speed 6000
              arm7_9 fast_memory_access enable
 }
 
@@ -23,12 +23,12 @@ $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
 
 # Bare-bones initialization of core clocks and SDRAM
 proc phytec_lpc3250_init { } {
-        # Set clock dividers 
+        # Set clock dividers
         #   ARMCLK = 266.5 MHz
         #   HCLK   = 133.25 MHz
         #   PERIPHCLK = 13.325 MHz
         mww 0x400040BC 0
-        mww 0x40004050 0x140        
+        mww 0x40004050 0x140
         mww 0x40004040 0x4D
         mww 0x40004058 0x16250
 
@@ -37,7 +37,7 @@ proc phytec_lpc3250_init { } {
         sleep 1 busy
         mww 0x40004044 0x106
         sleep 1 busy
-        mww 0x40004044 0x006        
+        mww 0x40004044 0x006
         sleep 1 busy
         mww 0x40004048 0x2
 
@@ -49,7 +49,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080008 0
         mww 0x40004068 0x1C000
         mww 0x31080028 0x11
-        
+
         mww 0x31080400 0
         mww 0x31080440 0
         mww 0x31080460 0
@@ -66,7 +66,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080054 1
         mww 0x31080058 1
         mww 0x3108005C 0
-        
+
         mww 0x31080100 0x5680
         mww 0x31080104 0x302