X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fphytec_lpc3250.cfg;h=036b16f2bb394ce21685726848f289c0c8cbda28;hb=4157732bd84c4e9e4b55357e1dc9a96078a35ee1;hp=1c48f5df7072b137b098014ca079d3cd74882469;hpb=38ac08c1c25adf42cf20e48e10e6ddeab6a12d71;p=fw%2Fopenocd

diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index 1c48f5df7..036b16f2b 100644
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/lpc3250.cfg]
 
 adapter srst delay 200
@@ -23,12 +25,12 @@ $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
 
 # Bare-bones initialization of core clocks and SDRAM
 proc phytec_lpc3250_init { } {
-        # Set clock dividers 
+        # Set clock dividers
         #   ARMCLK = 266.5 MHz
         #   HCLK   = 133.25 MHz
         #   PERIPHCLK = 13.325 MHz
         mww 0x400040BC 0
-        mww 0x40004050 0x140        
+        mww 0x40004050 0x140
         mww 0x40004040 0x4D
         mww 0x40004058 0x16250
 
@@ -37,7 +39,7 @@ proc phytec_lpc3250_init { } {
         sleep 1 busy
         mww 0x40004044 0x106
         sleep 1 busy
-        mww 0x40004044 0x006        
+        mww 0x40004044 0x006
         sleep 1 busy
         mww 0x40004048 0x2
 
@@ -49,7 +51,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080008 0
         mww 0x40004068 0x1C000
         mww 0x31080028 0x11
-        
+
         mww 0x31080400 0
         mww 0x31080440 0
         mww 0x31080460 0
@@ -66,7 +68,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080054 1
         mww 0x31080058 1
         mww 0x3108005C 0
-        
+
         mww 0x31080100 0x5680
         mww 0x31080104 0x302