X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fimx35pdk.cfg;h=2a7efaba7ef82a73951c47f9a051c51e361f36bf;hb=e5f515f990cc345fd3089a5520f39d5a128329bd;hp=b81c0b01cc2a3a715e0ea7af0e8e56eed1cd71ea;hpb=6d3cb807aaa60c4a4cd8ed49ae7860097bc1b3ce;p=fw%2Fopenocd

diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index b81c0b01c..2a7efaba7 100644
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -8,9 +8,9 @@ $_TARGETNAME configure -event reset-init { imx35pdk_init }
 jtag_rclk 10
 
 proc imx35pdk_init { } {
-	
+
 	imx3x_reset
-	
+
 	mww 0x43f00040 0x00000000
 	mww 0x43f00044 0x00000000
 	mww 0x43f00048 0x00000000
@@ -25,11 +25,11 @@ proc imx35pdk_init { } {
 	mww 0x53f00050 0x00000000
 	mww 0x53f00000 0x77777777
 	mww 0x53f00004 0x77777777
-	
+
 	# clock setup
 	mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
 	mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
-	
+
 	#=================================================
 	# WEIM config
 	#=================================================
@@ -45,14 +45,14 @@ proc imx35pdk_init { } {
 	mww 0xB8002054 0x444a4541
 	# CS5A
 	mww 0xB8002058 0x44443302
-	
+
 	# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
 	mww 0x43FAC368 0x00000006
 	mww 0x43FAC36C 0x00000006
 	mww 0x43FAC370 0x00000006
 	mww 0x43FAC374 0x00000006
 	mww 0x43FAC378 0x00000006
-	mww 0x43FAC37C 0x00000006	
+	mww 0x43FAC37C 0x00000006
 	mww 0x43FAC380 0x00000006
 	mww 0x43FAC384 0x00000006
 	mww 0x43FAC388 0x00000006
@@ -76,7 +76,7 @@ proc imx35pdk_init { } {
 	mww 0x43FAC3D0 0x00000006
 	mww 0x43FAC3D4 0x00000006
 	mww 0x43FAC3D8 0x00000006
-	
+
 	# DDR data bus SD 0 through 31
 	mww 0x43FAC3DC 0x00000082
 	mww 0x43FAC3E0 0x00000082
@@ -110,13 +110,13 @@ proc imx35pdk_init { } {
 	mww 0x43FAC450 0x00000082
 	mww 0x43FAC454 0x00000082
 	mww 0x43FAC458 0x00000082
-	
+
 	# DQM setup
 	mww 0x43FAC45c 0x00000082
 	mww 0x43FAC460 0x00000082
 	mww 0x43FAC464 0x00000082
 	mww 0x43FAC468 0x00000082
-	
+
 	mww 0x43FAC46c 0x00000006
 	mww 0x43FAC470 0x00000006
 	mww 0x43FAC474 0x00000006
@@ -130,30 +130,30 @@ proc imx35pdk_init { } {
 	mww 0x43FAC494 0x00000006
 	mww 0x43FAC498 0x00000006
 	mww 0x43FAC49c 0x00000006
-	mww 0x43FAC4A0 0x00000006	
+	mww 0x43FAC4A0 0x00000006
 	mww 0x43FAC4A4 0x00000006	;# RAS
 	mww 0x43FAC4A8 0x00000006	;# CAS
 	mww 0x43FAC4Ac 0x00000006	;# SDWE
 	mww 0x43FAC4B0 0x00000006 	;# SDCKE0
 	mww 0x43FAC4B4 0x00000006  ;# SDCKE1
 	mww 0x43FAC4B8 0x00000002  ;# SDCLK
-	
+
 	# SDQS0 through SDQS3
 	mww 0x43FAC4Bc 0x00000082
 	mww 0x43FAC4C0 0x00000082
 	mww 0x43FAC4C4 0x00000082
 	mww 0x43FAC4C8 0x00000082
-	
-	
+
+
 	# *==================================================
 	#  Initialization script for 32 bit DDR2 on RINGO 3DS
 	# *==================================================
-	
+
 	#--------------------------------------------
 	# Init CCM
 	#--------------------------------------------
 	mww 0x53F80028 0x7D000028
-	
+
 	#--------------------------------------------
 	# Init IOMUX for JTAG
 	#--------------------------------------------
@@ -164,24 +164,24 @@ proc imx35pdk_init { } {
 	mww 0x43FAC5FC 0x000000F3
 	mww 0x43FAC600 0x000000F3
 	mww 0x43FAC604 0x000000F3
-	
-	
+
+
 	# ESD_MISC : enable DDR2
 	mww 0xB8001010 0x00000304
-	
+
 	#--------------------------------------------
 	# Init 32-bit DDR2 memory on CSD0
 	# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
 	#--------------------------------------------
-	
+
 	# ESD_ESDCFG0 : set timing parameters
-	mww 0xB8001004 0x007ffC2f	
-	
+	mww 0xB8001004 0x007ffC2f
+
 	# ESD_ESDCTL0 : select Prechare-All mode
 	mww 0xB8001000 0x92220000
 	# DDR2 : Prechare-All
 	mww 0x80000400 0x12345678
-	
+
 	# ESD_ESDCTL0 : select Load-Mode-Register mode
 	mww 0xB8001000 0xB2220000
 	# DDR2 : Load reg EMR2
@@ -192,18 +192,18 @@ proc imx35pdk_init { } {
 	mwb 0x82000400 0xda
 	# DDR2 : Load reg MR -- reset DLL
 	mwb 0x80000333 0xda
-	
+
 	# ESD_ESDCTL0 : select Prechare-All mode
 	mww 0xB8001000 0x92220000
 	# DDR2 : Prechare-All
 	mwb 0x80000400 0x12345678
-	
+
 	# ESD_ESDCTL0 : select Manual-Refresh mode
 	mww 0xB8001000 0xA2220000
 	# DDR2 : Manual-Refresh 2 times
 	mww 0x80000000 0x87654321
 	mww 0x80000000 0x87654321
-	
+
 	# ESD_ESDCTL0 : select Load-Mode-Register mode
 	mww 0xB8001000 0xB2220000
 	# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
@@ -212,19 +212,19 @@ proc imx35pdk_init { } {
 	mwb 0x82000780 0xda
 	# DDR2 : Load reg EMR1 -- OCD exit
 	mwb 0x82000400 0xda	;# ODT disabled
-	
+
 	# ESD_ESDCTL0 : select normal-operation mode
 	# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
 	# disable PWT & PRCT
 	# disable Auto-Refresh
 	mww 0xB8001000 0x82220080
-	
+
 	## ESD_ESDCTL0 : enable Auto-Refresh
 	mww 0xB8001000 0x82228080
 	## ESD_ESDCTL1 : enable Auto-Refresh
 	mww 0xB8001008 0x00002000
-	
-	
+
+
 	#***********************************************
 	# Adjust the ESDCDLY5 register
 	#***********************************************
@@ -233,20 +233,20 @@ proc imx35pdk_init { } {
 	mww 0xB8001024 0x00F48000	;# this is the default value
 	mww 0xB8001028 0x00F48000	;# this is the default value
 	mww 0xB800102c 0x00F48000	;# this is the default value
-	
-	
+
+
 	#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
 	mww 0xB8001010 0x00000384
 	# wait a while
 	sleep 1000
 	# now clear the force measurement bit
 	mww 0xB8001010 0x00000304
-	
+
 	# dummy write to DDR memory to set DQS low
 	mww 0x80000000 0x00000000
-	
+
 	mww 0x30000100 0x0
 	mww 0x30000104 0x31024
-	
-	
+
+
 }