X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fhilscher_nxhx10.cfg;h=6e2eba79ebae0fe3557b890408ec8889925db9af;hb=70338509ca52a9b78c52a5d464ba2605fbaf193b;hp=4a6b972ac5dd5d7c8b2696f19bd711e9a06721eb;hpb=6839618062f07a12bd969da8dc54546f96938b67;p=fw%2Fopenocd

diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
index 4a6b972ac..6e2eba79e 100644
--- a/tcl/board/hilscher_nxhx10.cfg
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -9,7 +9,7 @@ source [find target/hilscher_netx10.cfg]
 # problems try to line below
 # reset_config trst_and_srst srst_pulls_trst
 reset_config trst_and_srst
-jtag_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
@@ -26,15 +26,13 @@ proc flash_init { } {
 }
 
 proc mread32 {addr} {
-  set value(0) 0
-  mem2array value 32 $addr 1
-  return $value(0)
+  return [read_memory $addr 32 1]
 }
 
 proc init_clocks { } {
   puts "Enabling all clocks "
   set accesskey [mread32 0x101c0070]
-  mww  0x101c0070 [expr $accesskey]
+  mww  0x101c0070 $accesskey
 
   mww  0x101c0028 0x00007511
 }
@@ -42,7 +40,7 @@ proc init_clocks { } {
 proc init_sdrambus { } {
   puts "Initializing external SDRAM Bus 16 Bit "
   set accesskey [mread32 0x101c0070]
-  mww  0x101c0070 [expr $accesskey]
+  mww  0x101c0070 $accesskey
   mww  0x101c0C40 0x00000050
 
   puts "Configuring SDRAM controller for K4S561632E (32MB) "
@@ -79,4 +77,4 @@ $_TARGETNAME configure -event reset-init {
 #flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
 
 init
-reset init
\ No newline at end of file
+reset init